JPS6322400B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dummy cell circuit for a semiconductor memory device, particularly a field programmable element such as a PROM.

The same is true for ROM, but in PROM (programmable read-only memory) all storage (memory) cells are in an on or off state until they are written to, so it is almost impossible to test the normality or abnormality of wiring and peripheral circuits. It's almost impossible. Therefore, if two rows of test bits and two test words are provided in the memory cell section and test patterns are written to them, almost all types of tests can be performed, which is very effective in guaranteeing the quality of PROMs. be.
However, subsequent research has shown that this separately proposed method is inconvenient for failures where there is a leak in the circuit and the leak has a threshold. The present invention aims to improve this point, and includes a test bit in the memory cell section that stores information depending on whether or not the bit line and word line are short-circuited. In a programmable read-only semiconductor memory device in which information is written by applying a higher voltage than when reading, at least one unconnected memory cell that constitutes the test bit is not short-circuited between the bit line and the word line. A feature of the present invention is that the write memory cell is made larger than other memory cells so that a test can be performed with a write voltage and a write current applied. Next, this will be explained in detail with reference to examples.

As shown in Figure 1, PROM is a memory cell section.
CELL, the word line of the cell section is selected by the X address inverter ADD and the decoder driver D/D, and the bit line is selected by the Y address inverter ADD and the multiplexer MPX, and each bit of the read word line is 1, 0. Output information from output circuit OUT. PRG is a programming circuit used during writing. There are two rows of test bits TB ₁ in this memory cell section CELL,
TB ₂ and two test words TW ₁ and TW ₂ are provided. (If there is no need to distinguish between the test words, they are also called test bits.) If a test pattern is written to these, the H and L levels of the output voltage can be determined.
V _OH , V _OL , output leakage current after writing I _OLK ,
DC characteristics such as short circuit current I _OS at H level, and output status are H, L, Z (Z is an abbreviation of high impedance, this type of output circuit is equipped with an off buffer, and the output is H, L, Z). The mutual switching time t _PHL , t _PLH , t _PHZ , t _PLZ ,
t _PZH , t _PZL (t _P is propagation time, HL,
LH, etc. indicates switching from H to L, L to H, etc.)
It is possible to test not only the AC characteristics such as but also the write current absorption ability of the word decoder driver.

The ability to absorb this write current, etc. is tested as follows. That is, in Fig. 2, B ₁ , B ₂ ... are bit lines,
W ₁ , W ₂ ... are word lines, 11, 21, 31 ...
12, 22, 32... are test bits TB ₁ , TB ₂
Memory cells corresponding to 10, 20, . . . are bit lines B ₁ , B ₂ corresponding to the programming circuit PROG.
. . . selection transistors, D ₁ , D ₂ . . . are X decoder drivers for word line selection, and 30 and 40 are inverters corresponding to Y address inverters ADD. In this example, the memory cell is composed of an npn transistor, and writing is performed by flowing a large current from the bit line to the word line to short-circuit (destroy) the emitter-base junction. Short circuit (destruction) of emitter-base junction
Then the transistor becomes just a diode,
Therefore, in FIG. 2, written memory cells are shown as diodes. Therefore, test bit TB ₁ of this PROM is written as 1010... and TB ₂ is written with the opposite value.
0101... is written. In this way, the decoder drivers D ₁ , D ₂ , consisting of NAND gates...
The outputs of ... are sequentially set to L level and the word lines W ₁ , W ₂
..., select bit line _B1 to memory cell 11,
Word lines W ₁ , W ₂ , W ₃ through 21, 31...
By checking the current flowing to . . _. and finding that it is 1010 . . . , it is possible to know whether _the X address selection system is normal.
Try passing a large current equivalent to the write current into W ₁ , W ₂ ... (this current flows into the output terminals of the decoder drivers D ₁ , D ₂ ... that are in the L level output state) and check the current absorption capacity of the drivers. You can check. However, in this test, a write current of about 200mA is applied through the written cells, so the voltage may be low. To give a numerical example, if the potential of word line _W1 is 1V in the selected state, the bit line
If the potential of B ₁ is set to 2V, written memory cell 1
A current of 200mA can be passed through driver D1 through _D1 . On the other hand, in order to write to an unwritten cell, it is necessary to raise the bit line potential to about 8V, and in this way, since the emitter-base breakdown voltage is about 7V, this breakdown voltage will be broken and the emitter current will be about 200mA. By continuing this for a suitable period of time, the emitter-base junction is destroyed and shot, resulting in a write state.

By the way, raising the bit line potential means increasing the power supply voltage _V0 , and naturally the base potential must also be raised. In other words, the collector, base, and emitter circuits of the transistors 10, 20, . . . all receive high voltage. Therefore, if there is a leak in these circuit systems, especially in the base circuit system, a sufficient base current will not be supplied, and the transistors 10, 20, . . . will enter the saturation region.
If this leakage is linear as shown by the resistor 52, for example, when the potential of the bit line _B2 is set to 2V and the current absorption ability of the driver _D2 is examined through the written cell 22, the base current will pass through the resistor. However, as shown by the zener diode 51, leakage has a threshold value and does not occur at all up to a certain potential, as shown by the Zener diode 51. This leakage will not be detected at all when checking the driver current absorption ability at a low voltage using a written cell. Figure 3 is a diagram explaining this.
V ₀ and I ₀ are the output voltage and current, C ₁ is the cell before writing, and C ₂ is each V ₀ -I ₀ characteristic of the cell after writing.
Note that since this writing is performed from the output circuit OUT (FIG. 1) side, the writing voltage and writing current are also called output voltage and output current. When the base current decreases due to leakage and the emitter current enters the saturation region, the curves C ₁ and C ₂ become C ₁₁ , C ₁₂ , C ₂₁ , and C ₂₂ . Assuming that the required write current is I _W , when checking using the cell after writing, the voltage V ₀ is changed to V ₀₁
(approximately 2V as described above) and check the current absorption ability by flowing a current higher than the write current _IW , the saturation due to leakage has just begun and no modulation is applied to the 200mA supply, so leakage cannot be detected. Moreover, when the user attempts to write desired data to the cell before writing and sets V ₀ = 8V (= V ₀₂ ), the current
The current is limited as shown by _C12 , and writing is impossible because a predetermined write current _IW cannot be obtained.

The present invention attempts to improve this point. Since the above-mentioned problem arises from the fact that the current absorption ability is checked at a low voltage, it is sufficient to make it possible to check at a high voltage, that is, the write voltage (8V). This is done by connecting a resistor 53 in series to the written cells 11, 22, etc., as shown by the dotted line in Figure 2, and making the voltage-current characteristics 200mA at 8V as shown in Figure 4. is one method. By doing this, if there is a leak, you will not be able to flow 200mA at 8V during the test, making it easy to check for leaks. Note that leaks whose threshold voltage is higher than the voltage received during writing cannot be checked by such a test, but since such a high voltage is not applied, there is no particular problem.

However, in the method of inserting a resistor, the resistor must be formed in the memory cell portion, which results in a complicated structure. Therefore, in the present invention, instead of inserting the resistor 53, the area of the unwritten cell is increased. An unwritten memory cell, for example 12, is represented by two diodes connected in anti-series, but a large-area cell is equivalent to a plurality of groups of such anti-series diodes connected in parallel, and such a group of diodes is write voltage,
Will not be destroyed even if a current of 8V, 200mA is applied (EB
(The breakdown voltage is the same as normal memory cells, but the allowable current amount is increased.) Therefore, it is possible to check the current absorption ability by applying a write voltage. Of course, since the voltage is high, any leaks mentioned above will be easily detected.

The transistor for bit line selection is 1 in Figure 2.
In this case, the output currents of the drivers 30 and 40 become considerably large. For example, if one driver handles 16 bit lines and the transistor β is 10, then 200/10×16=
320mA is required. This is an extremely large value for this type of circuit, so in practice a combination circuit of multiple transistors is used to reduce the driver output. FIG. 5 shows an example, in which the transistor 10 consists of transistors 10a and 10b in this example, and the transistor 10a
The base current is supplied by the emitter current of the transistor 10b, and therefore ultimately supplied by the power supply V ₀ . In addition, in one of such transistor combination circuits, for example, a circuit in which the transistor 10b is a pnp type, a certain part constitutes a pnpn junction,
Although it may exhibit parasitic thyristor characteristics and enter an oscillation state, this circuit suppresses this and supplies the base current of the first stage transistor 10b to the chip enable circuit. In operation, when the output of the inverter (NAND gate in this example) 30 is at L level, the current from the chip enable circuit flows into the inverter 30 and does not flow to the transistor 10b, and the transistor is off, but the inverter 30 When the output of the chip enable circuit becomes H level, current from the chip enable circuit flows into the base of transistor 10b, turning on transistor 10b, and its emitter current flows into the base of transistor 10a, turning it on. This circuit operates only in the linear region and does not oscillate. Of course, it is possible to connect the transistors in more stages, and the more stages the transistors are connected, the more likely the leakage problem in the base circuit described above will occur.

As explained in detail above, according to the present invention, the write test can be performed with both voltage and current in normal conditions, so the presence of leakage etc. can be reliably detected, and the pre-shipment test of field programmable elements can be performed more reliably. be able to.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of PROM, Figure 2 is a circuit diagram showing the circuit configuration of its test bit section, Figures 3 and 4 are explanatory diagrams of write voltage-current characteristics, and Figure 5 is bit line selection. FIG. 3 is a circuit diagram showing a specific example of the section. In the drawing, CELL is the memory cell part, TB, TW are test bits, B ₁ , B ₂ are bit lines, W ₁ , W ₂ ,...
. . are word lines, and 11, 12, . . . are memory cells.

Claims (1)

[Scope of Claims] 1. A memory cell has a test bit in a memory cell section that stores information by determining whether or not a bit line and a word line are short-circuited, and a higher voltage than when reading is applied to the memory cell. In a programmable read-only semiconductor memory device in which information is written by applying a voltage, at least one unwritten memory cell that is not short-circuited between the bit line and the word line among the memory cells forming the test bit is connected to another memory cell. A programmable read-only semiconductor memory device characterized in that it is larger than a cell and can be tested with a write voltage and write current applied.