JPS6322478B2 - - Google Patents
Info
- Publication number
- JPS6322478B2 JPS6322478B2 JP56066750A JP6675081A JPS6322478B2 JP S6322478 B2 JPS6322478 B2 JP S6322478B2 JP 56066750 A JP56066750 A JP 56066750A JP 6675081 A JP6675081 A JP 6675081A JP S6322478 B2 JPS6322478 B2 JP S6322478B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- groove
- light emitting
- current blocking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Description
【発明の詳細な説明】
本発明は、レーザ・ダイオード或いは発光ダイ
オードなど半導体発光装置を製造する方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in methods for manufacturing semiconductor light emitting devices such as laser diodes or light emitting diodes.
従来、活性層をクラツド層で取り囲んだ構造を
有するレーザ・ダイオード、例えばBHLD
(Buried Heterostructure Laser Diode),
BCLD(Buried Crescent Laser Diode)などが
知られている。 Conventionally, laser diodes have a structure in which the active layer is surrounded by a cladding layer, such as BHLD.
(Buried Heterostructure Laser Diode)
BCLD (Buried Crescent Laser Diode) is known.
第1図はBHLDの構造を表わす要部側断面説
明図である。 FIG. 1 is an explanatory side sectional view of the main part showing the structure of BHLD.
図に於いて、1はn―InP半導体基板、2はp
―InP電流阻止層、3はn―InPクラツド層、4
はInGaAsP活性層、5はp―InPクラツド層、6
はp―InGaAsPコンタクト層、7はn側電極、
8はp側電極をそれぞれ示す。 In the figure, 1 is an n-InP semiconductor substrate, 2 is a p-InP semiconductor substrate, and 2 is a p-InP semiconductor substrate.
-InP current blocking layer, 3 is n-InP cladding layer, 4
is InGaAsP active layer, 5 is p-InP clad layer, 6 is
is a p-InGaAsP contact layer, 7 is an n-side electrode,
8 indicates a p-side electrode.
ところで、このレーザ・ダイオードを製造する
には、n―InP半導体基板1に液相エピタキシヤ
ル成長法を適用してp―InP電流阻止層2を成長
させた段階で表面から基板1に達する溝を形成
し、その後、再び液相エピタキシヤル成長法を適
用してn―InPクラツド層3、InGaAsP活性層
4、p―InPクラツド層5、p―InGaAsPコンタ
クト層6を成長させるようにしているが、この技
法を採ると2回に亘り液相エピタキシヤル成長を
行なうので製造歩留りが極めて悪い欠点がある。 By the way, in order to manufacture this laser diode, a groove reaching from the surface to the substrate 1 is formed at the stage where the p-InP current blocking layer 2 is grown by applying the liquid phase epitaxial growth method to the n-InP semiconductor substrate 1. After that, the liquid phase epitaxial growth method is applied again to grow the n-InP cladding layer 3, the InGaAsP active layer 4, the p-InP cladding layer 5, and the p-InGaAsP contact layer 6. When this technique is adopted, liquid phase epitaxial growth is performed twice, which has the disadvantage that the manufacturing yield is extremely low.
本発明は、液相エピタキシヤル成長を1回で済
ませることができる半導体発光装置の製造方法を
提供するものであり、以下、これを詳細に説明す
る。 The present invention provides a method for manufacturing a semiconductor light emitting device that can be completed by liquid phase epitaxial growth in one step, and will be described in detail below.
第2図乃至第4図は本発明一実施例を説明する
為の工程要所に於ける装置の要部側断面説明図を
それぞれ示すものであり、次に、これ等の図を参
照しつつ記述する。 FIGS. 2 to 4 are side cross-sectional views of the main parts of the apparatus at key points in the process for explaining one embodiment of the present invention.Next, referring to these figures, Describe.
第2図参照
(1) n―InP基板11にフオト・リソグラフイ技
術及びエツチング技術にて幅例えば約2〔μm〕、
深さ例えば約1.5〔μm〕である溝11aを形成
する。Refer to Figure 2 (1) The width of the n-InP substrate 11, for example, approximately 2 [μm], is etched using photolithography and etching techniques.
A groove 11a having a depth of, for example, about 1.5 [μm] is formed.
第3図参照
(2) 液相エピタキシヤル成長法を適用し、p―
InP電流阻止層12を厚さ例えば溝外にて約0.1
〔μm〕に成長させる。このようにすると、溝内
では厚さが約0.5〔μm〕になる。 See Figure 3 (2) Applying the liquid phase epitaxial growth method, p-
The InP current blocking layer 12 has a thickness of, for example, approximately 0.1 outside the groove.
Grow to [μm]. In this way, the thickness within the groove will be approximately 0.5 [μm].
第4図参照
(3) 前記工程に引き続いてn―InPクラツド層1
3を厚さ例えば溝外にて約0.1〔μm〕に成長さ
せる。これに依り、溝内では厚さが約0.5〔μm〕
になる。 See Figure 4 (3) Following the above steps, the n-InP cladding layer 1 is
3 is grown to a thickness of, for example, about 0.1 [μm] outside the groove. Due to this, the thickness inside the groove is approximately 0.5 [μm]
become.
(4) In1-xGaXAs1-yPy活性層14を溝内に於いて
厚さ例えば約0.15〔μm〕に形成する。(4) An In 1-x Ga X As 1-y P y active layer 14 is formed in the groove to a thickness of about 0.15 [μm], for example.
(5) p―InPクラツド層15を厚さ例えば溝外に
て1〔μm〕程度に成長させる。(5) The p-InP cladding layer 15 is grown to a thickness of, for example, about 1 [μm] outside the groove.
これに依り溝11aは完全に埋められ、しか
も表面は平坦になる。 As a result, the groove 11a is completely filled and the surface becomes flat.
(6) p―In1-zGazAs1-sPsコンタクト層16を厚
さ例えば0.5〔μm〕程度に成長させる。これで
一連の連続エピタキシヤル成長を終了する。(6) The p-In 1-z Ga z As 1-s P s contact layer 16 is grown to a thickness of, for example, about 0.5 [μm]. This completes the series of continuous epitaxial growth.
(7) 通常の技術にてp側電極17及びn側電極1
8を形成して完成する。(7) P-side electrode 17 and n-side electrode 1 using normal techniques
Form 8 and complete.
このように、本発明では、1回の連続エピタキ
シヤル成長法にて全ての半導体層を成長させてし
まう。 In this way, in the present invention, all semiconductor layers are grown by one continuous epitaxial growth method.
ところで、前記実施例に依ると、溝内にもp―
InP電流阻止層12が形成され、その上に形成さ
れるn―InPクラツド層13との間に生成される
p.n接合には逆バイアスが印加されることになる
から電流は阻止されて横流れし、図に矢印で示す
方向に流れることになるが動作上は何等差し支え
ない。又、拡散電位の差からp―InP層15から
n―InP基板11への電流注入に比べ、p―InP
層15から活性層14への電流注入の方が容易に
行なわれるため、効率の良い活性層への電流注入
が可能である。 By the way, according to the above embodiment, p-
An InP current blocking layer 12 is formed and an n-InP cladding layer 13 is formed thereon.
Since a reverse bias will be applied to the pn junction, the current will be blocked and will flow horizontally in the direction shown by the arrow in the figure, but this will not affect the operation in any way. Also, due to the difference in diffusion potential, compared to current injection from the p-InP layer 15 to the n-InP substrate 11, the p-InP
Since current injection from layer 15 to active layer 14 is performed more easily, current can be efficiently injected into the active layer.
第5図は他の実施例を説明する為の半導体発光
装置の要部側断面説明図であり、第4図に於いて
用いた記号と同記号は同部分を示すか或いは同じ
意味を持つものとする。 FIG. 5 is a side cross-sectional view of a main part of a semiconductor light emitting device for explaining another embodiment, and the same symbols as those used in FIG. 4 indicate the same parts or have the same meanings. shall be.
この実施例では、p―InPクラツド兼電流阻止
層12′を形成することに依り、第4図に於ける
n―InPクラツド層13を省略したものである。
この場合、電流は活性層14の側面から矢印で示
すように流れる。 In this embodiment, the n-InP cladding layer 13 in FIG. 4 is omitted by forming a p-InP cladding/current blocking layer 12'.
In this case, current flows from the side surface of the active layer 14 as shown by the arrow.
第6図は他の実施例を説明する為の半導体発光
装置の要部側断面説明図であり、第4図に関して
説明した部分と同部分を同記号で指示してある。 FIG. 6 is a side cross-sectional view of a main part of a semiconductor light emitting device for explaining another embodiment, and the same parts as those explained with reference to FIG. 4 are indicated by the same symbols.
この実施例では、p―InP電流阻止層12の上
にn―InGaAsPガイド層13′を形成してもので
あり、このガイド層13′は活性層14とは組成
を変えてあ、バンド・ギヤツプを0.1〔eV〕程度
大に採る。 In this embodiment, an n-InGaAsP guide layer 13' is formed on the p-InP current blocking layer 12, and this guide layer 13' has a different composition from the active layer 14 and has a band gap. is taken to be about 0.1 [eV] large.
このようにすると、活性層14からガイド層1
3′への光のしみ出し方が大になる為、発光面積
は広くなり、高出力化,発光形状の円形化が可能
になる。 In this way, from the active layer 14 to the guide layer 1
Since the amount of light seeping out to 3' increases, the light emitting area becomes wider, making it possible to increase the output and make the light emitting shape circular.
第7図は他の実施例を説明する為の半導体発光
装置の要部側断面説明図であり、第4図に関して
説明した部分と同部分は同記号で指示してある。 FIG. 7 is a side cross-sectional view of a main part of a semiconductor light emitting device for explaining another embodiment, and the same parts as those explained with reference to FIG. 4 are indicated by the same symbols.
この実施例では、第5図に見られるp―InPク
ラツド兼電流阻止層12′の組成を第6図に関し
て説明したように変えてp―InGaAsPガイド兼
電流阻止層12″としたものである。 In this embodiment, the composition of the p-InP cladding and current blocking layer 12' shown in FIG. 5 is changed as explained with reference to FIG. 6 to form a p-InGaAsP guide and current blocking layer 12''.
前記各実施例に於いて、基板11はクラツド層
の役目も果していることは云うまでもなく、ま
た、各実施例に於いて導電型即ちn型及びp型を
それぞれ逆にしても良く、更にまた、電流阻止層
に不純物を導入することなく例えばInP,
InGaAsPなどの高抵抗層としても良い。 Needless to say, in each of the embodiments described above, the substrate 11 also serves as a cladding layer, and in each embodiment, the conductivity types, that is, n-type and p-type, may be reversed, and further, In addition, without introducing impurities into the current blocking layer, for example, InP,
A high resistance layer such as InGaAsP may also be used.
前記した何れの実施例に於いても、所要各半導
体層を形成するエピタキシヤル成長は一回の連続
成長で済むことは云うまでもない。 In any of the embodiments described above, it goes without saying that the epitaxial growth for forming each required semiconductor layer can be accomplished by one continuous growth.
以上の説明で判るように、本発明に依れば、基
板に最初から溝を形成し、その後、各半導体層を
連続エピタキシヤル成長させ、溝内の最下部に他
領域と分離した電流阻止層を、その上に該溝内に
埋め込まれる活性層を、該活性層に接してクラツ
ド層をそれぞれ形成した構造になつているので、
エピタキシヤル成長は1回で済むから製造歩留は
向上する。 As can be seen from the above explanation, according to the present invention, a groove is formed in the substrate from the beginning, and then each semiconductor layer is epitaxially grown continuously, and a current blocking layer is formed at the lowest part of the groove, separated from other regions. , an active layer buried in the groove, and a cladding layer in contact with the active layer.
Since epitaxial growth only needs to be performed once, manufacturing yield is improved.
第1図は従来例の要部側断面説明図、第2図乃
至第4図は本発明一実施例を説明する為の工程要
所に於ける半導体発光装置の要部側断面説明図、
第5図乃至第7図は本発明に於けるそれぞれ異な
る実施例を説明する為の半導体発光装置の要部側
断面説明図である。
図に於いて、11は基板、11aは溝、12は
電流阻止層、13はクラツド層、14は活性層、
15はクラツド層、16はコンタクト層である。
FIG. 1 is an explanatory side cross-sectional view of the main part of a conventional example, and FIGS. 2 to 4 are side cross-sectional views of the main part of a semiconductor light emitting device at important process points for explaining an embodiment of the present invention.
5 to 7 are sectional side views of essential parts of a semiconductor light emitting device for explaining different embodiments of the present invention. In the figure, 11 is a substrate, 11a is a groove, 12 is a current blocking layer, 13 is a cladding layer, 14 is an active layer,
15 is a cladding layer, and 16 is a contact layer.
Claims (1)
基板の表面上及び該溝の底面上に電流阻止層と活
性層とクラツド層とをその順に一回の成長で連続
して形成する工程が含まれてなることを特徴とす
る半導体発光装置の製造方法。1. Forming a groove in a semiconductor substrate, and then successively forming a current blocking layer, an active layer, and a cladding layer in that order on the surface of the semiconductor substrate and the bottom of the groove in one growth step. A method of manufacturing a semiconductor light emitting device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6675081A JPS57181186A (en) | 1981-05-01 | 1981-05-01 | Semiconductor light emission device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6675081A JPS57181186A (en) | 1981-05-01 | 1981-05-01 | Semiconductor light emission device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57181186A JPS57181186A (en) | 1982-11-08 |
| JPS6322478B2 true JPS6322478B2 (en) | 1988-05-12 |
Family
ID=13324862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6675081A Granted JPS57181186A (en) | 1981-05-01 | 1981-05-01 | Semiconductor light emission device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57181186A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0471880U (en) * | 1990-10-30 | 1992-06-25 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5493380A (en) * | 1977-12-30 | 1979-07-24 | Fujitsu Ltd | Semiconductor light emitting device |
| JPS55121693A (en) * | 1979-03-15 | 1980-09-18 | Tokyo Inst Of Technol | Manufacture of band-like semiconductor laser by selective melt-back process |
-
1981
- 1981-05-01 JP JP6675081A patent/JPS57181186A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0471880U (en) * | 1990-10-30 | 1992-06-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57181186A (en) | 1982-11-08 |
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