JPS6322490B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a pulse width modulation circuit, and more particularly to a modulation circuit that generates pulses whose width gradually increases in proportion to the number of reference pulses. In general, when measuring the minimum input signal pulse width (minimum write pulse width) required for the operation of a memory circuit, etc., the control pulse width that is input to the memory circuit is gradually widened from a narrow width. The pulse width when is turned on or off is the minimum write pulse width. For automatic measurement of this, a pulse width modulation circuit is required to automatically change the width of the control pulse from a narrow pulse width to a wide pulse width. Figure 1 is an example of a pulse width modulation circuit used in a minimum write pulse width measurement circuit of a memory circuit, etc.
This is a pulse width modulation circuit whose output pulse width changes in proportion to the number of input pulses. The pulse width modulation circuit shown in the figure is composed of a ramp voltage generation circuit 1, a pulse number-to-analog conversion circuit 10, and a comparator 20. The lamp voltage generation circuit 1 causes a constant current to flow through a capacitor 2 from a constant current source circuit 3, and generates a lamp voltage _e1 based on the charging voltage of the capacitor 2. Transistor 4 and resistor 5 are connected to the lamp voltage e ₁
This is a switch circuit for synchronizing the generation of CP to the input pulse _CP . That is, as shown in the operating waveform (e ₁ ) in FIG. 2, first, the input pulse signal CP _G
This turns on the transistor 4 through the resistor 5 and discharges the charge in the capacitor 2. Since the capacitor 2 is charged by the constant current source circuit 3 until the next pulse CP _G comes, a lamp voltage e ₁ synchronized with the input pulse is generated. The pulse number-to-analog conversion circuit 10 counts the number of pulses using counters 11 and 12 (FIG. 1 shows an example of an 8-bit configuration using 4-bit counters 11 and 12), and outputs the contents to the D/A.
It is converted into an analog voltage _e2 through a conversion circuit 13. Note that 14 is a pulse number display circuit that displays the output contents of the counters 11 and 12. 20 is a comparator circuit that connects the output e ₁ of the lamp voltage generation circuit 1 and the pulse number-to-analog conversion circuit 10
This is to compare the output e ₂ of . Now, if the maximum output voltage value of the pulse number-to-analog conversion circuit 10 (the value of the output voltage e2 when 256 input pulses are counted since it has an 8-bit configuration in FIG. ₁ ) is E, then the As shown in Fig. 2, when one pulse is input, a voltage of 1/256·E is generated, and the value of the output e ₂ increases stepwise with each additional pulse. Therefore, if the peak voltage value of the lamp voltage e ₁ synchronized with the input pulse CP _G is E, and the interval between the input pulses CP _G is T, then the output CP _M of the comparator 20 that compares the voltages e ₁ and e ₂ is obtains a pulse whose pulse width increases by 1/256·T every time the pulse increases by one pulse. That is, for example, if n input pulses _CPG are counted by the counters 11 and 12 as shown in FIG. 3, a voltage of n/256E is generated at the output _e2 of the D/A conversion circuit 13. On the other hand, the width of the pulse _CPM output from the comparator 20 is n/256·T since the relationship between e ₁ and e ₂ is the time when e ₁ ≦e ₂ . Similarly, the n+1st input pulse
By counting CP _G , a pulse CP _M with a pulse width of n+1/256·T can be obtained. In this way, it is possible to obtain an output with a pulse width proportional to the number of input pulses. However, the pulse width modulation circuit shown in FIG.
Lamp voltage generation circuit 1 and D/A conversion circuit 1
3. Since an analog signal system is included in the comparator 20, etc., there is a problem that highly accurate pulse width modulation cannot be obtained. For example, there is a drawback that the accuracy of the output pulse CPM deteriorates due to the influence of the linearity of the lamp voltage, the setting accuracy of the final voltage E of the lamp voltage, the setting accuracy of the maximum voltage value E of _{the D} /A conversion circuit 13, etc. In view of these problems, an object of the present invention is to digitize the entire circuit system and provide a highly accurate pulse width modulation circuit. A feature of the present invention is that a reference pulse is frequency-divided according to the number of input pulses, and a single pulse corresponding to one cycle of the frequency-divided reference pulse is generated to modulate the pulse width. FIG. 4 shows a block diagram of a pulse width modulation circuit according to an embodiment of the present invention. In the figure, 30 is an input pulse counter circuit, 40 is a reference pulse generation circuit, 50 is a preset counter, 60 is a single pulse extraction circuit, and 70 is a pulse number display circuit. The operation of the pulse width modulation circuit shown in FIG.
This will be explained using the operational waveform diagram shown in the figure. The counter 30 is a counter that counts the number of input pulses _CPG , and the contents of the counter increase sequentially from 1, 2...n, n+1 as shown in FIG. On the other hand, the preset counter 50 receives the reference pulse
CP _S is counted, and the frequency division ratio is preset according to the contents of the counter 30, that is, the number of input pulses. Therefore, the first (corresponding to the left end of Figure 5)
The preset counter 50, in which the input pulses _CPG are counted by the counter 30, is divided into 1/1. In this case, the output pulse of the preset counter 50
For CP ₁ , the reference pulse CP _S is output as is. Next, when the second input pulse _CPG is counted, the preset frequency division ratio of the preset counter 50 is set to 1/2, and the output pulse _CP1 becomes a pulse whose interval is twice that of _CPS . Furthermore, if the counter 30 counts up to n input pulses CP _G , then the preset counter 50
The frequency division ratio is set to 1/n, and the output pulse _CP1 of the preset counter 50 is output at an interval n times the reference pulse _CPS . Note that the content is displayed by the pulse number display circuit 70. Therefore, the pulse period of the reference pulse CP _S is τ
Then, each time the input pulse CP _G is counted (the contents of the counter 30 are 1, 2,...n, n+1...
Since the frequency division ratio of the preset counter 50 is set to 1/1, 1/2, . . . 1/n, 1/n+1, etc., the output pulse _CPM of the preset counter 50 The period is τ, 2τ,...nτ, (n+1)τ...
...and increases. The single pulse extraction circuit 60 is a circuit that counts the input pulses CP _G and then generates a single pulse having a pulse width equivalent to one period of the pulse CP ₁ .
A specific example thereof is shown in FIG. 6, and the operation will be explained with reference to FIG. This single pulse extraction circuit 60 has two (J-K) flip-flops 61 and 62.
and an inverter 63. In addition,
64 is the input terminal of the divided reference pulse CP ₁ ;
5 is an input terminal for the input pulse CP _G , and 66 is an output terminal. As shown in Table 1, in the J-K flip-flops 61 and 62, when the reset terminal R (R ₁ , R ₂ in FIG. 6) goes to the "L" level, the positive output Q goes to the "L" level and the negative output goes to the "H" level. "Reset to level.
Also, when the J terminal is at the "L" level and the K terminal is at the "H" level, the clock terminals C (C ₁ and C ₂ in Figure 6)
When a pulse is input to , the positive output Q goes to “L” level and the negative output goes to “H” level when the input pulse falls.
fixed at the level.

[Table] Therefore, in the circuit of FIG. 6, when the input pulse CP _G (positive pulse) is input at time t ₁ as shown in FIG _. , _R2 are input with negative pulses, the reset terminals _R1 and _R2 become "L" level, and the output _Q1 becomes "L" level (in Fig. 7, it becomes "L" level before time _t1 ). 2), the negative output ₂ is reset to the "H" level. After that, the reset terminals R ₁ and R ₂ become "H" level, and when the i-th reference pulse CP ₁ is input to the reference pulse input terminal 64 at time t ₂ and falls, only the positive output Q ₁ of the flip-flop 61 becomes "L". ” level reverses to “H” level and rises. At this time, the positive output _Q1 is input to the clock terminal _C2 of the flip-flop 62, but the negative output ₂ of the flip-flop ₆₂ is inverted only when the input to the clock terminal C2 falls, so the input to the clock terminal _C2 rises. At time _t2 , negative output ₂ is “H” without being inverted.
held at the level. Next, at time _t3 , when the i+1th reference pulse _CP1 falls after being input to the clock terminal _C1 , the positive output _Q1 of the flip-flop ₆₁ is inverted from the "H" level to the "L" level. positive output
With the fall of the signal at the clock terminal _C2 to which _Q1 is input, the negative output ₂ of the flip-flop 62 is inverted from the "H" level to the "L" level. Here, the _J1 terminal connected to negative output ₂ is also “L”
Therefore, even if the i+2th reference pulse _CP1 is inputted at time _t4 , the _J1 terminal remains at the "L" level, so the flip-flop 61
The positive output _Q1 is held at “L” level, and
Since _C2 is also held at the "L" level, _C2 continues to be held at the "L" level and the operation is stopped.
In this operation stop state, reset terminals R ₁ and R ₂ are “L”.
It is held until time t ₅ when it reaches the level. Here, the positive output of flip-flop 61
The pulse waveform obtained from Q ₁ is a single pulse having a width equivalent to one cycle of the reference pulse CP ₁ after the input pulse CP _G is input. That is, the reference pulse
A single pulse CP _M with one period of CP ₁ can be generated. Similarly, the input pulse is
By inputting CP _G as 1, 2,..., (n+1)..., the pulse width of CP _M becomes τ, 2τ,...
nτ, (n+1)τ, etc., and a pulse _CPM whose width increases in proportion to the number of input pulses is obtained. According to this embodiment, unlike the circuit shown in FIG. 1, there is no analog signal system, so that _CPM with high accuracy in pulse width can be generated at an integral multiple of the reference pulse period τ. Furthermore, the degree of modulation of the width of _CPM with respect to the number of input pulses can be changed by changing the frequency (1/τ) of the reference pulse _CP1 , and this can be done digitally. Therefore, it is very effective as a control pulse for automatic measurement of the minimum write pulse width of the aforementioned memory circuit, etc. As described above, according to the present invention, a highly accurate pulse width modulation circuit can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional pulse width modulation circuit for the present inventors, FIGS. 2 and 3 are diagrams explaining the operation of the circuit in FIG. 1, and FIG. A block diagram of a pulse width modulation circuit according to an embodiment, FIG. 5 is a diagram explaining the operation of the circuit of FIG. 4, and FIG. 6 is an example of a single pulse extraction circuit used in the circuit of FIG. 4. The figure shown in FIG. 7 is a diagram explaining the operation of FIG. 6. 30...Counter, 40...Reference pulse generation circuit, 50...Preset counter, 60...Single pulse extraction circuit, 70...Pulse number display circuit.

Claims (1)

[Claims] 1 In a circuit in which the output pulse width is modulated according to the number of input pulses generated by the input pulse generation circuit, there is a counter connected to the input pulse generation circuit that counts the number of input pulses, and a counter connected to the counter that counts the number of input pulses. a preset counter whose frequency division ratio is set by a reference pulse generator connected to the input of the preset counter and which determines the minimum value of the output pulse width; 1. A pulse width modulation circuit comprising: an extraction circuit that extracts output pulses each having a pulse width of one period from a group of reference pulses whose frequency is sequentially divided by a counter at different frequency division ratios.