JPS6322644B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a radio receiver that can perform channel selection by directly inputting reception frequency data, and in particular, when the input data deviates from the normal value, This invention relates to a radio receiver configured to automatically correct the value.

In recent radio receivers, the local oscillator circuit is configured with a phase-locked loop (PLL), and by changing the division ratio of the programmable frequency divider that makes up the PLL, tuning can be performed in frequency steps between stations. A so-called synthesizer method is used to perform this. In the past, it was common to automatically sweep the receiving stations by automatically increasing or decreasing the frequency division ratio of the programmable frequency divider by 1. There is a need for a method that allows direct input.

In this method, the receiving station is set at a predetermined frequency interval (for example, 9KHz in the medium wave band, and 9KHz in the FM band).
100KHz) frequency, so if the received frequency data entered using the numeric keypad is input at a frequency that deviates from the regular frequency, there is a risk that the PLL will not be synchronized and the desired station will not be received. .

Therefore, the present invention has been made in view of this point.
To provide a radio receiver configured to automatically correct to the closest normal value when input reception frequency data deviates from a normal value.

Embodiments of the present invention will be described below with reference to the drawings. 1
A control circuit controls each circuit according to a program in a program memory 2 in which processing steps are programmed, and a key input means 3 is a numeric keypad for inputting received frequency data. Reference numeral 4 denotes an arithmetic circuit that performs arithmetic processing based on data input from the key input means 3, which is connected to the control circuit 1 and includes registers 5, 6, and 7 that store and hold data.
is connected to. The register 5 is configured to store reception frequency data inputted from the key input means 3, and the registers 6 and 7 are configured to store calculation results. A display section 8 digitally displays the reception frequency based on the reception frequency data supplied from the control circuit 1. A PLL section 9 is also connected to the control circuit 1 and is configured to generate a predetermined local oscillation frequency (f ₀ ) based on reception frequency data supplied from the control circuit 1.
Although there is a difference between the reception frequency and the local oscillation frequency by an amount equivalent to an intermediate frequency, the configuration is such that the PLL section 9 corrects it and obtains a predetermined local oscillation frequency (f ₀ ). Reference numeral 10 denotes an error indicator lamp that indicates an error when the input reception frequency data is outside the range of the reception band.

Next, a second explanation will be given of the operation of the present invention having such a configuration.
This will be explained with reference to the flowchart shown in the figure. First, a case where a receiving station receives medium wave bands arranged at 9KHz intervals will be explained. When receiving frequency data is input using the numeric keypad of the key input means 3,
The control circuit 1 determines whether the input data is within the medium wave band reception frequency range of 531 to 1611 KHz, and if it is outside the range, the error indicator lamp 1 is activated.
0 is lit to instruct the operator that there is an error in the input data. If the input data is within the range, after taking the input data into register 5,
Subsequently, the arithmetic circuit 4 performs the calculation of input data divided by 9, and stores the quotient in the register 6 and the remainder register 7. Next, it is determined whether the remainder is 5 or less, and 5
In the following cases, the arithmetic circuit 4 calculates the quotient x 9 based on the quotient stored in the register 6, and the result of the calculation is supplied to the display section 8 and the PLL section 9 to enter the receiving state. On the other hand, if the remainder is 5 or more, the arithmetic circuit 4
Then, the calculation of (quotient+1)×9 is performed and the calculation result is supplied to the display section 8 and the PLL section 9.

Therefore, for example, by the key input means 3
If 1307KHz data is input,
1307KHz is within the range, so the input data is “1307”
is stored in register 5, and then in arithmetic circuit 4.
The calculation 1307÷9 is performed. This results in a quotient of 145,
A remainder of 2 is obtained and stored in registers 6 and 7, respectively. Next, since the remainder 2 is less than or equal to 5,
Next, the arithmetic circuit 4 reads out the quotient data 145 stored in the register 6 and performs an operation of 145×9.
The calculation result "1305" is supplied from the control circuit 1 to the display section 8 and the PLL section 9. In this way, the frequency is corrected to the normal frequency and 1305KHz is displayed on the display section 8, and the receiving frequency of 1305KHz is displayed on the PLL section 9.
A local oscillation frequency (f ₀ ) corresponding to is generated,
1305KHz reception is performed.

Next, when receiving frequency data of 1312KHz is input from the key input means 3, when the calculation of 1312÷9 is performed in the same manner as above, a quotient of 145 and a remainder of 7 are obtained, so that the remainder is 5 or more. Therefore, this time, (quotient + 1) x 9, or (145 + 1)
×9 calculation is performed, and the calculation result “1314” is supplied from the control circuit 1 to the display unit 8 and PLL unit 9, so that the input data “1312” is corrected to the regular “1314”, 1314KHz reception is performed. If the input data deviates from the regular frequency data, it is corrected to the closest regular frequency data. Although the above explanation was for the medium wave band, the same modification can be made for the FM band etc. by simply changing the calculation formula.As described above, the radio receiver of the present invention When selecting a station by directly inputting frequency data, if incorrect frequency data is input, it will be automatically corrected to the closest correct frequency data, allowing the operator to avoid receiving frequencies that he or she has vaguely remembered. Even when the input signal is input, the reception operation can be performed accurately without malfunctioning, and this has an extremely large practical effect.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the main parts of the radio receiver of the present invention, and FIG. 2 is a flowchart showing the operating state of FIG. 1. 1...Control circuit, 2...Program memory,
3...Key input means, 4...Arithmetic circuit, 5, 6,
7...Register, 8...Display section, 9...PLL
Section 10...Error display lamp.

Claims (1)

[Claims] 1. In a radio receiver configured to select a station by directly inputting reception frequency data using input means, it is determined whether the input data is an integer multiple of the inter-station frequency, and the integer 1. A radio receiver comprising means for correcting the input data to receive frequency data that is an integer multiple, if the received frequency data is not a multiple. 2. The correction means includes means for determining which of two adjacent received frequency data that is an integral multiple of the inter-office frequency, the input data is closer to,
2. The radio receiver according to claim 1, wherein the input data is modified to receive frequency data closest to the input data.