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JPS632364B2 - - Google Patents
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JPS632364B2 - - Google Patents

Info

Publication number
JPS632364B2
JPS632364B2 JP56058766A JP5876681A JPS632364B2 JP S632364 B2 JPS632364 B2 JP S632364B2 JP 56058766 A JP56058766 A JP 56058766A JP 5876681 A JP5876681 A JP 5876681A JP S632364 B2 JPS632364 B2 JP S632364B2
Authority
JP
Japan
Prior art keywords
circuit
control voltage
input
generating means
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56058766A
Other languages
Japanese (ja)
Other versions
JPS57173210A (en
Inventor
Shintaro Gomi
Katsuaki Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP5876681A priority Critical patent/JPS57173210A/en
Publication of JPS57173210A publication Critical patent/JPS57173210A/en
Publication of JPS632364B2 publication Critical patent/JPS632364B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3052Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【発明の詳細な説明】 技術分野 本発明は受信機のアンテナ受信入力回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an antenna reception input circuit for a receiver.

背景技術 受信機のチユーナ回路においては、AGC(自動
利得制御)回路が不可欠となつているが、かかる
AGC回路を有するチユーナの回路図を第1図に
示す。アンテナ素子1からのRF(高周波)受信信
号はコンデンサC1を介して可変インピーダンス
素子であるダイオードD1,D2より成るレベル制
御回路2へ導入される。このレベル制御回路2の
各インピーダンス素子D1,D2は、AGC電圧VA
よりそのインピーダンスが制御されてアンテナ受
信信号レベルを制御する。尚、コンデンサC2
バイパスコンデンサである。
BACKGROUND ART An AGC (automatic gain control) circuit is indispensable in the tuner circuit of a receiver.
Figure 1 shows a circuit diagram of a tuner with an AGC circuit. An RF (high frequency) received signal from the antenna element 1 is introduced via a capacitor C 1 to a level control circuit 2 consisting of diodes D 1 and D 2 which are variable impedance elements. The impedance of each impedance element D 1 and D 2 of this level control circuit 2 is controlled by the AGC voltage V A to control the antenna reception signal level. Note that capacitor C2 is a bypass capacitor.

このレベル制御回路2の出力はコンデンサC3
を介して、商用電源周波数を基準電位点に落とす
ハムノイズ遮断用のコイルL1及び能動素子であ
るFET(電界効果トランジスタ)Q1を有するRF
バツフアアンプ3へ入力される。このRFバツフ
アアンプ3自身はアンテナ素子1からの受信信号
を非同調で受けるものであり、このアンプ3の負
荷には、同調トランスT、可変容量素子VD、ト
リマコンデンサC4及び抵抗R1より成る並列同調
回路4が接続されて、所望の受信バンド内の周波
数を選択的に導出するようになされている。可変
容量素子VDは、チユーニング電圧VTが抵抗R2
介して印加されることによりその容量値が制御さ
れる。尚、コンデンサC5はバイパス用である。
The output of this level control circuit 2 is the capacitor C 3
RF that has a hum noise blocking coil L1 that lowers the commercial power frequency to the reference potential point and an active element FET (field effect transistor) Q1 .
It is input to the buffer amplifier 3. This RF buffer amplifier 3 itself receives the received signal from the antenna element 1 in a non-tuned manner, and the load of this amplifier 3 includes a parallel circuit consisting of a tuning transformer T, a variable capacitance element VD, a trimmer capacitor C4 , and a resistor R1. A tuning circuit 4 is connected to selectively derive frequencies within the desired reception band. The capacitance value of the variable capacitance element VD is controlled by applying a tuning voltage V T via a resistor R 2 . Note that capacitor C5 is for bypass.

選択的に導出されたRF同調出力は、RFアンプ
5により増幅されて、周波数変換器6において
IF(中間周波数)信号となり、IFアンプ及び検波
器7へ導かれる。この検波器7の出力がチユーナ
出力となる。そして、IF信号又は検波信号レベ
ルに応じた電圧V′Aが回路7内に於いて発生さ
れ、これがIFアンプと更にはRFアンプ5のAGC
電圧として用いられる。また、電圧V′AはAGCバ
ツフア回路8によりインピーダンス変換されて、
先のレベル制御回路2の制御電圧VAとして出力
される。
The selectively derived RF tuning output is amplified by the RF amplifier 5 and then sent to the frequency converter 6.
It becomes an IF (intermediate frequency) signal and is guided to the IF amplifier and detector 7. The output of this detector 7 becomes the tuner output. Then, a voltage V′ A corresponding to the IF signal or detection signal level is generated in the circuit 7, and this is applied to the AGC of the IF amplifier and further the RF amplifier 5.
Used as voltage. In addition, the voltage V′ A is impedance-converted by the AGC buffer circuit 8,
It is output as the control voltage V A of the level control circuit 2 mentioned above.

かかる構成においては、RF段及びIF段に設け
られたフイルタを経た信号レベルを検出して
AGC電圧VA、V′Aを発生するものであるから、
AGC電圧と周波数との関係は、第2図に示すよ
うな極めて狭帯域特性を呈することになる。その
ために、受信希望波に対してはAGC作用は有効
であるが、希望波以外の妨害波に対しては何等動
作しない。従つて、強電界において中電界の希望
波を受信する如き場合又は相対的に電界が強くな
る夜間等においてはIM(相互変調)妨害波等によ
る混信現象が顕著となる欠点がある。これは、
RF入力段のAGCにおいてはS/N悪化を防止す
るために遅延をかけており、中電界では希望波で
このRF入力段のAGCがかからないことによつて
も生じるものである。
In such a configuration, the signal level that has passed through the filters provided in the RF stage and the IF stage is detected.
Since it generates AGC voltages V A and V′ A ,
The relationship between AGC voltage and frequency exhibits an extremely narrow band characteristic as shown in FIG. Therefore, although the AGC effect is effective against received desired waves, it does not work at all against interference waves other than the desired waves. Therefore, when receiving a desired wave of a medium electric field in a strong electric field, or at night when the electric field is relatively strong, there is a drawback that interference phenomena due to IM (intermodulation) interference waves etc. become noticeable. this is,
A delay is applied to the AGC of the RF input stage to prevent S/N deterioration, and this is also caused by the fact that the AGC of the RF input stage is not applied due to the desired wave in a medium electric field.

更には、AGCループが2重になつている関係
上、回路全体が不安定となることが避けられない
という欠点もある。
Furthermore, since the AGC loop is duplicated, there is also the disadvantage that the entire circuit inevitably becomes unstable.

発明の概要 従つて、本発明の目的はIM妨害波等による混
信を排除し得るアンテナ受信入力回路を提供する
ことである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an antenna reception input circuit that can eliminate interference caused by IM interference waves and the like.

本発明によるアンテナ受信入力回路は、アンテ
ナ素子からのRF信号を非同調で受ける能動素子
と、該能動素子の出力負荷として設けられた負荷
回路と、該負荷回路によつて得られる出力信号を
入力としてこの出力信号のレベルに応じた制御電
圧を発生する制御電圧発生手段と、該制御電圧発
生手段からの制御電圧を受けてアンテナ素子と能
動素子との接続点におけるRF信号のレベルを前
記制御電圧に応じて減衰させるように制御する
RF入力制御手段とを具備し、負荷回路は抵抗と
周波数選択回路との直列接続回路により構成さ
れ、前記直列接続回路における前記抵抗の前記能
動素子側端部より導出された出力信号を前記制御
電圧発生手段に印加せしめ、広帯域のAGC機能
を有するようにしたことを特徴としている。
An antenna receiving input circuit according to the present invention includes an active element that receives an RF signal from an antenna element in an asynchronous manner, a load circuit provided as an output load of the active element, and an output signal obtained by the load circuit. a control voltage generating means that generates a control voltage according to the level of this output signal; and a control voltage generating means that receives the control voltage from the control voltage generating means and sets the level of the RF signal at the connection point between the antenna element and the active element to the control voltage. control to attenuate according to
RF input control means, the load circuit is constituted by a series connection circuit of a resistor and a frequency selection circuit, and the output signal derived from the active element side end of the resistor in the series connection circuit is applied to the control voltage. It is characterized in that it is applied to the generating means and has a broadband AGC function.

実施例 以下に本発明を図面を用いて説明する。Example The present invention will be explained below using the drawings.

第3図は本発明の一実施例の回路図であり、第
1図と同等部分は同一符号により示されている。
第1図と異なる部分についてのみ示せば、RFバ
ツフアアンプ3のFETQ1のドレイン負荷すなわ
ちバツフアアンプ3の出力負荷である並列同調回
路4の同調トランスTの1次コイルと直列に抵抗
R3を挿入し、この直列接続回路における抵抗R3
のFETQ1側の端部より導出された信号を制御電
圧発生手段、すなわち広帯域AGC処理回路9に
入力し、AGC電圧VAを発生するようにする。こ
の電圧VAにより可変インピーダンス素子D1,D2
のインピーダンスが制御されて、アンテナ入力信
号レベルが制御される。
FIG. 3 is a circuit diagram of one embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same symbols.
To show only the parts that are different from Fig. 1, there is a resistor connected in series with the primary coil of the tuning transformer T of the parallel tuning circuit 4, which is the drain load of FETQ 1 of the RF buffer amplifier 3, that is, the output load of the buffer amplifier 3.
Insert R 3 and resistor R 3 in this series connected circuit
The signal derived from the end of the FETQ 1 side is inputted to the control voltage generating means, that is, the wideband AGC processing circuit 9, and the AGC voltage V A is generated. This voltage V A causes variable impedance elements D 1 , D 2
The impedance of the antenna is controlled to control the antenna input signal level.

この広帯域AGC処理回路9としては、例えば
RF増幅、検波及び平滑化する回路構成とすれば
良い。他の回路構成ついては第1図のそれと同等
であるから説明は省略する。
As this wideband AGC processing circuit 9, for example,
A circuit configuration for RF amplification, detection, and smoothing may be used. Since the other circuit configurations are the same as those shown in FIG. 1, their explanations will be omitted.

かかる構成において、FETQ1のドレインと同
調トランスTとの間に抵抗R3が挿入されている
ために、ドレインからみた周波数対VAとの関係
を示す選択特性は第4図に示すようになる。すな
わち、抵抗R3が零の場合の選択特性(第2図の
それと同一である)に対して、抵抗R3の値を増
大することにより選択周波数0を中心とした上下
両外側の周波数波に対しては略平坦な特性が次第
に上昇するようになる。よつて、任意の周波数特
性を有する広帯域のAGC作用を行わせることが
可能となり、IM妨害波等による混信が著しく減
少する。
In this configuration, since the resistor R 3 is inserted between the drain of FETQ 1 and the tuning transformer T, the selection characteristic showing the relationship between the frequency and V A seen from the drain becomes as shown in Figure 4. . In other words, for the selection characteristic when the resistance R 3 is zero (same as that in Figure 2), by increasing the value of the resistance R 3 , the frequency waves on both the upper and lower sides of the selection frequency 0 are changed. On the other hand, the approximately flat characteristic gradually increases. Therefore, it becomes possible to perform a wideband AGC operation having arbitrary frequency characteristics, and interference due to IM interference waves and the like is significantly reduced.

ここで、FETQ1の出力インピーダンスは同調
トランスTの1次巻線に比し極めて高いので、受
信信号に対する選択特性は抵抗R3の影響を受け
ることなく尖鋭な特性を維持し得ると共に、損失
も殆んど生じない。更には、AGC電圧VAにより
RF入力信号レベルを制御しており、FETQ1の動
作点を変化させる如きAGC方式ではないので、
能動素子の動作点変動に起因する歪の発生更には
この歪によるIM妨害及び混変調妨害が防止され
ることになる。また、AGCループが2重ループ
を構成することがないので回路全体が安定とな
る。
Here, since the output impedance of FETQ 1 is extremely high compared to the primary winding of the tuning transformer T, the selection characteristics for the received signal can maintain sharp characteristics without being affected by the resistor R 3 , and the loss can also be reduced. Almost never occurs. Furthermore, depending on the AGC voltage V A
Since it controls the RF input signal level and is not an AGC method that changes the operating point of FETQ 1 ,
This will prevent the generation of distortion due to operating point fluctuations of active elements, as well as IM interference and cross-modulation interference due to this distortion. Furthermore, since the AGC loop does not form a double loop, the entire circuit becomes stable.

発明の効果 本発明は以上のように能動素子の出力負荷とし
て設けられた負荷回路を、抵抗と周波数選択回路
との直列接続回路により構成し、この直列接続回
路における前記抵抗の能動素子側端部よりAGC
に利用する信号を導出するようにしたので、広帯
域AGC機能を安定に動作させることができ、よ
つて強電界における混信をなくすことが可能とな
ると共に広帯域AGC特性を感度抑圧をみながら
自由に設定できる利点がある。この発明は特に、
MW(中波)又はLW(長波)の周波数バンドの車
載用チユーナに用いて好適となるが、特に限定さ
れるものではない。また、上記の回路例も種々の
変形が可能であることは勿論である。
Effects of the Invention As described above, the load circuit provided as an output load of an active element is configured by a series connection circuit of a resistor and a frequency selection circuit, and the active element side end of the resistor in this series connection circuit More AGC
Since the signal used for this purpose is derived, the wideband AGC function can operate stably, thereby eliminating interference in strong electric fields, and the wideband AGC characteristics can be freely set while considering sensitivity suppression. There are advantages that can be achieved. In particular, this invention
Although it is suitable for use in an on-vehicle tuner for the MW (medium wave) or LW (long wave) frequency band, it is not particularly limited. Furthermore, it goes without saying that the circuit example described above can be modified in various ways.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のチユーナの回路図、第2図は第
1図のAGC特性を示す図、第3図は本発明の一
実施例の回路を用いたチユーナの回路図、第4図
は第3図のAGC特性を示す図である。 主要部分の符号の説明、1……アンテナ、2…
…入力レベル制御回路、3……RF入力回路、4
……同調回路、9……広帯域AGC処理回路。
Figure 1 is a circuit diagram of a conventional tuner, Figure 2 is a diagram showing the AGC characteristics of Figure 1, Figure 3 is a circuit diagram of a tuner using a circuit according to an embodiment of the present invention, and Figure 4 is a diagram showing the AGC characteristics of Figure 1. 3 is a diagram showing the AGC characteristics of FIG. 3. FIG. Explanation of symbols of main parts, 1...Antenna, 2...
...Input level control circuit, 3...RF input circuit, 4
... Tuning circuit, 9... Wideband AGC processing circuit.

Claims (1)

【特許請求の範囲】 1 アンテナ素子からのRF信号を非同調で受け
る能動素子と、前記能動素子の出力負荷として設
けられた負荷回路と、前記負荷回路によつて得ら
れる出力信号を入力としてこの出力信号のレベル
に応じた制御電圧を発生する制御電圧発生手段
と、前記制御電圧発生手段からの制御電圧を受け
て前記アンテナ素子と能動素子との接続点におけ
る前記RF信号のレベルを前記制御電圧に応じて
減衰させるように制御するRF入力制御手段とを
具備したアンテナ受信入力回路であつて、前記負
荷回路は抵抗と周波数選択回路との直列接続回路
により構成され、前記直列接続回路における前記
抵抗の前記能動素子側端部より導出された出力信
号を前記制御電圧発生手段に印加せしめ、前記周
波数選択回路によつて定められる選択周波数0
中心とする広帯域特性にて前記制御電圧を前記
RF入力制御手段に供給したことを特徴とするア
ンテナ受信入力回路。 2 前記RF入力制御手段は前記アンテナ素子と
前記能動素子との接続点にその一端が接続され、
その他端が基準電位点に接続された電圧依存性可
変インピーダンス素子より成ることを特徴とする
特許請求の範囲第1項記載のアンテナ受信入力回
路。
[Claims] 1. An active element that receives an RF signal from an antenna element in an asynchronous manner, a load circuit provided as an output load of the active element, and an output signal obtained by the load circuit as an input. control voltage generating means for generating a control voltage according to the level of the output signal; and receiving the control voltage from the control voltage generating means, adjusting the level of the RF signal at the connection point between the antenna element and the active element to the control voltage. RF input control means for controlling the attenuation according to the frequency selection circuit, wherein the load circuit is constituted by a series connection circuit of a resistor and a frequency selection circuit, and An output signal derived from the active element side end of the control voltage generating means is applied to the control voltage generating means, and the control voltage is applied to the control voltage generating means with a wide band characteristic centered on a selection frequency 0 determined by the frequency selection circuit.
An antenna reception input circuit characterized in that the antenna reception input circuit is supplied to an RF input control means. 2. The RF input control means has one end connected to a connection point between the antenna element and the active element,
2. The antenna reception input circuit according to claim 1, further comprising a voltage-dependent variable impedance element whose other end is connected to a reference potential point.
JP5876681A 1981-04-18 1981-04-18 Antenna receiving and inputting circuit Granted JPS57173210A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5876681A JPS57173210A (en) 1981-04-18 1981-04-18 Antenna receiving and inputting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5876681A JPS57173210A (en) 1981-04-18 1981-04-18 Antenna receiving and inputting circuit

Publications (2)

Publication Number Publication Date
JPS57173210A JPS57173210A (en) 1982-10-25
JPS632364B2 true JPS632364B2 (en) 1988-01-19

Family

ID=13093661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5876681A Granted JPS57173210A (en) 1981-04-18 1981-04-18 Antenna receiving and inputting circuit

Country Status (1)

Country Link
JP (1) JPS57173210A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS609323U (en) * 1983-06-28 1985-01-22 パイオニア株式会社 car radio receiver
JPS6019246U (en) * 1983-07-15 1985-02-09 クラリオン株式会社 High frequency signal attenuation circuit
JPS6065634A (en) * 1983-09-20 1985-04-15 Matsushita Electric Ind Co Ltd Tuner device
JPS60136432A (en) * 1983-12-24 1985-07-19 Matsushita Electric Ind Co Ltd Diversity receiver
JPH0167837U (en) * 1987-10-27 1989-05-01
JPH01126732U (en) * 1988-02-23 1989-08-30
JP2008035419A (en) * 2006-07-31 2008-02-14 Mitsumi Electric Co Ltd FM amplifier for car radio and FM receiver including the same
JP4903834B2 (en) * 2009-04-27 2012-03-28 株式会社日立製作所 Variable gain amplifier circuit and integrated circuit for wireless communication equipment using the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5637718A (en) * 1979-09-04 1981-04-11 Fujitsu Ten Ltd Mobile receiver

Also Published As

Publication number Publication date
JPS57173210A (en) 1982-10-25

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