JPS6324581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a demodulation circuit for modulated signals used in a codirectional data transmission system.

In data transmission, the sending side sends the clock along with the data, and the data includes the clock and sends it to the receiving side, such as Co-Directional data transmission.
In the opposite direction (contra-direction), the transmitting side sends data to the receiving side according to the clock sent from the receiving side.
For example, in the former unidirectional data transmission method, the transmitted signal is as shown in FIG. In the figure, TD is transmission data, and 8 bits D ₀ to D ₇ constitute one frame. DD is a transmission code obtained by converting this transmission data according to the following law. In other words, “1” and “0” of the 64KHz (64K bits/second) transmission data TD
are converted into 256KHz code strings "1100" and "1010", respectively, and the polarity of "1" in the code strings is inverted for each bit of data TD. for example
At D ₀ bit, “1” is negative, but at the next D ₁ bit, “1” is positive, and at the next D ₂ bit, it is “1”.
is negative, and the following applies accordingly. The transmitted signal is thus made bipolar. Just one frame D ₀ ~
D ₇ 's final data bit D ₇ does not follow the above rule;
Make it the same as the D ₆ bit in front of it. That is, in this example, since the _D6 bit "1" has positive polarity, the _D7 bit "1" also has positive polarity. This is called bipolar violation BV, and by detecting it, frame synchronization can be achieved. Note that the first
In the figure, numerals 1 and 2 are a terminal and a center or terminals, which mutually transmit data in this data transmission system.

By the way, since the above-mentioned co-directional data transmission method is rarely actually implemented, the modulation code DD
The configuration of a demodulation circuit that reproduces the original data TD from TD has not been established.

The present invention is directed to a demodulation circuit for this modulation code DD, especially to an IC.
The present invention is intended to provide a demodulation circuit that is easy to convert. The demodulation circuit of the present invention converts "1" and "0" bits of N bits/second transmission data into code strings "1100" and "1010" of 4N bits/second, respectively, and A bipolar code string in which the polarity of a 1 is inverted for each bit of data, and the polarity of the 1 in the last bit of one frame is made equal to the characteristic of the 1 in the previous bit to create a violation. A demodulation circuit for a co-directional data transmission system that uses the received bipolar code string as a transmission signal includes a circuit that converts the positive side and negative side of the received bipolar code string into first and second unipolar code strings, respectively, and a circuit that converts the received code string into N-bits. a data reproducing unit that decodes the original data using a clock of /second and 4N bit seconds;
A circuit that is set and reset by the first and second unipolar code strings, a shift register that takes in and shifts the output of the set-reset circuit with a clock of N bits/second, and a a bipolar violation detection unit consisting of a circuit that takes an exclusive OR of outputs;
and a clock extraction section that includes a digital phase lock loop and extracts the clocks of N and 4N bits/second from the received code string. will be explained in detail.

FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a time chart thereof. In Figure 2, 10 is the received bipolar code string DD
is divided into its positive side and negative side, and the polarity of the negative side is inverted to create the first and second unipolar code strings U ₁ and U ₂ of the same positive polarity.
U) Conversion circuit 11 is an OR circuit that performs the logical sum of code strings U ₁ and U ₂ to create a third unipolar code string (U ₁ +U ₂ ). 12 is the original data a by decoding the third unipolar code string (U ₁ + U ₂ )
(corresponding to TD).
It consists of a shift register 13 and a decode 14. Reference numeral 15 denotes a violation detection unit that detects a violation BV of the received bipolar code string DD, and a set/reset circuit that is set at the first unipolar code string _U1 and reset at the second unipolar code string _U2 . 16. A shift register 17 that takes in the output Q of the circuit 16 and shifts it using a 64K clock; A circuit 1 that takes the exclusive OR of each adjacent 2-bit output Q _A and Q _B within the register 17.
8, and the circuit 18 includes a protection circuit 19 that regulates the transmission of the violation detection signal b as necessary.
Provided after the . 20 is a clock extractor consisting of a digital PLL (phase lock loop) 21 and an 8MHz oscillator 22, which inputs the third unipolar code string (U ₁ +U ₂ ) and extracts the bipolar code string DD.
Outputs clocks CK ₁ and CK ₂ that are synchronized with the 256KHz clock and 64KHz clock included in the . Clock CK ₁ is used in the data reproducing section 12, and clock CK ₂ is used in the decoder 14 and shift register 1.
7. Used in the protection circuit 19 and buffer circuit 23. This buffer circuit 23 is for speed conversion, and can be converted to high speed by channel pulses from the interface LSI 24 (data output D _OUT in this example is 1.5M).
Hz) and sent to the primary group bus 25.

In the demodulation circuit with the above configuration, the shift register 13 is
3rd unipolar code string with 256K clock CK ₁
Read U ₁ + U ₂ , in the example in Figure 3 1100 from the left end
(D ₅ ), 1010 (D ₆ ), etc. and shift. The decoder 14 receives this and decodes it in units of four using a 64K clock _CK2 to generate a demodulated output a. The output a is input to the buffer circuit 23. Next, the set-reset circuit 16 resets the code string.
Since it is set at _U1 and reset at _U2 , the output Q is normally inverted alternately between "1" and "0" as shown in FIG. The leftmost one outputs "1".
When Q _A and Q _B are shifted by one bit, normally "1" and "0" are reversed, but in the case of violation, they are the same, and in this example, they are "1" and "1". Therefore, if the gate 18 performs an exclusive OR, a violation detection output b which becomes "0" at the violation point is obtained.

In this circuit, the clock extractor 20 has a digital
Since the PLL21 is used, the entire circuit is composed of digital circuits and can be easily integrated into an IC. Since the third unipolar code string (U ₁ +U ₂ ) is decoded using the generated clocks CK ₁ and CK ₂ , the output a of the decoder 14 has the same information as the original data TD of 64 KHz. Furthermore, the violation detection unit 15 using the clock CK ₂ detects the unipolar code string U ₁ +
Violation BV can be easily detected by utilizing the property of _U2 having two consecutive bits of the same polarity.

As described above, according to the present invention, it is possible to easily configure a demodulation circuit of the same direction transmission system that transmits data and clock in the same direction, and there is an advantage that it is easy to implement into an IC. In the embodiment, the unipolar code string U ₁ +U ₂ is used as the demodulation input, but it is also possible to use the received code string DD as the demodulation input and to invert the negative polarity "1" to the positive polarity for decoding. Further, the input to the clock extraction circuit may be _U1 or _U2 instead of _U1 + _U2 .

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a co-directional transmission system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart thereof. In the figure, 10 is a bipolar/unipolar conversion circuit, 12 is a data reproducing section, 14 is a decoder, and 15
1 is a violation detection section, 16 is a set-reset circuit, 17 is a shift register, 18 is an exclusive OR circuit, 20 is a clock extraction section, and 21 is a digital PLL.

Claims (1)

[Claims] The “1” and “0” bits of the 1N bit/second transmission data are each converted into a 4N bit/second code string “1100”,
1010”, and inverts the polarity of “1” in the code string for each bit of data, and at the last bit of one frame, the polarity of “1” is changed to the “1” of the previous bit. In a demodulation circuit of a codirectional data transmission system in which a bipolar code string with a violation equal to the characteristic and given a violation is used as a transmission signal, the positive side and the negative side of the received bipolar code string are used as first and second unipolar codes, respectively. A circuit that converts the received code string into a code string, a data reproducing section that decodes the received code string into original data using clocks of N bits/second and 4N bit seconds, and a data reproducing section that is set and reset using the first and second unipolar code strings. A bipolar violation circuit consisting of a circuit that takes in and shifts the output of the set-reset circuit at a clock rate of N bits/second, and a circuit that takes the exclusive OR of the outputs of two adjacent bits in the shift register. It is equipped with a detection section and a digital phase lock loop to detect N and
A demodulation circuit for co-directional data transmission, characterized in that it comprises a clock extractor for extracting the clock at 4N bits/second.