JPS6325679B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention provides various fundamental waves (BASIC WAVE).
This invention relates to a wave generator for an electronic musical instrument.

One type of electronic musical instrument is the music synthesizer, but most of this type of electronic musical instrument is based on analog circuits, and there are almost no such electronic musical instruments that have been realized using digital methods.

However, various researches have been conducted on methods for digitally obtaining musical sound waveforms in electronic organs and the like, and some of them appear to have been put to practical use. However, how to obtain such a musical sound waveform,
In particular, methods for digitally storing musical sound waveforms in advance in ROM and reading them out based on scale frequencies can be broadly classified into the following three types.

That is, in the first method, the ROM is addressed by the output of an address counter that cumulatively adds a constant value. This method samples the same waveform regardless of frequency, so it is necessary to use a band-limited waveform to prevent aliasing (aliasing) from occurring due to the sampling theorem for high-frequency musical tones. Waveforms that are band-limited in this manner have the disadvantage that low-frequency waveforms produce timbres with few high-order harmonics. In addition, in this first method, since the number of address steps is small, the same address is specified several times in succession, which has the disadvantage of causing so-called jitter. Furthermore, when the number of address steps is increased to prevent the occurrence of jitter, and the number of quantization bits is also increased to further reduce quantization noise, there is of course the problem that the storage capacity of the ROM becomes extremely large. As an improvement on the first method, there is a technique disclosed in Japanese Patent Application Laid-Open No. 119913/1983. According to this, the shape of the waveform is changed depending on how the address signal is given and how it is interpolated, and the timbre of the musical tone generated based on the waveform stored in the same memory is changed over time from the start of sound generation. I'm trying to change it.

However, even with the technology disclosed in this publication, the amount of harmonic components included changes depending on the pitch of the musical sound to be generated, and naturally the higher harmonics decrease in the lower range, making music It is not suitable as a sound source for a synthesizer, and it is impossible to obtain a waveform with a spectrum band-limited at 1/2 of the sampling frequency _fs over the entire range.

In the second method, one cycle of reading from the ROM is an integral multiple of the output cycle of the basic clock. With this method, the frequency of the musical tone to be sounded is an integral multiple of the basic clock, so no jitter or quantization noise occurs. The frequency must be several hundred times higher than the frequency of the highest note, and in order to achieve effects such as biprato and portamento through digital control, the frequency of the basic clock must be raised even higher, which requires a large hardware configuration. There are drawbacks. Furthermore, as mentioned above, since the period of the readout waveform is set to an integer number of basic clocks, the intervals between address steps are generally not equal, and there is also a drawback that the timbre changes slightly for each scale.

The third method is to read out the ROM using a variable clock. Since this type of clock outputs the variable clock from an analog oscillator, it does not generate the above-mentioned aliasing distortion, jitter, or quantization noise, and also reduces the content of high-order overtones in the case of low-frequency waveforms. Furthermore, while there is no change in timbre for each scale, the disadvantage is that the frequency generating section cannot be multiplexed, so polyphonic musical tones cannot be obtained from a single waveform synthesizer, and the hardware configuration is large.

This invention was made under the above-mentioned circumstances, and its purpose is to make it possible to generate fundamental waves such as rectangular waves through arithmetic processing by digital circuits without using a waveform ROM, and to make it possible to generate fundamental waves such as rectangular waves without using a waveform ROM. To generate a limited waveform,
To provide a wave generator for an electronic musical instrument, which interpolates a waveform of a fixed period in a part where the amplitude level of a musical sound waveform suddenly changes, regardless of a specified pitch, using a function curve.

An embodiment in which the present invention is applied to a music synthesizer will be described below with reference to the drawings. FIG. 1 shows a system configuration diagram of a music synthesizer according to the above embodiment. In the figure, a keyboard 1 is equipped with a plurality of keys, and each key outputs a key operation signal. The switch section 2 includes switches for selecting various sound source waveforms (fundamental waves) such as a rectangular wave, PWM wave (asymmetric square wave), and sawtooth wave, and switches for controlling a digital filter 6, an envelope generator 7, etc., which will be described later. Various switches are provided. The respective outputs from the keyboard 1 and the switch section 2 are both supplied to a CPU (central processing unit) 3.

The CPU 3 is a device that controls all operations of this music synthesizer, and is composed of a microprocessor, etc., but its details will be omitted.

A ROM (read only memory) 4 is a memory that stores the scale frequency code β. And the scale frequency code β corresponding to the operation key on keyboard 1
The address data to read is output from CPU3,
Supplied to ROM4. Further, the read scale frequency code β is supplied to the wave generator 5.

The wave generator 5 receives the above-mentioned scale frequency code β and the data α, γ, supplied from the CPU 3.
This circuit creates the above-mentioned sound source waveform by digital calculation based on K, and the created waveform data is supplied to the digital filter 6. The digital filter 6 removes a part of the harmonic components in the waveform data based on the control signal from the CPU 3, and supplies the output to the envelope generator 7. Also, envelope generator 7 is CPU3
Based on the control signal from the digital filter 6, an envelope is applied to the output of the digital filter 6 to produce a musical tone signal, which is then supplied to the digital/analog converter 8. The digital/analog converter 8 is a circuit that converts the inputted digital musical tone signal into an analog musical tone signal, and this analog musical tone signal is sent to an amplifier 9 connected to the output side of the digital/analog converter 8. A musical tone is emitted through the speaker 10. This digital filter 6 is based on Japanese Patent Application No. 55-53179 ``Digital Filter Device,'' and the envelope generator 7 is based on Japanese Patent Application No. 53179.
No. 56-74244 “Envelope control method for electronic musical instruments”
can be applied.

Next, referring to FIG. 2, the wave generator 5
The specific configuration will be explained. A shift register 17 outputs signals to the A input terminals A ₁₅ to _{A 0} of the full adder 15 and circulates them. 16 bit data is applied. Also B
16-bit constant value data α (X ₁₅ -X ₀ ) from the CPU 3 is applied to the input terminals B ₁₅ -B ₀ . A high level signal "H" is always applied to the terminal Cin. Therefore, the full adder 15 subtracts the input data α to the B input terminal from the input data at the A input terminal, and outputs the resultant data from the S output terminals _S15 to _S0 , which are connected to the output side of the full adder 15. It is applied to the A input terminals A ₁₅ to A ₀ of the full adder 16. The B input terminals B ₁₅ to _{B 0} of this full adder 16 are connected to the scale frequency code β (in the case of creating a rectangular wave or sawtooth wave) output from the gate circuit G ₁ or to the gate circuit
The data β±(β-K)γ (in the case of PWM wave creation) output from G ₂ are outputted from AND gates 18 ₁₅ to 18, respectively.
Preset through ₀ . Note that the carry output output from the terminal Cout of the full adder 15 is applied to each control input terminal of the AND gates 18 ₁₅ to _{18 0} via the inverter 19.

The result data of full adder 16 is S output terminal S ₁₅ ~
It is output from _S0 and applied to the shift register 17 connected to the output side of the full adder 16. For example, if this music synthesizer is an 8-tone polyphonic synthesizer, the shift register 17 is composed of 8 stages of 16-bit capacity shift registers connected in cascade. The circuit shown in FIG. 2 executes time-sharing processing operations under the control of the CPU 3.

The lower 9 of the output data of the shift register 17
Bit data is exclusive or gate 20 ₈ ~ 20 ₀
is applied to Further, each of the 10 to 15 bits of the output data is applied to each control input terminal of AND gates 22-1 to 22-6 via inverters 21-1 to 21-6, respectively. Furthermore, the most significant bit of the output data is applied to the other input terminal of AND gate 22-6 via inverter 21-7. AND gates 22-1 to 22-6 are connected in series as shown, so the output of AND gate 22-6 is applied to the other input terminal of AND gate 22-5, and the output of AND gate 22-6 is applied to the other input terminal of AND gate 22-5. The outputs -5 to 22-2 are applied to the other input terminals of the AND gates 22-4 to 22-1 at the subsequent stage. The output of AND gate 22-1 is then applied to exclusive OR gates 20 ₈ to 20 ₀ .

The output of exclusive OR gates 20 ₈ to 20 ₀ is ROM
(Read-only memory) 23 is applied to A input terminals A ₈ to A ₀ as address data. The ROM 23 stores 1/4 waveform sine wave data shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave generated by the wave generator 5 suddenly changes.
The 7-bit waveform data read from output terminals O ₆ -O ₀ of 3 is applied to OR gates 24 ₆ -24 ₀ .

The output of the AND gate 22-2 is also applied to the OR gates 24 ₆ to 24 ₀ via an inverter 25 and a transfer gate 26. The outputs of the OR gates 24 ₆ -24 ₀ are applied to one end of each of the exclusive OR gates 27 ₆ -27 ₀ . The output of the AND gate 22-1 is applied to the other ends of the exclusive OR gates 27 ₆ to 27 ₀ via an inverter 28 and a transfer gate 29. The outputs of the exclusive OR gates 27 ₆ to 27 ₀ are sent to the A input terminal A ₆ of the full adder 30 configuring the polarity inversion circuit.
~A applied to ₀ . Further, the output of the AND gate 22-1 is applied to the A input terminal _A7 of the full adder 30 via the inverter 28, transfer gate 29, and inverter 31. Furthermore, an AND gate 22- is connected to the input terminal Cin of the full adder 30.
1 is applied via an inverter 28 and a transfer gate 29, and the output of a polarity inversion circuit 32, which will be described later, is applied via a transfer gate 33. And the output end S ₇ of the full adder 30
The data output from ~ _S0 is sent to the digital filter 6 via transfer gates ₃₄₇ ~ ₃₄₀ .

The transfer gate 26 is controlled to open or close by applying a control signal output from the CPU 3 to the gate when a switch is operated to designate a rectangular wave or a PWM wave, respectively. Further, the control signals output from the CPU 3 are directly applied to the transfer gates 29 and 35 when the switch for specifying the sawtooth wave is operated, and the control signals are applied to the transfer gate 33 via the inverter 36 to control opening and closing. Further, transfer gates 34 ₇ to 34 ₀ connect the output of the AND gate 22-2 to the inverter 2.
5. The voltage is applied to the gates via the transfer gate 35 and the inverter 37 to control opening and closing.

A scale frequency code β and data K (constant value) are applied to the subtraction circuit 41, respectively. The resulting data β-K is then applied to a multiplication circuit 42 and a division circuit 44, respectively. The multiplication circuit 42 also receives data γ (this data γ takes a value of 0≦γ≦1,
) is applied to determine the duty ratio, and the resulting data (β-K)γ is added to the adder/subtractor circuit 4.
3 is applied. A scale frequency code β is applied to the other end of this addition/subtraction circuit 43, and a control input ±
The output of the polarity inverting circuit 32 is applied to.
Then, the result data β±(β−K) of the addition/subtraction circuit 32
γ is applied to gate circuit _G2 . Note that the gate circuit G ₁ is controlled to open and close by a control signal output from the CPU 33 when a switch that specifies a rectangular wave and a sawtooth wave is operated, and the gate circuit G ₂ is
Opening/closing is controlled by a control signal output from the CPU 3 when operating a switch specifying a PWM wave.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . The resulting data M-K is then applied to the division circuit 44. Then, the result data of the division circuit 4 (M-K)/(β-
K) is sent to the digital filter 6 as sawtooth wave data via transfer gates ₄₆₇ to ₄₆₀ . Transfer Gate 46 ₇ ~ 46 ₀
The output of the AND gate 22-2 is applied to each gate via the inverter 25, transfer gate 35, and inverters 37 and 47, and opening/closing is controlled.

The polarity inversion circuit 32 includes a shift register 48 and an exclusive OR gate 49 connected to the output side of the shift register 48. The other input terminal of the exclusive OR gate 49 receives the output from the output terminal C' of the full adder 15.
applied via. Further, the output of the exclusive OR gate 49 is fed back to the input side of the shift register 48. In the case of the above-mentioned 8-tone polyphonic synthesizer, the shift register 48 is formed by cascading 8 stages of shift registers each having a capacity of 1 bit.
Further, the output terminal C' of the full adder 15 outputs an "H" level signal (carry) when the result data of the full adder 15 reaches "512".

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 14. First, referring to the time chart in FIG.
The operation when generating is explained below. In this case, first, turn on the switch for specifying the rectangular wave on the switch section 2, and operate the other necessary switches. Therefore, by turning on the square wave designation switch, the CPU 3 sets the gate circuits G ₁ and G ₂ of the wave generator 5 to the "H" (i.e., "1") level or "L" (i.e., "0") level, respectively. ”) outputs a level signal. Therefore, from then on, gate circuit G ₁ is opened and gate circuit G ₂ is closed.
Further, the CPU 3 outputs a "1" level signal to the transfer gate 26, and outputs a "0" level signal to the transfer gates 29 and 35. Therefore, from now on, transfer gate 26
is opened, and transfer gates 29 and 35
is closed. In addition, the transfer gate 2
As a result, transfer gates 33 and 34 ₇ to 34 ₀ are opened, and transfer gates 46 ₇ to 46 ₀ are closed.
is closed.

A case in which, for example, one upper key on the keyboard 1 is turned on in the above state will be described below. In this case, when the above one key is turned on, CPU ₃
Predetermined address data for reading out the scale frequency code β corresponding to the operation key from the ROM ₄ is output to the ROM ₄ . As a result, the scale frequency code β is read from the ROM ₄ and supplied to the wave generator 5. Then, this scale frequency code β is applied to the AND gates 18 ₁₅ to 18 ₀ via the gate circuit G ₁ which is being opened. Now, the output of the output terminal Cout of the full adder 15 is "0", so the AND gates 18 ₁₅ to 18 ₀ are being opened due to the output "1" of the inverter 19. Therefore, the scale frequency code β is applied to the B input ends B 15 _to B ₀ of the full adder 16 via the AND gates 18 ₁₅ to 18 ₀ . On the other hand, at this time, 16-bit all "0" data is applied from the S output terminals S ₁₅ to _{S 0} of the full adder 15 to the A input terminals A ₁₅ to _{A 0} of the full adder 16. Therefore, the result data of the full adder 16 at that time will be data with the same value as the set scale frequency code β, and S
When output from the output terminals S ₁₅ to _{S 0} , the signals are input to the shift register 17 . After being shifted, this data is outputted from the shift register 17 and is input cyclically to the A input terminals A ₁₅ to A ₀ of the full adder 15, as well as to exclusive OR gates 20 ₈ to 20 ₀ and inverters 21 ₇ to 21 _1. .

By the way, in the case of this embodiment, the values of the frequency code β of each scale are all output as values larger than "1024". In other words, the top 11 of the 16-bit data
~16 bits always contain data of "1". Therefore, when the scale frequency code β is set when one key is turned on, and the shift register 17 outputs data of the same value, the output of the AND gate 22-2 is always "" as shown in FIG. 4e. 0” level.
Therefore, the output of the AND gate 22-1 is also at the "0" level while the output of the AND gate 22-2 is "0" as shown in FIG. 4B. Furthermore, at this time, the output of the inverter 50 is at the "1" level as shown in FIG. 4b, and therefore the output of the polarity inverting circuit 32 is at the "0" level as shown in FIG. 4d. As a result, the “0” level signal of the AND gate 22-1 is transmitted to the exclusive OR gates 20 ₈ to 2
₀₀ , and the data of the lower 9 bits of the output of the shift register 17 is applied as is to the A input terminals _A8 to _A0 of the ROM 23. Also and gate 2
The “1” level signal obtained by inverting the “0” level signal of 2-2 by the inverter 25 is output to the OR gate 2.
applied to 4 ₆ to 24 ₀ , therefore OR gate 2
Signals of "1" level are outputted from the gates 4 ₆ to 24 ₀ , respectively, and applied to one end of each of the exclusive OR gates 27 ₆ to 27 ₀ . Therefore, exclusive or gate 27 ₆ ~ 27 ₀
The "0" level output of the polarity inversion circuit 32 is applied to each other end of the polarity inversion circuit 32. Therefore, all outputs of the exclusive OR gates 27 ₆ to 27 ₀ become "1" level signals. Further, the output of the inverter 31 is also at the "1" level. As a result, full adder 30
All "1" data is input to the A input terminals _A7 to _A0 . Also, the carry input terminal of Full Adder 30
Cin is the output of the polarity inversion circuit 32 (“0” signal)
is inputting. Therefore, the result data of the full adder 30 at this time is output as 8-bit all "1" data from the S output terminals _S7 to _S0 , and is sent to the digital filter 6 via the transfer gates ₃₄₇ to ₃₄₀ , which are being opened. Ru. The waveform diagram in FIG. 4a shows a rectangular wave sent to this digital filter 6. Therefore, digital filter 6
Then, the specified overtone component is removed under the control of the CPU 3, and the envelope generator 7 applies an envelope to the output thereof, and starts generating and emitting musical tones of the scale of the operation keys.

When data with the same value as the set scale frequency code β is circulated and input to the A input terminals A ₁₅ to A ₀ of the full adder 15, the constant value data output from the CPU 3 is output to the B input terminals B ₁₅ to B ₀ . α is input as 16-bit data. In addition, since the carry input terminal Cin is always set to the "H" level, the full adder 15 executes the first subtraction operation of β - α at this time, outputs the resulting data from the S output terminal, and the full adder 16 Apply to the A input terminal. In addition, "-α" in the above formula "β-α" is α ₀ , α ₁ , ... α ₁₅ in Figure 2.
It corresponds to the value obtained by subtracting "-1" from the value of . When this subtraction operation is executed, the output of the carry output terminal Cout of the full adder 15 becomes "1" level, so the output of the inverter 19 becomes "0", and the AND gates 18 ₁₅ to 18 ₀ are closed. Therefore, input of the scale frequency code β to the B input terminal of the full adder 16 is blocked. Therefore, the result data of the full adder 16 at this time is the same as the result data of the first time of the full adder 15, and is applied to the shift register 17. When this first result data is output from the shift register 17, it is circulated to the A input terminal of the full adder 15, while exclusive OR gates 20 ₈ to 20 ₀ and inverters 21-7 to
21-1. After this first calculation, the data input states of the A input terminal and the carry input terminal Cin of the full adder 30 are unchanged from the previous time, so that 8-bit all "1" data is sent to the digital filter 6. full adder 15,
ANDGATE 18 ₁₅ ~ 18 ₀ , FULL ADDER 16,
Thereafter, the shift register 17 repeats the same cumulative subtraction operation as the first subtraction operation described above until the resulting data, ie, the output of the shift register 17, becomes "1024" (see FIG. 4f).
During this time, the input states to the A input terminal and the carry input terminal Cin of the full adder 30 do not change either, so during this time, 8-bit all "1" data is continuously sent to the digital filter 6. When the output of the shift register 17 becomes smaller than "1024" by the next subtraction operation, it means that the data in the upper 11th to 16th bits of the shift register 17 are all "0". Eventually, the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 4e. Therefore, from now on, the output of the inverter 25 becomes "0" level and is input to the OR gates 24 ₆ to 24 ₀ .

On the other hand, during the cumulative subtraction operation in which the output of the shift register 17 is from "1024" to "512", the 10th bit data of the output of the shift register 17 holds "1", so during this period, Figure 4b
As shown in , the output of the AND gate 22-1 continues to be “0” and the exclusive OR gates ₂₀
0 ₀ is supplied. For this reason, the above "1024" ~
During "512", the lower 9 bit data of the output of the shift register 17 continues to be applied to the A input terminal of the ROM 23 as it is. During the above period, the output of the polarity inversion circuit 32 continues to be at the "0" level as shown in FIG. 4d.

Therefore, assuming that the output of the shift register 17 becomes "1024" or less, for example "1023", then the lower 9 bits of the output of the shift register 17 are all "1", It is applied to the A input terminal of the ROM23. Therefore, the ROM 23 is addressed by this 9-bit all "1" address data, and 7-bit all "1" data is read out as shown in FIG. This 7-bit all "1" data is passed through exclusive OR gates ₂₇₆ to ₂₄₀ through OR gates ₂₄₆ to 240.
27 Enter ₀ . As mentioned above, exclusive or gates 27 ₆ to 27 ₀ and full adder 30
A "0" level signal is still being input to the carry input terminal Cin of the full adder 30, so 8-bit all "1" data is input to the A input terminal of the full adder 30, and as a result, the data is also 8-bit all "1". It is output as data and sent to the digital filter 6.

Next, when the output of the shift register 17 becomes a value smaller than "1023" by data α due to the next cumulative subtraction operation, the ROM 23 is stored at an address smaller by α than the above-mentioned 9-bit all "1" data (i.e., "511"). Addressed by data. Therefore, as can be seen from Figure 3, the ROM
23, data smaller by a predetermined value than the above-mentioned 7-bit all "1" data, that is, data with an amplitude value slightly smaller than the previous one, is read out, and the data with the amplitude value is output as is without having its polarity inverted by the full adder 30. The signal is sent to the digital filter 6.

Thereafter, in the same way, the output of the shift register 17 decreases by α by each cumulative subtraction operation,
Until the value reaches "512", the digital data in the ROM 23 is sequentially addressed in the direction of decreasing by α, and accordingly, each time, amplitude value data with a smaller value than the previous one is read out. Ru. During this time, the input state of data to the A input terminal and the carry input terminal Cin of the full adder 30 is the same as described above, and accordingly, the above-mentioned sequentially decreasing amplitude value data is sent to the digital filter 6. . When the output of the shift register 17 is "512", the ROM 23
will be addressed by address data of 9 bits all "0".

Next, the result data of cumulative subtraction operation is full adder 1
5, when the value changes from “512” to “511” or less, the output terminal _C1 of full adder 15 changes to “1”.
A signal is output, and in response, one pulse signal is output from the inverter 50 as shown in FIG. 4c. As a result, as shown in FIG. 4d, the output of the polarity inversion circuit 32 is subsequently inverted to the "1" level, and the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31,
The signals are applied to the carry input terminals Cin of the full adder 30, respectively.

Therefore, when data below "511" is output from the shift register 17 as shown in Figure 4f, the upper 10 to 16 bits of the output are all "0".
Therefore, the output of the AND gate _22-1 changes to the " ₁ " level as shown in FIG. is applied, and its output is inverted to 9 bits all “0”.
It is applied to the A input terminal of the ROM23. Therefore, the cumulative subtraction result data is sequentially from "511" to "0".
While the address data is decreasing by α, the ROM 23 is sequentially addressed in the direction in which the address data increases from all "0" to all "1". The amplitude value data read as a result is the third
As shown in the figure, the amplitude value data increases sequentially, and is input to the A input terminals A ₆ to A 0 of the full adder via exclusive OR gates 27 ₆ to _{27 0} , and “0” is input to the A input terminal A ₇ . signal is input, and a “1” signal is also input to the carry input terminal Cin, so the data output from the full adder 30 during this period is ROM
It becomes equal to the amplitude value data read out from 23 with the polarity inverted, and the data is sent to the digital filter 6.

As shown in FIG. 4 f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave in FIG. interpolated accordingly.

When the cumulative subtraction result becomes "0" or less as described above, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next subtraction operation, and as a result, the AND gates 18 ₁₅ to 18 ₀ are temporarily opened. The scale frequency code β is applied to the B input terminals B ₁₅ to _{B 0} of the full adder 16. and full adder 16
When the data given to the A input terminal of 1 and this scale frequency code β are added, and the resulting data is output from the shift register 17, the above data, that is, the scale frequency code β is greater than "1024" as described above. Therefore, for the reason mentioned above, from this point on, as shown in Fig. 4 b and e,
Each output of AND gates 22-1 and 22-2 is inverted to "0" level.

After the scale frequency code β is set again as described above,
The cumulative subtraction operation by α is executed, and the output of the shift register 17 decreases from β by α to “1024”.
decreases to During this period, 8-bit all "0" data is input to the A input terminals _A7 to _A0 of the full adder 30, and the carry input terminal
Since a "1" signal is input to Cin, 8-bit all "0" data is sent to the digital filter 6 during this period.

While the cumulative subtraction result becomes ``1024'' or less and further decreases to ``512,'' the AND gate 22-2 is first activated from the point at which it becomes smaller than ``1024'', that is, ``1023'' or less, as shown in Figure 4 f. The output is inverted to "1" level. Therefore, between "1023" and "512", the output of the full adder 30 moves the ROM 23 from its maximum address (9 bits all "1" data) to its minimum address (9 bits all "0" data).
It is equal to the inverted polarity of the amplitude value data that is sequentially addressed and read out.

Furthermore, when the cumulative subtraction result becomes "512", "1" is output from the output terminal C' of the full adder 15 as described above.
The signal is output, and in response, the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 4d. Next, when the cumulative subtraction result becomes "511" or less, the output of the AND gate 22-1 is inverted to the "1" level. As a result, as mentioned above, when the cumulative subtraction result is between "511" and "0", the output of the full adder 30 is read out by sequentially addressing the ROM 23 from the minimum address to the maximum address. The data matches the amplitude value data and is sent to the digital filter 6.

As shown in FIG. 4f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave shown in FIG. 4a is interpolated by the waveform data from the ROM 23. When the cumulative subtraction result becomes "0" or less, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next calculation, and the scale frequency code β is set in the full adder 16 again. Rectangular wave calculation processing is started.

With the above, the arithmetic processing operation for generating a rectangular wave for one cycle is completed. For example, the calculation period in which the output of the shift register 17 changes from "0" to "0" (that is, the period during which each scale frequency code β of the previous and current scales is set) shown in FIG.
When the T' sampling period is Ts, the calculation period T' is expressed by the following equation (1).

T′=Ts・β/α …(1) Also, the frequency of the rectangular wave generated as described above _{is 0}
is expressed by the following equation (2) when the sampling frequency is _s .

₀ = 1/2T' = _s /2·α/β (2) Next, the operation in the case of generating a PWM wave will be explained with reference to FIG. First, PWM on switch section 2
Turn on the wave designation switch. As a result, gate circuit _G1 is closed and gate circuit _G2 is opened.
Also, transfer gates 26, 33, 34 ₇
~34 ₀ is opened, and transfer gate 29,
35, 46 ₇ to 46 ₀ are closed. In the above state, when one key on the keyboard 1 is turned on, the calculation and generation process of the PWM wave is started.

An explanation will now be given starting from the timing when the shift register output shown in FIG. 5f is "0"("0" at the left end of the figure). That is, at this point, the output of the polarity inversion circuit 32 is at the "1" level as shown in FIG _.
7 ₀ , a “1” signal is applied to the carry input terminal Cin of the inverter 31 and the full adder 30, respectively.

On the other hand, the subtraction circuit 41 outputs the result data β-K and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data (β-K)γ to the addition and subtraction circuit 43.
is giving to Furthermore, the addition/subtraction circuit 43 outputs result data β+(β-K)γ, which is applied to the gate circuit _G2 . For example, the data K is "1024", and the data γ that determines the duty ratio is
It takes a value of 0≦γ≦1.

Therefore, when the above-mentioned one key is turned on, data β+(β-K)γ is set in the full adder 16 at the start of arithmetic processing in accordance with an operation similar to that described for the rectangular wave generation operation. Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data β+(β−K)γ. Until the resulting data, that is, the output of the shift register 17, decreases by α to "1024", the AND gate 2
2-1, the inverter 50, the polarity inverting circuit 32, and the AND gate 22-2 each output “0”, “1”,
Each level of "1" and "0" is held. Therefore, during this period, the read waveform from the ROM 23 is invalidated, and the data output from the full adder 30 and sent to the digital filter 6 becomes 8-bit all "0" data.

Cumulative subtraction result data, ie shift register 17
When the output is less than "1024", AND gate 22
-2 output is inverted to "1" level. Therefore, while the above result data changes from "1024" to "512", the polarity of the amplitude value data read out by sequentially addressing the ROM 23 from the maximum address to the minimum address is read from the full adder 30. The signal is output and sent to the digital filter 6.

When the resultant data becomes "512", the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 5d, and a subtraction command is given to the addition/subtraction circuit 43.
Further, a “0” signal is applied to the carry input terminals Cin of the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30 . Further, when the resultant data becomes less than "511", the output of the AND gate 22-1 is inverted to the "1" level as shown in FIG. 5B.
Therefore, until the result data changes from "511" to "0", the output of the full adder 30 is
The amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address is output as is, and the data is output directly to the digital filter 6.
sent to.

When the resultant data becomes "0" or less as shown in FIG. In addition, as shown in FIGS. 5b and 5c, when the result data is "0" or less, the AND gate 2
Each output of 2-1 and 22-2 is inverted to "0" level. When the data β-(β-K)γ is set in the full adder 16, the subtraction operation by α is started again. As a result, the output of the full adder 30 is held as 8-bit all "1" data until the data is reduced to "1024". And the fifth
When the resultant data becomes smaller than "1024" as shown in FIG. 5F, the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 5E. Therefore, while the result data decreases to "512", the output of the full adder 30 becomes the same data as the amplitude value data read out by addressing the ROM 23 from the maximum address to the minimum address, and sends it to the digital filter 6. .

Next, while the result data becomes smaller than "512" and further decreases to "0", the AND gate 22-1,
Each output of the polarity inversion circuit 32 is both inverted and held at the "1" level. Therefore, the output of the full adder 30 during this period is data obtained by inverting the polarity of the amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address, and is sent to the digital filter 6.

This completes the calculation process for one cycle of the PWM wave,
The following is a repetition of what has been described above. The frequency ₀ is the same as in the case of a rectangular wave, and is expressed by equation (2).

Next, the case of a sawtooth wave will be explained with reference to FIG. First, the sawtooth wave designation switch on the switch section 2 is turned on. As a result, gate circuit G ₁
is opened, and gate circuit _G2 is closed. Further, transfer gates 29 and 35 are opened, and transfer gates 26 and 33 are closed. In the above state, when one key on the keyboard 1 is turned on, arithmetic processing for generating a sawtooth wave starts.

Now, the output of the shift register 17 shown in FIG.
is set in the full adder 16. Therefore, when this scale frequency code β is then output from the shift register 17, since the code β is data larger than "1024", the AND gates 22-1 and 22 are output as shown in FIGS. 6b and 6c, respectively. -2 outputs are both inverted to "0" level. Since the output of the AND gate 22-2 becomes "0", the output of the inverter 37 becomes "0" and the output of the inverter 47 becomes "1", and accordingly, the transfer gates 34 ₇ to 34 ₀ are closed. Then, the transfer gates 46 ₇ to 46 ₀ are opened. Further, in the full adders 15 and 16, the shift register 17, and the AND gates 18 ₁₅ to 18 ₀ , an cumulative subtraction operation for subtracting data α (constant value) from the scale frequency code β starts. Since the output state of the AND gate 22-2 does not change until the data as a result of the cumulative subtraction operation decreases to the value "1024", the output of the division circuit 44 to the digital filter 6 is applied to the open transformer. It is sent out via argates 46 ₇ to 46 ₀ . The output data M-K of the subtraction circuit 45 is input to the input terminal A of the division circuit 44, and the output data β- of the subtraction circuit 41 is input to the input terminal B.
K is applied to each. Therefore, the output data H' of the division circuit is expressed by the following equation (3).

H'=M-K/β-K×H...(3) where M is the output of the shift register 17, K is a constant value, "1024" in this example, and H is the maximum amplitude value, In this example, it is "256".
Therefore, equation (3) can be written into the following equation (4).

H'=M-1024/β-1024×256...(4) As can be seen from equation (4), shift register 17
When the output M of , that is, the data as a result of cumulative subtraction becomes "1024", the data sent to the digital filter 6 becomes "0". When the resultant data becomes "1024" or less as shown in FIG. 6(d), the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 6(c). Therefore, transfer gates 34 ₇ to 34 ₀ are opened, and transfer gates 46 ₇ to 46 ₀ are closed. Until the above result data decreases to "512", the output of the AND gate 22-1 is held at the "0" level, so the output "1" of the inverter 28 is excluded via the open transfer gate 29. The signals are applied to the carry input terminals Cin of the target OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30, respectively. In other words, when the result data is between "1023" and "512", the full adder 30 outputs data in which the polarity of the amplitude value data read out by addressing the ROM 23 sequentially from the highest address to the lowest address is output, and the transfer data is outputted from the full adder 30. The signal is sent to the digital filter 6 via the argates ₃₄₇ to ₃₄₀ .

When the resultant data becomes smaller than "512", the output of the AND gate 22-1 is also inverted to the "1" level, as shown in FIG. 6b. Therefore, “1”
After the signal is applied to the exclusive OR gates 22 ₈ to 22 ₀ , the ROM 23 is addressed from the lowest address to the highest address, while the output “0” of the inverter 28 is applied to the exclusive OR gates 27 _{6 to 27 6} .
27 ₀ is applied to the carry input terminal Cin of the inverter 31 and the full adder 30, respectively. Therefore, between "511" and "0", the amplitude value data read from the ROM 23 is sent to the digital filter 6 as is. And then again full adder 16
A scale frequency code β is set to .

This completes one cycle of sawtooth wave generation. The frequency ₀ is expressed by the following equation (5).

₀ = _s・α/β …(5) That is, as can be understood from equation (5), in the case of a sawtooth wave, unlike the case of a rectangular wave or PWM wave, it is necessary to double the scale frequency code β. There is.

The operations for generating square waves, PWM waves, and sawtooth waves explained above are based on the case where only one key on the keyboard 1 is turned on, but in this example, the music synthesizer is used for eight-note polyphonic. Therefore, even if up to eight keys are turned on at the same time, each circuit in FIGS. 1 and 2 can simultaneously generate the fundamental wave for each key by time-sharing processing operation of 8 channels. can be done, but detailed explanation thereof will be omitted.

FIGS. 7 to 9 show the structure of overtone components of the sawtooth wave generated by the above embodiment at three frequencies based on experimental data. Therefore, in either case, the sampling frequency _s is
It is 64KHz.

In Figure 7, the frequencies of the fundamental tone of this sawtooth wave are α=831, β=240640, as shown in figure a.
221.011 obtained by substituting _s = 64KHz into the above equation (5)
It is Hz. As can be seen from FIG. 7b, the frequency ( _s /2=32 KHz) at which aliasing distortion occurs according to the sampling theorem corresponds to the 145th harmonic component. The levels of the fundamental tone and overtones from the 1st to the 144th order are both higher than the levels of the overtones of the 145th order and above, making them good. It has been experimentally confirmed that these high-order overtones of _s /2 or higher pose no problem in terms of hearing. Furthermore, as shown in the figure, there are taps in which each overtone component does not occur near the 176th order and near the 293rd order.

Figure 8 shows the harmonic structure of a sawtooth wave with a frequency different from that in Figure 7. As shown in Figure a, α = 831, β = 120320, and _s = 64KHz are substituted into equation (5). shows a sawtooth wave with a frequency of 442.02Hz obtained by
show. As can be seen from figure b, the frequency of the 73rd harmonic corresponds to the above-mentioned 32KHz. In this case as well, the levels of the fundamental tones and overtones of the 1st to 72nd orders are higher than the levels of overtones of the 73rd order and above. There are also two dips near the 88th and 146th orders.

FIG. 9 shows the overtone structure of the sawtooth wave at a different frequency from FIGS. 7 and 8. The frequency is a in the same figure.
As shown in , it is 884.04Hz obtained by substituting α = 831, β = 60160, and _s = 64KHz into equation (5). As shown in figure b, the frequency of the 37th harmonic is 32KHz.
roughly equivalent to. In addition, the levels of the fundamental tone and overtones of the 1st to 36th orders are also higher than the levels of the overtones of the 37th order and above. Similarly, dips occur at the 44th and 72nd positions.

Figures 7 to 9 show three types of frequencies that are related to overtones, but the sawtooth wave of each frequency also has a ROM2
Since the interpolated period (calculation period) in step 3 is set to a constant value of 1024, the characteristics of the harmonic composition (spectrum) are constant even if the frequency is different, and the frequency at which dips occur at two locations at each frequency is equal to the frequency. It remains almost constant regardless of (i.e. around 38897.9Hz and 64.5KHz). This also applies to frequencies other than those mentioned above.

Figures 10 to 12 show three types of frequencies, 221.011Hz, 442.021Hz, and
It shows the overtone composition of the 884.042Hz square wave.
Therefore, in this case as well, α=
831, β=240640 or β=120320 or β=
60160, _s = 64KHz, and the interpolation calculation period is "1024". As is obvious from the figure, this rectangular wave has exactly the same characteristics as the sawtooth wave described above. Furthermore, it goes without saying that the PWM wave is similar to the rectangular wave.

As can be seen from the above, if the width of the interpolation portion (calculation period) is constant regardless of the scale frequency, a band-limited waveform at a constant frequency can be easily obtained at all scale frequencies.

FIGS. 13 and 14 illustrate changes in overtone structure when the above-mentioned interpolation calculation periods are made different for two sawtooth waves having the same frequency. That is, in Figure 13, as shown in Figure 13a, α = 543, β = 78592, _s = 64KHz are substituted into equation (5) to make the frequency 442.2Hz, and the interpolation calculation period is ``1024''. On the other hand, in Fig. 14, α, β, _{and s} are the same as shown in a of the same figure,
In addition, the interpolation calculation period is doubled to "2048". That is, this can be realized by changing the value of data K from the CPU 3. Therefore, the first
Comparing Figure 3b and Figure 14b, it is clear that the levels of overtone components are different between the two. That is, by simply varying the calculation period of interpolation, it is possible to obtain a filter effect in which the tones of musical tones having the same sound generation frequency differ. Furthermore, Figures 8 and 13
Comparing the harmonic composition of the sawtooth wave shown in the figure, both of which have a frequency of 442 Hz, it can be seen that even if the sampling frequency _s and the interpolation calculation period are the same, the harmonic composition will change if the α and β values are different. I understand.

In addition, in the above example, the fundamental wave is a rectangular wave, PWM
Although the three types of fundamental waves are waves and sawtooth waves, other fundamental waves such as triangular waves and slope waves can be used. Further, although the interpolation at the point where the amplitude level of the fundamental wave suddenly changes is performed using a sine wave, other function curves such as a quadratic function, a cubic function, an exponential function, a trigonometric function, etc. may be used. Further, in the above embodiment, a 1/4 period sine wave is stored in the ROM 23, but it may be a 1 period or 1/2 period sine wave. Further, in the above embodiment, after setting the initial value β to the full adder, a cumulative subtraction operation was performed in which a constant value α was sequentially subtracted, but after setting the initial value β, a cumulative addition operation was performed in which a constant value α was sequentially added,
The same arithmetic processing for obtaining the fundamental wave as in the above embodiment may be performed, and the arithmetic circuit for determining the scale of the fundamental wave may be modified in various ways. Furthermore, it goes without saying that the present invention can be used not only for music synthesizers but also for other electronic musical instruments, and can be modified and applied in various ways without departing from the spirit of the present invention.

As explained above, the present invention provides a wave generator for an electronic musical instrument that generates various fundamental waves such as rectangular waves through arithmetic processing using a digital circuit.
There is no need to use ROM, and therefore a fundamental wave containing sufficient high-order harmonics can be generated even at low frequencies.Therefore, the hardware configuration does not have to become huge at all, and moreover, it uses time-sharing processing of digital circuits. This has the advantage that a polyphonic electronic musical instrument can be easily realized. In addition, by interpolating waveform generation at points where the amplitude level of the fundamental wave suddenly changes using a function curve such as a quadratic function, and by making the period of interpolation constant regardless of the specified pitch, it is possible to It is now possible to obtain a musical sound signal with a waveform whose spectrum is band-limited at a constant frequency for high frequency sounds, and the aliasing distortion based on the sampling theorem can be reduced to a point where there is no practical problem. It also has the advantage that it can be made to contain abundant high-order overtones.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a music synthesizer according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the wave generator 5, and FIG. 3 is a ROM
Figure 4 is a time chart explaining the rectangular wave generation operation, Figure 5 is a time chart explaining the PWM wave generation operation, and Figure 6 is a time chart explaining the sawtooth wave generation operation. Chaat, 7th
Figures 9 to 9 are diagrams showing the harmonic composition of sawtooth waves of three frequencies, Figures 10 to 12 are diagrams showing the harmonic composition of rectangular waves of three frequencies, and Figures 13 and 14 are interpolation. It is a figure which shows each overtone structure of the sawtooth wave in the same scale frequency when the calculation period of a part is made to differ. 1...Keyboard, 2...Switch part, 3...
CPU, 4...ROM, 5...Wave generator, 6...Digital filter, 7...Envelope generator, 8...Digital/analog converter, 15, 16, 30...Full adder, 17
...Shift register, ₁₈₁₅ to ₁₈₀ ...And gate, ₂₀₈ to ₂₀₀ , 276 to ₂₇₀ ...Exclusive OR gate, _21-7 to 21-1...Inverter, 22-6 to 22-1 ...And Gate, 23
...ROM, 24 ₆ ~ 24 ₀ ...Or Gate, 26,
29,33,35,34 ₇ ~34 ₀ ,46 ₇ ~46 ₀
... Transfer gate, 31 ... Inverter, 32 ... Polarity inversion circuit, 41, 45 ... Subtraction circuit, 42 ... Multiplication circuit, 43 ... Addition and subtraction circuit,
44...Division circuit, _G1 , _G2 ...Gate circuit.

Claims (1)

[Scope of Claims] 1. Storage means for storing frequency information corresponding to a plurality of musical tone frequencies; Reading means for reading out desired frequency information from the storage means in accordance with pitch specification; A calculation means that performs a predetermined calculation based on the output frequency information and outputs a multi-bit signal that changes at a rate according to the specified pitch; A control means for forming a musical tone signal having a waveform; and a control means for forming a musical tone signal having a waveform; and a control means for generating a spectrum by interpolating the waveform for a certain period of time irrespective of the specified pitch at a portion where the amplitude level of the musical tone signal generated from the control means suddenly changes, using a function curve. A wave generator for an electronic musical instrument, comprising: interpolation means for obtaining a musical tone signal having a band-limited waveform; 2. The wave generator for an electronic musical instrument according to claim 1, wherein the interpolation means has a ROM that stores sine waves, and performs the interpolation using sine waves. 3. The wave generator for an electronic musical instrument according to claim 1, wherein the interpolation means includes variable control means for variably controlling the interpolation period based on the function curve.