JPS6326565B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit, particularly a high-speed frequency divider circuit having two frequency division ratios.

Programmable counters that can obtain arbitrary frequency division ratios according to program data have traditionally been used.
It is used in applications that require high-speed operation, such as PLL (phase locked loop) frequency synthesizers. A programmable counter that can operate in the FM band around 100MHz is ECL (Emitter Coupled−
A common method is to use a high-speed logic element such as Logic as a prescaler to lower the frequency and then input it to a programmable counter using an LSI MISFET.

FIG. 1 shows one method of the prescaler method, which is known as the pulse swallow method. If the frequency division ratio P of the prescaler is fixed, if the frequency division ratio of the programmable counter connected in series with it is changed by 1, the overall frequency division ratio will change by P, so it is not possible to obtain a continuous frequency division ratio, but the pulse According to the swallow method, it is possible to obtain continuous frequency division ratios. In Figure 1, prescaler 1 has control input 2.
0 allows the frequency division ratio to be switched between P and P+1, and the output of the swallow counter 3 is fed back to the control input 20 thereof. Such a prescaler having two frequency division ratios is known as a two-modulus prescaler. Now, assuming that programmable counter 2 is programmed with A and swallow counter 3 is programmed with S, prescaler 1 is programmed with P+ while swallow counter 3 is counted S times.
It operates at a frequency division ratio of 1, and thereafter operates at a frequency division ratio of P while the programmable counter 2 is counted (A-S) times. When the programmable counter 2 finishes counting, the swallow counter 3 is preset to S again, and the prescaler 1 is switched to the division ratio of P+1, so that the above-described operation is repeated again. Therefore, the frequency division ratio N when looking at the input clock pulse φ from the output of the programmable counter A is N=(P
+1) S+P(A-S)=PA+S, and by making the program value S of the swallow counter 3 variable from 0 to (A-1), it is possible to obtain continuous values for the frequency division ratio N. The prescaler 1 used in the pulse swallow method not only has two frequency division ratio modes but also has another requirement. That is, the timing of reading the control input requires a special phase relationship with the output of the prescaler itself. This is because, as the prescaler's frequency division ratio, one of P and P+1 is selected depending on the output level of swallow counter 3, but it is necessary to avoid the output of swallow counter 3 from changing when prescaler 1 is in the reading state. . Therefore, if the swallow counter 3 changes with the rise of the output of the prescaler 1, it is optimal for the prescaler 1 to read the bit time just before that and use it as the bit time, and this is another necessary condition for the two-modulus prescaler.

In recent years, MIS FETs have also become faster due to short channeling, and there is a trend to use LSIs for PLLs, including prescalers. The conventional 2-modulus prescaler is the ECL as shown in Figure 2.
There is a flip-flop circuit that uses a flip-flop circuit, but there are the following disadvantages when converting it to MIS LSI. That is, a multi-input gate has a large propagation delay time and is very disadvantageous in terms of maximum operating frequency. Furthermore, a D-type flip-flop requires two clock pulses with opposite phases to each other.
Using this as a shift register is disadvantageous in terms of maximum operating frequency.

The present invention was made to solve the above problems, and an object of the present invention is to provide a high-speed two-modulus prescaler suitable for MIS LSI.

The present invention is characterized in that a switching means which is made conductive and non-conductive by a single clock pulse is connected in series with a power supply to each of N cascade-connected inverters, and the clock pulse is applied to the inverter. Therefore, in a counter that performs N frequency division operation, a transistor circuit that determines each output of a part of two successive inverters to be at an opposite logic level asynchronously with the clock pulse, and one of the two successive inverters and a transistor series circuit, one end of which is connected to the output end of a next-stage inverter that receives the output of the next-stage inverter, and the other end of which is connected to one of the power supplies, and the transistor series circuit connects the two consecutive inverters. The transistor circuit includes a first transistor whose gate receives an input signal applied to the preceding inverter, a second transistor whose gate receives the clock pulse, and a third transistor, and the third transistor is connected to the transistor circuit. This is characterized in that it is made conductive by a signal that activates the signal, thereby enabling N-1 frequency division operation.

The present invention will be explained in detail below.

FIG. 3 shows a first embodiment of the present invention, and FIG. 4 shows a time chart for explaining its operation. In the figure, φ is the input clock pulse 20, the control input is 1
1 to 19 and 21 indicate CMOS (complementary MOS) inverting circuits. Figure 3 shows a two-modulus prescaler of 1/8 and 1/9, and its configuration is two series-connected Pch type MOS FETs and two series-connected channel MOS FETs.
It is based on a complementary type MOSFET consisting of type MOS FETs. And Pch type MOSFET and nch type MOS
A clock pulse is applied to one gate electrode of each of the -FETs, and the output of the previous stage is applied to the other gate electrode of each FET. It is already known that a 1/n frequency dividing circuit can be obtained by cascading n (odd number) stages of inverters as described above.
The first embodiment shown in the figure is based on a 1/9 scale circuit that can be obtained by cascading nine stages of inverters in one cycle. The switching of the frequency division ratio by the control signal causes the inverters 16 and 17 to operate independently of the clock pulse φ, thereby obtaining a frequency division of 1/8.

Figure 4 is a time chart of inverters 11 to 19 during 1/9 frequency division operation and 1/8 frequency division operation, and when control input 20 is in the "H" state, 1/8 frequency division operation is performed. When the signal is in the "L" state, frequency division is performed by 1/9. Now, the states of the inverters 11 to 19 are defined as 1 to 34 as shown in FIG. 4, and will be sequentially explained as time passes. First, in the state 1, the output of the inverter 19 becomes "H" level at the falling edge of the clock pulse φ, and in the state 2, the signal is shifted to the inverter 11, and in the state 3, it is further shifted to 3, and in this way, the input pulse It is sequentially shifted as φ changes. If the control input 20 is at “L” level, the Nch type MOS-FET shown in Figure 3
N ₁ to N ₄ and Pch type MOSFET P ₁ undergo the above-mentioned state shifts sequentially without any meaning, and at state 19, they become the same state as 1 again, which means that 1/9 frequency division has been performed. . If the control input 20 is at “H” level, the Nch type MOSFETs N ₁ to _{N 4} and Pch shown in Figure 3
Since both type MOSFETs _P1 are conductive, when the inverter 15 goes to the "H" level in state 33 of FIG. 4, the inverters 16 and 17 go to the "L" level and "H" level, respectively, asynchronously with the input clock pulse φ.
Change in level. The fact that the inverters 16 and 17 change asynchronously with the input clock pulse φ is equivalent to a state transition for one period of the clock pulse, and a frequency division operation of 1/8 is obtained. However, in state 33 of the time chart in Figure 4, inverter 1
5 is transmitted to the inverter 17, and if the inverter 18 reads the signal from the previous stage, that is, the inverter 17, in state 34, it will be very disadvantageous in terms of the maximum operating frequency. The nch type MOSFETs N ₂ to _{N 4} are necessary to prevent the operating frequency from decreasing for the reasons mentioned above. In state 34, the signal from inverter 15 is shifted to inverter 18, so the states of inverters 16 and 17 do not affect the operation. As described above, 1/8 frequency division can have a maximum operating frequency that is almost the same as 1/9 frequency division.

In order to use the 2-modulus prescaler in the pulse swallow method, as described above, the time to read the control input signal for switching the frequency division ratio must also be taken into consideration. In the time chart of FIG. 4, states 15, 16, 33, and 34 are when the control input 20 becomes active, and the frequency division ratio is selected at 1/8 or 1/9 of one cycle of the output. Therefore, the time allowed for the control input to change is 7/8 or 8/9 of one cycle of the output.
This fully satisfies the requirements for a two-modulus prescaler.

The circuit of the first embodiment is an example in which the frequency division ratio is relatively small, but as the frequency division ratio increases, the number of elements increases, and the load on the clock driver increases, so the drive capacity must be increased, and power consumption increases. will also increase.

The second embodiment shown in FIG.
This circuit system is advantageous in the case of a modulus prescaler, and is effective in solving the problems described above. However, in the example of FIG. 5, the frequency division ratios are set to 1/8 and 1/9, the same as in the first embodiment, for convenience. In operation, when the control input 30 is at "H" level, frequency division is performed by 1/4, and when it is at "L" level, frequency division is performed by 1/5. Inverters 32 and 33 in the figure are equivalent to inverters 16 and 17 in FIG. 3, respectively.
The output of inverter 35 is 1/
After the frequency is divided by 2, the control input 20 is used as another input.
It becomes a control input 30 through an input OR circuit. When the control input 20 is at the "L" level, the control input 30 remains at the "H" state, and a 1/8 frequency divided output is obtained from the T flip-flop. Control input 20 is “H”
When it is at the level, the control input 30 goes to the "L" level every cycle of the 1/4 and 5 frequency divider circuits, and a 1/9 frequency divided output is obtained. At 16 in the time chart of Fig. 6, a 1/8 frequency division output and a 1/9 frequency division output are obtained.

In the two embodiments shown in Figures 3 and 5, the input clock pulse is the gate input of the MOSFET on the power supply side, and the previous stage signal is the gate input of the MOSFET on the output side. There is no problem with replacing it. The ring frequency divider circuit is not limited to one phase, but can also be configured using a two-phase frequency divider circuit.

The output is from inverter 1 in the first embodiment shown in FIG.
In the second embodiment of FIGS. 8 to 5, the inverter 34
The output is very good. In addition, in the two embodiments shown in Figures 3 and 5, Pch type MOSFET and nch type MOSFET
It is also possible to completely replace the MOSFETs.

As described in detail above, according to the present invention, it is possible to construct a two-modulus counter with a high maximum operating frequency using a small number of elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional pulse swallow type programmable counter, FIG. 2 is a diagram showing a circuit of a conventional 2-modulus counter, and FIG. 3 is a first embodiment of a 2-modulus counter of the present invention. FIG. 4 is a time chart for explaining its operation, FIG. 5 is a diagram for explaining the second embodiment of the 2-modulus counter of the present invention, and FIG. 6 is for explaining its operation. This is a time chart. In the figure, φ is the input clock pulse, 20 is the control input, 11 to 19, 3
1 to 35 are CMOS inverters.

Claims (1)

[Claims] 1. By connecting in series with a power supply switching means that are made conductive and non-conductive by a single clock pulse for each of the N cascaded inverters, and applying said clock pulse to the N inverters. A counter that performs a frequency division operation includes a transistor circuit that sets each output of a part of two consecutive inverters to a logic level opposite to each other asynchronously with the clock pulse, and a transistor circuit that sets the outputs of two consecutive inverters to mutually opposite logic levels, and and a transistor series circuit having one end connected to the output end of the next stage inverter which receives the output of a first transistor whose gate receives an input signal applied to the inverter; a second transistor whose gate receives the clock pulse; and a third transistor, the third transistor activating the transistor circuit. A counter characterized in that it is made conductive by a signal that allows N-1 frequency division operation.