JPS6326584B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an independent synchronization transmission system in facsimile, and more particularly to a method of synchronizing the transmitting side and receiving side in a G machine specified by CCITT.

According to the CCITT G standard, the scanning frequency of facsimile messages is f ₀ = 6 Hz (tolerance ± 5
×10 ^-6 ), therefore, the scanning period is T ₀ = 1/6 (s) ≒
It is specified as 166.667 (ms), and it is necessary to maintain this time T ₀ and perform message processing for each line during transmission or reception. Therefore, in the past, a synchronizing signal with a period T ₀ was generated, and based on this signal, message processing was performed for each line during transmission or reception. However, according to this method, during transmission, there is a synchronization signal generation circuit configured using a counter etc. to generate a synchronization signal with a period T ₀ , and a large number of gate circuits for data processing based on the generated synchronization signal. In addition, at the time of reception, in addition to these circuit configurations, a circuit that performs synchronization (phase) matching and synchronization maintenance between the synchronization signal generated at period T ₀ and the synchronization signal on the transmitting side, etc., is required. The system becomes complicated, the number of parts increases, the cost goes up, and there are disadvantages in that phase matching errors are more likely to occur due to noise and the like.

The present invention is based on the periodicity at the time of transmission or reception.
By time-managing the message processing for each T ₀ using software, there is no need for any hardware configuration such as a synchronization signal generation circuit, and by using the only microcontroller provided for message processing, it is extremely efficient. It is an object of the present invention to provide an independent synchronous transmission system for G machines that can economically establish a synchronous relationship between the transmitting side and the receiving side.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the entire facsimile apparatus according to an embodiment of the present invention, and 1 is
A reading section reads and scans a document using a CCD sensor, and binarizes and outputs the resulting video signal for each line; 2 is an S/P conversion circuit that converts the binarized serial data into parallel data in 8-bit units;
3 is a CPU, 4 is a ROM that stores processing programs, 5 is a RAM that stores various data, and 6
The P/S transfers image data to the CPU 3 in 8-bit parallel, while the P/S transfers image data serially to the modem 7.
-S/P conversion circuit, 8 is NCU (network control circuit), 9
1 is a P/S conversion circuit that converts 8-bit parallel data into serial data, 10 is a recording unit that records the serial data line by line, and 11 is a keypad.
The output port 12 outputs the AGC control signal to the modem 7, and is a clock generation circuit (OSC).

With the above configuration, let us take as an example the case where the line scanning line length is 216 mm, reading scanning is performed at a main scanning linear density of 8/mm during transmission, and recording scanning is performed at a main scanning linear density of 6/mm during reception. explain.

As is well known, according to the CCITT G standard, transmission procedures in phases C and D are defined as shown in FIG. That is, before sending a message, the sending side sends out a phase signal, that is, a synchronization signal with a period T ₀ , while the receiving side must detect this synchronization signal, perform phase alignment, or synchronization matching, and maintain it. . Moreover, as shown in FIG. 3, this synchronization signal _{has a period t 0 (} =
It is stipulated that T ₀ ×0.04 to _{T 0} ×0.06) is used as a black level signal, and the remaining time τ ₀ is sent out as a white level signal. During the message sending period, this
A white level signal is input during the t ₀ period, and image data is input during the remaining τ ₀ period.

On the other hand, in the case of this embodiment, the number of pixels in one line is 8 at the time of transmission based on the above line scanning line length and main scanning line density.
×216 = 1728 bits, 6 × 216 = 1296 bits when receiving.

Also, the processing cycle for one line is T ₀ = 1/6 (s)
Since the modem clock is
TMDMCK=1/(1/6)/(1728/1)=1728×6=
10.368 (kHz), similarly when receiving RMDMCK =
1296×6=7.776 (kHz).

Furthermore, in the case of this embodiment, since the CPU 3 processes image data in units of 8 bits, 1 line of image data of 1728 bits at the time of transmission becomes 216 bytes, and 1 line of image data of 1296 bits at the time of reception. A bit is 162 bytes. Therefore, during transmission, data read by reading unit 1 is used as a line buffer (LBF) area to pass to modem 7, and is expressed in hexadecimal.
The memory areas of RAM 5 at addresses 7028 to 70FF and addresses 7128 to 71FF are used. On the other hand, during reception, addresses 705E to 70FF of RAM 5 and addresses 715E to 715E are used as the LBF area between modem 7 and recording unit 10.
Use 71FF address.

From the above, when transmitting a synchronization signal to the receiving side, first, as shown in Figure 4,
Black level data is preset in 10 bytes of addresses 7028 to 7031 of No.5, and white level data is set in the remaining addresses 7032 to 70FF. Next, when the transmission of the synchronization signal is started, the modem 7 uses the 10.368kHz clock TMDMCR from the clock generation circuit 12 to start the P/S-
Data is taken in one bit at a time from the S/P conversion circuit 6. As a result, the P/S-S/P conversion circuit 6 outputs an interrupt signal INT to the CPU 3 when 8 bits of data is output to the modem 7. CPU
3 receives this interrupt signal INT, and performs a process of outputting one byte of transmission data from the RAM 5 to the P/S-S/P conversion circuit 6, giving top priority to other processes. In this process, the CPU 3 first outputs 1 byte of 7028 address data from the RAM 5 to the P/S-S/P conversion circuit 6. Next, the P/S-S/P conversion circuit 6
When it receives an interrupt signal INT from , it outputs 1 byte of 7029 address data to the P/S-S/P conversion circuit 6.

In this way, the modem 7 is constantly connected to the P/S-S/P
While the data to be sent from the conversion circuit 6 to the receiving side is taken in one bit at a time, the CPU 3 converts the P/S-S/
RAM5 in response to the interrupt signal INT from the P conversion circuit 6.
The data is output to the P/S-S/P conversion circuit 6 one byte at a time. Eventually, when all the data at the addresses in the RAM 5 have been output to the P/S-S/P conversion circuit 6, the process returns to 7028 and repeats the output process. As a result, a synchronization signal as shown in FIG. 4 and corresponding to FIG. 3 is sent to the receiving side from the transmitting side.
Furthermore, the synchronization signal generation state at this time is fixed thereafter on the transmitting side. That is, facsimile data is transmitted while maintaining this phase relationship.

On the other hand, on the receiving side that receives this synchronization signal,
The synchronization signal input via NCU8 is sent to modem 7.
is the 7.776kHz clock from clock generation circuit 12
It outputs one bit at a time to the P/S-S/P conversion circuit 6 using RMDMCK. When this data becomes 1 byte, the P/S-S/P conversion circuit 6 issues an interrupt signal INT.
Output to CPU3. CPU3 uses this interrupt signal
Interrupt other processing with INT and P/S-S/P
A synchronizing signal is detected by taking in one byte data from the conversion circuit 6 and checking its level. Furthermore, by capturing the change point from the black level to the white level, the receiving side 7063 address corresponding to the sending side 7032 address is captured, and from then on, the interrupt signal is
This address is updated one by one for each INT input. This performs phase matching with the synchronization signal, and thereafter synchronization is maintained by maintaining this phase relationship and circulating and updating addresses.

After that, when the message transmission starts, the CPU 3 on the sending side converts the binary data obtained from the reading section 1 into 8-bit data using the S/P conversion circuit 2, takes it in, and sequentially reads it one byte at a time from address 7028 in the RAM 5. When you store image data and store one line of data up to 70FF, the next one line will be
Store from address 7128 to 71FF. meanwhile,
Every time an interrupt signal INT is received from the P/S-S/P conversion circuit 6, the CPU 3 interrupts these processes and downloads 1 byte from address 7028 in the LBF (line buffer) area where 1 line of data has already been stored. Each signal is output to the P/S-S/P conversion circuit 6. At this time, as described above, the CPU 3 forcibly replaces the first 10 bytes of the line with white level data and outputs it to the P/S-S/P conversion circuit 6. 70FF
Once the data for one line has been sent, the next step is
The process of sending data from the 7128 is repeated alternately, and one page of facsimile data is sent. Also, the phase at this time is that the address update is
The interrupt signal INT is based on the 10.368 kHz clock TMDMCK, and as a result of regularly cycling through 216 bytes, it is held constant after the synchronization signal is sent.

On the other hand, the receiver receiving this message,
CPU3 constantly clocks 7.776kHz RMDMCK
Synchronization with the sending side is maintained by regularly and cyclically updating the 162-byte address using the interrupt signal INT based on . Therefore,
The image data sent from the transmitting side via the NCU 8 is taken in one bit at a time from the modem 7 to the P/S-S/P conversion circuit 6 using the clock RMDMCK.
Regularly byte by byte by interrupt signal INT
It is stored in the address that is being held in rotation at that time in RAM5. In addition, in the meantime, CPU 3 uses the two LBF areas 705E to 705E where the received data is stored.
Data is taken out one byte at a time alternately from 70FF and 715E to 71FF and output to the P/S conversion circuit 9. This image data is converted to serial data and stored in the recording section 1.
0 and is recorded at a main scanning line density of 6/mm.

In this way, according to this embodiment, it is possible to perform synchronization matching and maintenance between the transmitting side and the receiving side using software without providing a synchronizing signal generation circuit unlike the conventional device, and using only a microcontroller. This allows the G-machine to be configured extremely compactly and economically.

Figures 5 to 8 are flowcharts showing the above operations in more detail.
The figure shows an operational flow on the transmitting side, and FIGS. 7 and 8 show operational flows on the receiving side.

In the main flow shown in Figure 5, the phase signal transmission time on the transmitting side ((s) ±0.5 in CCITT) is monitored, and when this time expires, a signal transmission stop command is issued to the modem 7. .

On the other hand, the receiving side performs synchronization matching using this phase signal, and if synchronization is achieved, the CFR is returned to the transmitting side.

On the transmitting side, since it is necessary to maintain synchronization even after sending out the phase signal, the interrupt signal INT is enabled and the interrupt flow shown in FIG. 6 is always executed.
As soon as the CFR from the receiving side is detected, the sending side sends the image data, so the image data read by the reading unit 1 is transferred to the S/P conversion circuit 2 in the LBF area of the RAM 5.
Save through.

The main flow in Figure 5 is that facsimile data is
It monitors that the data has been stored in the LBF area, and when it becomes possible to send the data, it sets a message flag and proceeds to the data sending flow to the modem 7 in FIG.

That is, in the flow shown in FIG. 6, when the lower address register becomes 0, transmission of one line of data in the LBF ₁ or LBF ₂ area is completed, so the LBF
Counter for full control of area
Subtract 1 from FULCNT and use the other one in the next interrupt.
To send the data in the LBF area, the upper address registers 70←→71 are switched.

Since the full counter FULCNT is used for the LBF ₁ and LBF ₂ areas in this embodiment, buffer full is controlled by incrementing and decrementing the counter.
That is, if the full counter FULCNT is smaller than 2, data is input to the LBF area via the S/P conversion circuit 2, and the full counter FULCNT is incremented. If FULCNT=2, this process will not be executed. On the other hand, when transmission of one line of LBF area data is completed, FULCNT is decremented and facsimile data input processing is executed again. At this time, a job of moving the document in the sub-scanning direction is also executed. In this case, the speed at which the reading unit 1 reads data is naturally faster than the speed at which the modem 7 sends data. That is, FULCNT
+1 speed is set faster than FULCNT-1 speed.

In the flow of storing facsimile data in the LBF area of RAM5, the beginning of the line in Figure 4
Since the 10-byte synchronization period is a white level, the read data is replaced with white data and sent to addresses 7028 to 7031 in the LBF ₁ area and 7128 to 7128 in the LBF ₂ area.
Store in 7131 address.

Furthermore, the job of storing this facsimile data in the LBF area is executed using an interrupt flow that has a lower priority than the interrupt signal INT.

Next, during reception, the phase signal sent from the transmitting side is demodulated by the modem 7 and taken into the CPU 3 from the P/S-S/P conversion circuit 6. This is the seventh
In the main flow shown in the figure, it is checked whether the phase signal is normal. That is, in the main flow of Figure 7
When the CPU 3 extracts one byte of data from the P/S-S/P conversion circuit 6, the next time the P/S-S/P conversion circuit 6 becomes FULL is at the time of 8/RMDMCK, as shown in Figure 3. It can be used to check the time of t ₀ , τ ₀ , and T ₀ period of the demodulated output. The changing point of the rising or falling edge of this demodulated output is searched, and the LBF area address determined from the effective recording area of the receiving side recording device is set at that point in the working (WK) area. Then, when the interrupt signal INT is enabled, the demodulated data is taken into the LBF ₁ area in the reception interrupt flow shown in FIG. At this time, in the first interrupt, demodulated data is set to the LBF ₁ address previously set in the WK area. Thereafter, the LBF ₁ address is incremented every time the interrupt signal INT occurs.

As mentioned above, the LBF area on the receiving side is set to 162 bytes due to the linear density determined by the recording device.
That is, the interrupt signal INT occurs 162 times, and LBF ₁ occurs 162 times.
It returns when the address is incremented. Here, to update to the start address of LBF ₁ ,
The same operation is performed when sending. That is, during phase signal transmission, only _one LBF area is used in this embodiment.
When the LBF ₁ address changes from 70FF to 7100 by incrementing the addresses 705E to 70FF of LBF ₁ every time the interrupt signal INT is generated, that is, when the lower part of the LBF ₁ address becomes 00,
Updated to 705E address. in this way,
Synchronization can be maintained by controlling the LBF address in a loop.

After the phase signal demodulation data is stored in LBF ₁ , in the main flow of Figure 7, a synchronization check is performed by checking whether the phase signal demodulation data is stored at a predetermined address in LBF ₁ . Let's do it. If the synchronous matching fails, the interrupt signal INT is disabled and the synchronous matching is restarted from the beginning.

If synchronization is successful, it waits for the end of the phase signal and returns CFR indicating successful synchronization to the transmitting side.

Then, when the message carrier is detected,
The message flag is set and the interrupt flow shown in FIG. 8 is advanced to the message-in-progress flow. In this flow, one line of data is sent in the opposite direction to the interrupt flow during transmission.
When it is imported into the LBF area, FULCNT is incremented.

In this message flow, LBF ₁ area and
Use the LBL ₂ areas alternately. Each buffer also consists of 162 bytes,
The LBF address is incremented every time the interrupt signal INT occurs, and for example, the LBF ₁ address starts from 70FF.
When it reached 7100, LBF ₁ became FULL, so
Increment FULCNT. And then the next
Change address to LBF ₂ area. That is, it is set in the WK area so that it becomes the start address 751E of the LBF ₂ area when the next interrupt signal INT occurs.
When the LBF ₂ area also becomes FULL, increment FULCNT and set the start address of LBF ₁ . By controlling the addresses of the LBF ₁ area and LBF ₂ area in a loop in this way, synchronization can be maintained.

In addition, in the message flow, the AGC circuit is
In order to perform keyed AGC operation to operate AGC using the carrier wave during time _t0 in the figure, the keyed AGC control terminal is turned on and off at a predetermined LBF address.

Furthermore, in the reception interrupt flow, output port 11 is turned ON and OFF at a predetermined address in the LBF area.
This allows the synchronization signal to be monitored using an oscilloscope, etc.

Although the above embodiment has been explained using LBF address control, it can be similarly implemented by providing a synchronous counter area in the RAM area and controlling the value of this counter in a loop.

As described above, according to the present invention, the LBF function is
The bit resolution clock generates an interrupt for each predetermined bit.
By controlling the LBF address on the RAM in a loop, the synchronization signal can be generated and held with a minimum number of circuit components. In addition, since the demodulated data is checked for each byte during reception, even if the demodulated signal is disturbed by noise on the line, the point of synchronization matching can be detected accurately, so synchronization matching can be performed reliably. It becomes like this.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a facsimile device according to an embodiment of the present invention, and Fig. 2 is a block diagram of a facsimile device according to an embodiment of the present invention.
Figure 3 is a phase signal waveform diagram according to the CCITT G standard. Figure 4 is an explanatory diagram of LBF address data for generating the phase signal in Figure 3. Figures 5 to 8 The figure shows the operation flow of Figure 1. Figures 5a and b are the main flowcharts when transmitting, Figures 6a and b are the interrupt flowcharts when transmitting, and Figures 7a and b are the main flowcharts when receiving. Flowchart FIG. 8 is an interrupt flowchart at the time of reception. 1... Reading section, 2... S/P conversion circuit, 3...
CPU, 4...ROM, 5...RAM, 6...P/
S-S/P conversion circuit, 7...Modem, 8...
NCU, 9...P/S conversion circuit, 10...recording section,
11...Output port, 12...Clock generation circuit.

Claims (1)

[Claims] 1. In an independent synchronous transmission system for facsimile in which a line buffer memory is provided in the memory of a microcomputer to sequentially store image data for each line, and image data is sent and received from a modem,
When transmitting a message, a synchronization signal is put into the line buffer area before sending the message, and the read address is circulated to send out the synchronization signal at a constant cycle, while when receiving the message, the synchronization signal is received and written into the line buffer area. An independent synchronous transmission method characterized by detecting a target address and cyclically holding a write address from that address to thereafter maintain a synchronized state with the transmitting side.