JPS6326875B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device that displays radar output as an image. In particular, the present invention relates to a random access radar display device that mixes and displays digital lights including radar video and lines in a radar control automation system in a PPI (Plan Position Indicator) timeshare.

The timeshare display method of radar video display using PPI sweep and digital line display including line segments uses the X-deflection signal as shown in Figure 1.
X _A and Y - generate deflection signals X _B , and these two
This method displays radar information on a CRT using a signal deflection circuit shown in FIG. In FIG. 1, I and I indicate the PPI sweep signal waveform, and symbol I indicates the digital line display signal waveform, respectively. In Figure 2, 1 is an X-deflection amplifier, 2 is a Y-deflection amplifier, 3 is an X-deflection yoke, 4 is a Y-deflection yoke,
5 each indicates a CRT.

As a time shear display method for generating this PPI sweep and digital line generation, the third
The circuit configuration shown in the figure is conventionally known. That is, in Fig. 3, 10 is a line generation circuit, and 11 is a PPI.
Sweep generation circuit, 12 is a deflection system control circuit, 13
1 is a mode select circuit, 14 is a digital-to-analog converter (hereinafter referred to as "DA converter"), 15 is a smoothing circuit, 16 is a yoke deflection amplifier, 1
7 each indicate a deflection yoke.

4 and 5 are operation time charts showing the input or output waveforms at the points indicated by the x marks in FIG. 3. That is, FIG. 4 shows various timing signals for PPI sweep and digital line display. Further, in FIG. 4, A indicates a radar trigger signal, and B indicates an ONM range signal. FIG. 5 shows the input and output waveforms of the smoothing circuit 15, and in particular, I in FIG. 5 shows a time chart in the case of PPI sweep data, and FIG. 5 shows a time chart in the case of digital line data, respectively.

The PPI sweep data processing operation and the digital line display deflection data processing operation will be explained with reference to FIG. Digital line display deflection data is
The data is input to the line generation circuit 10 as two components, X _D1 as the X component and Y _D1 as the Y component, and output as X _D2 and Y _D2 converted into constant brightness line generation data.
X _D2 and Y _D2 pass through the mode select circuit 13,
=X _D2 , Y=Y _D2 is inputted to the DA converter 14 as digital display deflection data, and outputted as digital-to-analog converted x and y signals.

The PPI sweep offset data X ₀ and Y ₀ are input to the PPI sweep generation circuit 11 and output as the X _S and Y _S signals. The X _S and Y _S signals are given as the following equations (1) and (2).

X _S = R・cosθ+X ₀ ...(1) Y _S =R・sinθ+Y ₀ ...(2) However, θ is the angle in the polar coordinate system and 0°≦θ<
The range is 360°, and R means the radius in polar coordinates.

The PPI sweep signal corresponding to each range is RATEΔR, cosθ and
By multiplying RATEΔR by sinθ and accumulating this product signal, R·cosθ and R·sinθ can be generated. This process can be expressed as equations (3) and (4).

R・cosθ＝〓RATEΔR・cosθ……(3) R・sinθ＝〓RATEΔR・sinθ……(4) This RATEΔR・cosθ and RATEΔR・sinθ
The calculation is performed by a rate multiplier built into the PPI sweep generation circuit 11. The rate multiplier output signal is accumulated by the up-down counter of the sweep generating circuit 11 and
Output as cosθ signal and R・sinθ signal. X
The offset amounts X ₀ and Y ₀ of the Y component and Y component are initially loaded into the up-down counter of the PPI sweep generation circuit 11 immediately before the PPI sweep corresponding to each angle starts sweeping. Through such a processing process, X _S and Y _S can be generated. This _XS ,
The Y _S signal is input to the mode select circuit 13,
Output as X and Y signals where X=X _S and Y=Y _S ,
Further, the X and Y signals are converted into analog signals x and y, respectively, by a DA converter 14.

The timeshare mode for PPI sweep and digital line display is executed at the mode timing shown in FIG. 4, and this mode switching is performed by the mode select circuit 13 shown in FIG. That is, when processing digital line display deflection data, the deflection system control circuit 12 to the line generation circuit 10
An ENABLE signal b is applied to the line generating circuit 10, and the line generating circuit 10 returns a BUSY signal a to the deflection system control circuit 12 during digital line display deflection data processing. Further, the digital line display deflection data is input to the DA converter 14 through the mode select circuit 13 during the space period of the control signal d. At this time, a clock signal e with a period _T2 is applied from the line generation circuit 10 to the DA converter 14, and analog conversion processing is performed. This analog signal output x,
The signal y is applied to a smoothing circuit 15, where the waveform is shaped as shown in FIG. 5, and output signals x ₁ and y ₁ are sent out.

In addition, the processing of PPI sweep data is performed using the control signal d.
is performed during marking, and at this time, DA converter 1
4 is supplied with a clock signal f having a period T ₁ from the deflection system control circuit 12. These analog signal outputs x, y are applied to a smoothing circuit 15, where the waveforms are shaped as shown in FIG. 5I, and output signals x ₁ , y ₁ are sent out. The x ₁ , y ₁ signals are connected to the yoke deflection amplifier 16
, the voltage change signals x ₁ , y ₁ are converted into current change signals x ₂ , y ₂
The signal is converted and amplified and supplied to the deflection yoke 17. The above is the operation of the conventional method, but this method has the following drawbacks.

(1) In this method, as a result, the same line is
To display above, line generator circuit and PPI
A separate sweep generation circuit is required.

(2) From the standpoint of electrical performance, the rate multiplier method of the PPI sweep generation circuit uses thinning of the reference clock to perform multiplication, which essentially impairs the smoothness of the generated line.

The present invention improves this point by omitting the PPI sweep generation circuit and by commonly using the line generation circuit for digital line display in the timeshare, simplifying and downsizing the hardware. We developed a device that can improve image quality by preventing the lack of smoothness in PPI sweeps caused by multiplication errors in the rate multiplier method, which is a problem with conventional PPI sweep generation methods. The purpose is to provide.

By changing the basic clock of the line generation circuit for digital line display, the present invention not only generates lines for digital line display, but also uses the same circuit to generate constant brightness and accurate PPI sweeps in synchronization with radar triggers in timeshare. It is characterized by achieving the following.

Here, the line generation circuit has a function of displaying a vector as a constant brightness line to the radar signal indicator. To explain how to generate a constant brightness line, the following steps are taken.

(1) Receive vector start and end position data.

(2) Calculate the line segment length l of the vector. This l is divided by a constant K to calculate the number of strokes N. For each of the X and Y components of the vector,

Claims (1)

[Claims] 1 In a radar display circuit configured to include means for generating a PPI sweep display signal and means for generating a digital line display signal, and for performing PPI timeshare display of radar video and digital lines, digital line display deflection data is temporarily held. a first means for temporarily holding PPI sweep deflection data; a line generating means for generating a constant brightness line using a reference clock; and a line generating means for generating a line with read data from the first and second means. 1. A radar display circuit comprising means for inputting a time-shared reference clock into the means and controlling the period of the reference clock at this time to be different between PPI deflection data and digital line display deflection data.