JPS6326899B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital multiplier that plays an important role in realizing a digital signal processing circuit in hardware.

Conventional configurations and their problems Many systems have been proposed for digital multipliers that multiply digital data, and these can be roughly divided into parallel multipliers, serial multipliers, and ROM (read-only) multipliers. Only
Memory) multipliers are known.

Each multiplier has its own characteristics in terms of hardware amount, arithmetic code format, arithmetic speed, arithmetic accuracy, etc., and each has advantages and disadvantages. Parallel multipliers are superior in calculation accuracy and speed, but require a large amount of hardware. Although serial multipliers require less hardware, they are limited in terms of calculation format and speed. ROM multipliers are relatively superior in terms of calculation speed, but if high precision is required, the ROM capacity, ie, the amount of hardware, increases. In addition, in a digital multiplier, for inputs A, B, and output C, A×B
The calculation =C is performed, but the input/output data formats also vary. In other words, a ROM multiplier can be configured arbitrarily, but a parallel multiplier has input A,
Both inputs A and C are parallel, and in a serial multiplier, one of the inputs A and B is parallel, the other is serial, and the output is serial. Therefore, when configuring a circuit including multipliers, various multipliers must be selected depending on the specifications. Therefore, if the entire circuit system is processed in parallel, the multiplier used will be a parallel type, but the parallel type requires more hardware, is more expensive, and is not suitable for applications that do not require high speed. There was a problem that it was not suitable.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a digital multiplier that has an operation speed equivalent to that of a serial multiplier and can be configured with a smaller amount of hardware than a parallel multiplier.

Structure of the Invention The digital multiplier of the present invention includes sign inversion and bit shift circuit means for inverting the sign and multiplying a parallel multiplicand A in two's complement representation as one input by a power of two; -b _O・2 ⁰ + _o-1 〓 ^j-1 b _j・2 ^-j ( b, n, j are integers), if the value of b _j is 1, it is passed, and if the value of b _j is O, it is controlled to stop b Only when the value of _j is 1, b _j・1/2 _j・
A switching circuit means for performing the calculation A, an accumulator circuit means consisting of a full adder and a D-type flip-flop that sequentially accumulates the output of the switching circuit means, and a D-type flip-flop circuit for extracting the final multiplication result, Two inputs A and B are multiplied by A and B in synchronization with the control clock, and the parallel digital multiplication result b _O (-A) + _o-1 〓 ^j=1 b _j (2 ^-j A) is output. It is configured as follows. According to this configuration, it is possible to have the characteristics of a parallel multiplier and a serial multiplier, and the calculation speed is equivalent to that of a serial multiplier, and the hardware amount has the advantage of being smaller than that of a parallel multiplier. It is especially suitable for parallel processing where high speed is not required.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 shows an embodiment of the digital multiplier of the present invention. In FIG. 1, 1 is the multiplier body, 2,
3 is an input terminal for parallel inputs A and B, and these parallel inputs A and B have code lengths of m and n bits, respectively.
4 is the output end of the parallel output C, and the code length of the output C is (m+n-1) bits. Here, the construction method of the multiplier main body 1 differs slightly depending on the input/output code format, but as an example, consider a two's complement format,
The amplitude is normalized to 1×1≦1. At this time, input/output A, B, and C are expressed as follows.

A=-a ₀・2 ⁰ + _n-1 〓 ⁱ⁼¹ a _i 2 ^-i (1) B=-b ₀・2 ⁰ + _o-1 〓 ^j=1 b _j 2 ^-j (2) C= −c ₀・2 ⁰ + _n+o-1 〓 ^k=1 c _k 2 ^-k (3) Therefore, the output C is as follows.

C=A×B =A×(-b ₀・2 ⁰ + _o-1 〓 ^j=1 b _j・2 ^-j ) =b ₀ {(−2 ⁰ )・A}+ _o-1 〓 ^j=1 b _j {2 ^-j・A} b ₀・(−A)+b ₁ (1/2・A)+b ₂ (1/2 ²・A
)+......+b _o-1 (1/2 ^n-1・A) (4) In binary numbers, each component a _i , b _j , c _k is 0 or 1, and multiplication by a power of 2 is This can be easily done by bit shifting. Therefore, as is clear from equation (4), multiplication can be performed by multiplying the multiplier A by powers of -1 and 2, and adding only the terms in which the component b _j of the multiplicand B is 1. FIG. 2 shows the specific structure of the multiplier main body 1, and FIG. 3 shows its operation timing chart. In FIG. 2, parallel data A as a multiplier enters from input terminal 5 at the operation timing shown in FIG. 3a, and parallel data B as a multiplicand enters from input terminal 8 in the same manner. However, FIG. 3a shows only one fixed bit of the parallel input data A. The input A is subjected to predetermined operations by the sign inversion and bit shift circuit means 6, and then time-division multiplexed by the multiplex circuit means 7 into the data format shown in FIG. 3b. At this time, the data becomes (m+n-1) bits.

On the other hand, the multiplicand B input from the input terminal 8 is converted by the parallel-to-serial conversion circuit means 9 into the data format shown in FIG. 3c, which is synchronized with the time division multiplexed data. 1
0 is a switching circuit means that allows the output signal of the multiplexing means 7 to pass only when component b _j of the output of the parallel-to-serial conversion circuit 9 synchronized therewith is 1;
Consists of an AND circuit. That is, the third
In the figure, b _j of the output c of the parallel-serial conversion circuit 9
If the value of is 1, the signal of time division multiplexed data b synchronized with it is passed, and if it is 0, it is stopped and a zero signal is sent, and the calculation (b _j 1/2 ^j A) is performed. 11 is a full adder, and 12 is a D-type flip-flop as a unit delay device.These full adder 11 and D-type flip-flop 12 constitute an accumulator circuit means, which sequentially accumulates the multiplexed data output from the switching circuit means 10. I'm going to go. That is,
Perform the calculation b ₀ (-A) + _o-1 〓 ^j=1 b _j (2 ^-j A). The operating clock of the D-type flip-flop 12 is shown in FIG. 3d. Further, when one multiplication is completed and the next multiplication is to be performed, the data accumulated in the accumulator circuit means must be erased, and the reset signal to the D-type flip-flop for this purpose is shown in FIG. 3e.
13 is a D-type flip-flop for extracting the final multiplication result, and its operating clock is shown in FIG.
Shown below. And 14 is an output end.

In addition, in the sign inversion circuit means 6, when performing multiplication by (-1) in two's complement format, all data is inverted, but since this results in a result that is 1LSB less than the true value, this correction is necessary. Only when _b0 is 1, the carry input Z from the lower order of the full adder 11 is used in the first step of the accumulation.

Furthermore, if the multiplicand input B comes at the timing of the serial digital data shown in FIG. .

In addition, when m=n, that is, when the word lengths of both input data are equal, the configuration is uniquely determined, but m≠n
In this case, there are two possible configurations. In this case, it is advantageous in terms of calculation speed to set the longer word length as input A.

Effects of the Invention As described above in detail, according to the present invention, the sign inversion and bit shift circuit means for inverting the positive/negative and multiplying the positive/negative of the parallel multiplicand A in two's complement representation as one input by a power of two. The _outputs are time-division multiplexed by _multiplexing circuit _means , and the output ^of this multiplexing circuit means is used as ^the other ^input . If the value of b _j is 1, it is passed, and if the value of b _j is 0, it is stopped and the value of b _j is Only in case of 1 b _j・1/2 _j・
A is calculated, and the results of this calculation are sequentially accumulated by the accumulator circuit means, so that the parallel digital multiplication result b _O (-A) + _o-1 〓 ^j=1 b _j (2 ^-j A) is output. Because of this configuration, it can be configured with a relatively small amount of hardware, and has the advantage of having an operation speed equivalent to that of a serial multiplier. Additionally, the circuit configuration is simple, so it has the advantage of being easy to integrate into an IC.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the digital multiplier of the present invention, FIG. 2 is a specific circuit configuration diagram of the multiplier, and FIG. 3 is an operation timing chart thereof. 6...Sign inversion and bit shift circuit, 7...Multiplex circuit, 9...Parallel-serial conversion circuit,
10...Switching circuit, 11...Full adder, 12,1
3...D type flip-flop.

Claims (1)

[Scope of Claims] 1. Sign inversion and bit shift circuit means for inverting the positive/negative and multiplying by a power of 2 a parallel multiplicand A in two's complement representation as one input;
A multiplex circuit means for time-division multiplexing the output of this sign inversion and bit shift circuit means, and -b _O・2 ⁰ + _o-1 〓 ^j=1 b _j・2 ^-j (b, n, j are integers) of the serial multiplier B in two's complement representation, if the value of b _j is 1, it is passed, and if the value of b _j is O, it is stopped. Control is performed and only when the value of b _j is 1, b _j・1/2 _j・
A switching circuit means for performing the calculation A, an accumulator circuit means consisting of a full adder and a D-type flip-flop that sequentially accumulates the output of the switching circuit means, and a D-type flip-flop circuit for extracting the final multiplication result, Two inputs A and B are multiplied by A and B in synchronization with the control clock, and the parallel digital multiplication result b _O (-A) + _o-1 〓 ^j=1 b _j (2 ^-j A) is output. A digital multiplier characterized in that it is configured as follows.