JPS6326904B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for monitoring and controlling FIFO memory operations.

FIFO memory is an abbreviation for First In First Out memory, and is a digital memory characterized by the ability to write and read data asynchronously. Although this memory is already known, its outline will first be described in order to clarify the content of the present invention.

Figure 1 shows FIFO memory (hereinafter abbreviated as "FIFO")
The basic configuration is shown below. 11 is a data input terminal, 12
13 is a data output terminal, 13 is a write clock input terminal, 14 is a read clock input terminal, 15 is a reset terminal, 16 is a memory cell, and 17 is a read/write control section.

Figure 2 shows the FIFO operation time chart.
21 is a reset signal, 22 is an input data signal, 2
3 represents a write clock, 24 represents output data, and 25 represents a read clock. The operation of FIFO will be described below.

The FIFO is first reset by the reset signal 21, and then one bit of input data is sent to the input terminal 1 by the write clock 23 which is synchronized with the input data 22.
Write from 1. In this case, inside the FIFO, data 22 (#1) written first is in the first cell 16.
(#1), it is immediately transferred to the second, third, ... nth cell without any special external control, and finally the first data is stored in the nth cell, that is, the final cell 16.
(#n) is accumulated. Here, n is an integer.

It should be noted that as a result of data accumulation, the input data numbers (#1, #2, ...) and the memory cell 16 numbers (#1, #2, ..., #n) will be in the opposite order. .

Similarly, the second data 22 (#2) is the (n-th)
1) The mth data (m
n) are accumulated in the input side cells in order from the output side cells. Here, m is an integer.

Next, we will discuss reading. The data accumulated as described above is read out from the nth cell 16 in the order of data #1, #2, . . . by the read clock 25. At this time, the operation of the memory cell 16 is such that when data #1 is read from the n-th cell 16, data #2 stored in the (n-1)th cell is automatically transferred to the n-th cell. Moving. Similarly, data after data #3 is also set to 1 on the output side.
The cell is moved and waits in that state until the next read clock 25 arrives. This read clock 25 can be operated asynchronously with the write clock 23, which is a major feature of the FIFO.

As is clear from the above explanation, FIFO can store input data in a predetermined order without changing the order unless overflow or underflow occurs, and can output data in the input order at any time.

However, if a pulse is added to the write clock 23 or read clock 25, which corresponds one-to-one with the data, due to noise or other reasons, or if a part of the normal clock disappears, a difficult difference will occur between the write data string and the read data string. I will do it. For example, the third
As shown in the figure, when a noise pulse N occurs in addition to the write clock 23 (#2) corresponding to the second input data 22 (#2), the FIFO also considers this noise pulse to be a write clock and sets the clock at that time position. The existing second input data 22 (#2) is written, and as a result, the second input data 2 is written to the FIFO twice.
2 (#2) has been written.

When this input data is read by the normal read clock 25, the third input data 22 (#3) is read out by the clock 25 (#3) that should read the second input data 22 (#3).
(#2) is read out, and subsequent readings are performed with a shift of 1 bit. This is extremely inconvenient as it can lead to malfunctions if used in a way that makes the order of data a problem.

The present invention, when the above-mentioned malfunction occurs,
It provides a means to immediately discover it and a countermeasure against it.

The present invention will be described in detail below with reference to embodiments and the drawings.

FIG. 4 is a block diagram showing a first embodiment of the present invention, and FIG. 5 is a time chart of FIG. 4. In FIG. 4, 41 is an input side changeover switch, 42 is an output side changeover switch, 43 is a monitoring pattern signal generator,
44 indicates a monitoring pattern signal detector. Other symbols are the same as those in FIGS. 1 and 2.

Input data 22 is sequentially written to the FIFO by write clock 23 as described above. Here data 2
2 is written synchronously, and there are m pieces of data (#1 to #m) within one cycle.

Similarly, the output data 24 is read out periodically, and m pieces of data (#1 to #m) are output in one cycle.

Note that the numbers (#1 to #m) of the input data 22 and output data 24 correspond to each other between input and output, and are the same data (m<n).

Here, a certain fixed time position (for example, the first
Input data 22 (#1) and second input data 22
(between #2)), switch the changeover switch 41 to the monitoring pattern signal generator 43 side, and select a specific monitoring pattern (for example, set it to "0" between the first input data and the second input data, and "1" is written between the first input data and the second input data, and such an alternating pattern of "0" and "1" is continued.
The input data 22 in FIG. 5 is the input data on the data input terminal 11 in FIG.

On the reading side, at a certain predetermined time position (for example, the first data 24 (#1) and the second data 24
(#2) readout clock 25 (between #1, #2)), the monitoring pattern signal readout clock 25
(P), switch the changeover switch 42 to the monitoring pattern signal detector 44 side, and transfer only the data read by this clock to the monitoring pattern signal detector 44.
send to. If data is written and read in the correct order, the monitoring pattern can also be detected correctly. In this case, if the write clock 23
Or, if an error occurs in the read clock 25, the read monitoring pattern will deviate from the normal position.
This can be easily detected by the detector 44.

When this malfunction is detected, the monitoring pattern signal detector 44 sends a reset signal to the reset terminal 15 of the FIFO to temporarily reset the FIFO and notify a control section (not shown) of the malfunction. A control unit (not shown) stops sending out the write clock and read clock, and then starts sending out the write clock from the next first input data, writes,
By restarting the read operation, data is written and read in the normal order again.

As described above, FIFO malfunctions can be easily discovered by inserting a specific monitoring pattern into serial input data when reading and writing to the FIFO, and monitoring this on the reading side.

Next, as a second embodiment, means for inserting a monitoring pattern signal separately from input data will be described.

FIG. 6 is a block diagram of the second embodiment, and FIG. 7 is a time chart of FIG. here
The FIFO is set such that a plurality of data input/output terminals of the FIFO, that is, data cell groups of the FIFO shown in the first embodiment are prepared in parallel, and writing and reading of each cell group are performed in the same manner. For convenience, the cell group connected to the monitoring pattern signal generator 43 and the monitoring pattern signal detector 44 will be referred to as a monitoring cell group.

Writing and reading of data is assumed to have an input/output cycle of m units, as in the previous embodiment, and the sixth
In the figure, the monitoring pattern signal generator 43 and the monitoring pattern signal detector 44 are connected to the input/output terminals 11 and 12, respectively. In this case, the input monitoring pattern 7 is output from the monitoring pattern signal generator 44.
1 is generated and other data is written, and the monitoring pattern 71 is also written to the monitoring cell group. For example, as one monitoring pattern 71, “1000000...
…”, the first input data 22 (#1)
"1" is written to the monitoring cell group using the write clock when writing. Thereafter, as well as writing the input data, the input monitoring pattern 71 is written.

On the other hand, when data is read, the output monitoring pattern 72 is also read using the data read clock. When writing and reading are operating normally, the output monitoring pattern 72 is also detected correctly.
If an error occurs in writing or reading, a shift occurs in the reading output monitoring pattern 72, and it can be discovered that an error has also occurred in the data reading order. Therefore, in this case, similarly to the first embodiment,
Reset the FIFO and start writing and reading again.
By performing the steps in order starting from the data, normal operation can be restored.

As explained above, the present invention allows the operation of the FIFO to be easily monitored and controlled by inputting a monitoring pattern signal when using the FIFO memory and detecting it on the reading side. This has the effect of imparting reliability to the FIFO function as a buffer memory.

[Brief explanation of the drawing]

Figure 1 is a basic configuration diagram of FIFO memory, Figure 2 is a time chart explaining Figure 1, and Figure 3 is a diagram of the basic configuration of FIFO memory.
Time chart explaining when FIFO memory malfunctions,
FIG. 4 is a block diagram of the first embodiment of the present invention, FIG. 5 is a time chart explaining FIG. 4, FIG. 6 is a block diagram of the second embodiment of the present invention, and FIG. A time chart explaining FIG. 6 is shown. 11...Data input terminal, 12...Data output terminal, 13...Write clock input terminal, 14...
... Read clock input terminal, 15 ... Reset terminal, 16 ... Memory cell, 17 ... Read/write control section, 21 ... Reset signal, 22 ... Input data signal, 23 ... Write clock, 24 ...
Output data signal, 25...Read clock, 41
... Input side changeover switch, 42 ... Output side changeover switch, 43 ... Monitoring pattern signal generator, 44
...Monitoring pattern signal detector, 71...Input monitoring pattern, 72...Output monitoring pattern.

Claims (1)

[Claims] 1. Writing and reading can be performed asynchronously, and input data is written periodically using a write clock synchronized with input data, and read data is read periodically using a read clock. The number of write data and the number of read data are equal.
In the FIFO memory supervisory control method, a supervisory clock is inserted between specific clocks of the write clocks for each cycle described above, a supervisory pattern is written using the supervisory clock, and output data is read out in the order in which input data is written using a read clock. By checking the data read at the read clock position equal to the monitoring clock position for each cycle of data, abnormalities in the write operation due to dropping or adding of the write clock of the FIFO memory are monitored; If it is determined that there is an abnormality, the above FIFO
A FIFO memory monitoring and control method that resets the memory and starts writing and reading operations again. 2 Writing and reading can be performed asynchronously, input data is written periodically using a write clock synchronized with input data, and read data is read periodically using a read clock.The number of written data and read data for each cycle. The number of data is equal for each
In the FIFO memory supervisory control method, the FIFO memory is controlled by writing a supervisory pattern to the supervisory FIFO memory arranged in parallel with the FIFO memory using the write clock, and checking the supervisory pattern read from the supervisory FIFO memory using the read clock. It monitors write operation abnormalities caused by dropping or adding a memory write clock, and if it is determined to be abnormal, resets the FIFO memory mentioned above,
A FIFO memory monitoring control method characterized by restarting write and read operations.