JPS6327754B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device, and particularly to an image processing device suitable for application to an optical character reading device.

Conventionally, an OCR (optical character reading) device has an imaging unit that scans an image on a form and performs photoelectric conversion, and an analog-digital conversion circuit that converts an analog video signal output from the imaging unit into a digital value signal. These constitute an image input section.

Then, the digitalized pixel information obtained from this image input section is stored in an image memory, and characters are recognized from the contents of the image memory under program control or the like.

In recent years, before performing recognition processing, processes have been developed to convert pixel information such as characters stored in the image memory into skeleton lines, to remove noise that is unnecessary information, and to determine slice levels. Various types of preprocessing are performed, but these are performed by scanning the entire storage area of the image memory without any corner and processing uniformly. Therefore, shift memories have often come to be used as image memories suitable for such image processing.

FIG. 1 shows a conventional circuit that performs such preprocessing using a shift memory. In the figure, SM ₁ to _{SM 4} are shift memories each capable of storing pixel information Vid for one scan, MSK is a mask processing circuit, b ₁ , b ₂ , b ₃ ,
b _{4 .} . . b ₂₀₄₈ is a storage area corresponding to one pixel in each shift memory. To explain the operation, the input pixel information Vid is transferred to the shift memory for the first scan.
It is given to the first storage area b ₁ of SM ₁ , and then shifted to the subsequent storage areas b ₂ , b ₃ , etc. as shown by arrow A in synchronization with the clock signal _. When it reaches that point, it is moved to the first storage area of the shift memory _SM2 for the second scanning line.

In the shift memory SM ₂ for the second scanning line, pixel information is shifted in exactly the same way as in the shift memory for the first scanning line, and the same applies to the shift memories for the other scanning lines. Since the pixel information moves in this way, if the mask processing circuit MSK fixedly monitors, for example, the contents of the storage area in the shaded area, it will be equivalent to monitoring the pixel information group while scanning it from a relative perspective. This is advantageous in terms of processing time and circuit configuration since address selection is not required.

However, in the conventional circuit, the shift memory SM ₁ has a capacity large enough to store a group of pixel information per scan obtained from the image input section.
Since SM ₂ , SM ₃ ... are provided, there is a period in which the start and end of the scanning line are simultaneously read by the mask processing circuit MSK, and during this period, continuous processing makes it impossible to perform correct processing, so the scanning line is eventually There was an inconvenience that the starting end and ending end could not be treated as valid information.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus that can eliminate such inconveniences and process all of the information on a scanning line continuously and by the same processing operation using simple means.

In the present invention, this purpose is to provide an image input means equipped with a conversion means for scanning an image, photoelectric conversion and A/D conversion, a shift memory for storing a group of pixel information obtained from the image input means, and a necessary mask. In an image processing apparatus equipped with a processing circuit that sequentially and selectively reads and processes the contents of the shift memory according to a pattern, a halftone image signal from the image input means is inputted at one end, and the halftone image signal is A gate means whose other end receives a signal from a control signal generation circuit which outputs a gate signal of an image signal in synchronization with a video signal, and a white pixel in which a plurality of this gate means are arranged in parallel according to the gradation of the image signal. An additional circuit is provided to provide a shift register gate signal that is longer than the gate signal of the halftone image signal by a predetermined number of pixels in synchronization with the clock signal, and inputs the information group from the image input means to the shift memory. This is achieved by inserting and storing a predetermined number of pieces of white pixel information in the portions corresponding to each scanning line in the image data, and one embodiment thereof will be described in detail below with reference to the drawings.

FIG. 2 is a diagram showing a schematic configuration of an OCR device to which the present invention is applied, and FIG. 3 is a diagram showing a detailed configuration of a preprocessing circuit to which the present invention is applied in the OCR device shown in FIG. It is.

As shown in FIG. 2, the OCR device transports the form 10 in the direction of arrow B, and photoelectrically converts the image on the form while scanning it in the direction of arrow C using an image sensor 30 via an optical system 20. It's summery. This photoelectrically converted analog image signal is amplified through an amplifier 40 and then A/D
The converter 50 converts the image signal into a digital value image signal with 16 tones in which one pixel is made up of 4 bits, for example. The preprocessing circuit 60 to which the present invention is applied receives the 16-tone image signal that has become a digital value in this way, and
It is compressed into 1 bit (binary) information per pixel and transmitted, and the binary image information is temporarily stored in the video memory 70 and cut out (selected) character by character by the cutting circuit 80. After that, output for each character
For CHAR, characters are determined in a recognition processing circuit (not shown).

The present invention provides a preprocessing circuit 6 for such an OCR device.
0, this is implemented by expanding the storage capacity of the shift memory for each scan line.

That is, FIG. 3 shows a preprocessing circuit having a shift memory with an expanded storage capacity in this manner.

In FIG. 3, reference numeral 200 detects the end of a scanning line with respect to pixel information of 16 tones representing one pixel in 4 bits, for example, which is given from the A/D converter 50.
This is a white pixel addition circuit that adds pixel information indicating white "0000" for pixels (4 bits x 12 pieces). Also, 61
a#1, 61b#1 is one scanning line (for example
61a is a shift memory that stores pixel information of 2048 pixels) and the above 12 added pixel information.
#1 is a storage area for 3 pixels that can be read out,
61b#1 is the remaining storage area. 61a
The same applies to #2, 61b #2, 61a #3...61X, etc., and each of these shift memories for one scanning line transfers pixel information from the rear end of the previous shift memory to the beginning position of the shift memory. connected so that

Now, the shift memories for one scanning line, for example 61a#1 and 61b#2, have a storage capacity of 2060 pixels in total, and therefore the portion 6 that is not read out is
The storage capacity of 1b#1 is 2057 pixels. Therefore, when 2048 halftone pixel information (for one scanning line) is given from the image input section, 12 white pixel information is added to this and the information is transferred to the shift memory 61a.
#1, 61b Stored in #1.

FIG. 4 is a circuit configuration diagram and a time chart for inserting 12 white pixels into the shift memory. In the figure, Vid is a 4-bit video signal representing 16 tones, 201 to 204 are AND circuits, and 205 teeth
A CCD output gate signal generation circuit 206 is a shift memory gate signal generation circuit.

A 4-bit video signal Vid (0, 1, 2, 4) is input to the white pixel adding circuit 200 in synchronization with the video clock T (period T ₁ ). The tone at this time is
4 bits "0000" is "white" and 4 bits "1111" is "black". A control signal from a CCD output gate signal generation circuit 205 is input to one terminal of each of AND circuits 201 to 204 to which these 4-bit signals are input. This control signal is output for a length of _2048T1 by synchronizing the gate signal of the CCD output shown in FIG. 4B with the video clock T.

Furthermore, a control signal is output to the shift memory 61a#1 so that the output from the gate control signal generation circuit 206 is shifted by the length of _2060T1 in synchronization with the video clock T. 1, 12 pieces of white pixel information "0000" are automatically inserted and added after cycle 2048.
As a result, a distance of 12 pixels is always maintained between the pixel information at the end of one scanning line and the pixel information at the beginning of the next scanning line, and white pixel information is filled in between. . Then, as in the illustrated example, pixel information that is continuous for at most three pixels in the scanning line direction is transferred to each shift memory 61a#1, 61a.
#2, 61a #3, and performs processing in addition to, for example, the average value circuit 63 (details of this average value processing are described in Japanese Patent Application No. 52-41245, which was invented by the present inventor). In this case, the starting and ending ends of the scanning line will not be processed together. Therefore,
It is possible to perform a process of calculating the average value of 3×3 pixel information corresponding to the starting end and ending end of a scanning line in an independent state without interfering with each other. Of course,
The same applies when processing other than the average value.

By the way, in this embodiment, the shift memory 61X based on the present invention is used not only to calculate the average value, but also to calculate the maximum value for 5 x 5 pixels of the average value thus calculated. The operation of each part of this embodiment, including this operation, will be described below.

In the figure, 65 is a maximum value detection circuit, which inputs pixel information (average processed) having the same position in the scanning line direction for each of the five scanning lines, and detects the maximum value of the five pixel information. Works to extract things. 67 is also a maximum value detection circuit,
It operates to receive the output of five pixels in the scanning line direction from the maximum value detection circuit 65 in the previous stage via the shift register 66 and extract the maximum value thereof.
In this way, 69 extracts a total of 3 pixels separated by 5 pixels in the scanning line direction from the maximum value of the 5 x 5 pixel information (averaged value) through a 10-stage shift register. , a slice level determination circuit that determines a required slice level. When the slice level is thus obtained from the slice level determination circuit 69, the comparator circuit 100 uses the input image information Vid.
is received from the shift memory 64 for timing adjustment, and is compared with the slice level to binarize the input image information Vid. Note that when the input image information Vid to be compared at this time is placed at the center of gravity of the pixel information group (5 x 15 pieces) read to determine the slice level, it is indicated by a broken line in Fig. 3. A shift transfer route for input pixel information may be set as shown in FIG.

As explained above, according to the present invention, it is possible to independently read pixel information corresponding to the starting end and ending end of a scanning line according to masks having two or more widths in the scanning direction, and to effectively handle each of them. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit that performs conventional preprocessing and has a shift memory, FIG. 2 is a diagram showing an optical reading device having a preprocessing circuit to which the present invention is applied, and FIG. 3 is a diagram showing a circuit to which the present invention is applied. FIG. 4 is a diagram showing a specific configuration example of the applied preprocessing circuit, and is a circuit configuration diagram and a time chart for inserting 12 white pixels into the shift memory. 30 is an image sensor, 40 is an amplifier, 50 is an A/D converter, 60 is a preprocessing circuit, 70 is a video memory, 200 is a white pixel addition circuit, 61a#1, 6
1b#1 is a shift memory for storing pixel information for one scanning line, 61a#2 and 61b#2 are shift memories for storing pixel information for another scanning line, 63 is an average value circuit, and 65 and 67 are Maximum value detection circuit, 66,6
8 is a shift register, 69 is a slice level determining circuit, 100 is a comparison circuit, and Vid is 4 indicating 16 gradations.
201 to 204 are AND circuits, 205 is a CCD output gate signal generation circuit, and 206 is a shift memory gate signal generation circuit.

Claims (1)

[Scope of Claims] 1. An image input means equipped with conversion means for scanning an image, photoelectric conversion and A/D conversion; a shift memory storing a group of pixel information obtained from the image input means; Therefore, in an image processing apparatus equipped with a processing circuit that sequentially and selectively reads and processes the contents of the shift memory, the halftone image signal from the image input means is inputted at one end, and the halftone image signal A gate means whose other end receives a signal from a control signal generation circuit which outputs a gate signal in synchronization with a video signal, and a white pixel addition circuit in which a plurality of these gate means are arranged in parallel according to the gradation of the image signal. A gate signal of a shift register which is longer than the gate signal of the halftone image signal by a predetermined number of pixels is provided in synchronization with a clock signal, and a gate signal of a shift register which is longer than the gate signal of the halftone image signal by a predetermined number of pixels is provided to the shift memory. An image processing device characterized in that a predetermined number of pieces of white pixel information are inserted and stored in a portion corresponding to each scanning line.