JPS6327796B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information transfer method for a major-minor type (mainly block replicate transfer type) magnetic bubble memory device.

[Conventional technology]

As a data input/output method for magnetic bubble memory,
A major/minor system is used, and in particular, a block replicate transfer system that has a read major line and a write major line and has a relatively high transfer rate is used. This type of major-minor magnetic bubble memory has
The existence of defective loops (minor loops) is unavoidable under current circumstances. Therefore, when transferring information between a magnetic bubble memory and an external device, a buffer is essential to mask the above-mentioned defective loop, and conventionally, a shift register,
Alternatively, FIFO (first-in, first-out) is used.

[Problem that the invention seeks to solve]

When performing parallel information transfer, a shift register is mainly used to perform parallel-to-serial conversion or its inverse conversion. However, in this case, there is a problem that the period until the shift register becomes full or empty depends on the number of defective loops that exist in that period, and the transfer period of information (in word units) is not constant. Furthermore, when performing serial information transfer, it is not possible to use a shift register with a common input and output shift clock due to the presence of defective loops, so a FIFO with different input and output clocks is used. However, even in this case, the FIFO is 1
If the information has the number of bits for a page, it is possible to keep the transfer cycle of information (in word units) constant within the first page, but if it spans multiple pages, the bit length of one page, Number of bad loops, 1
This problem is affected by the number of bits in a word, the number of words in one page, etc., and the spacing between information (words) cannot be guaranteed at the joints of pages.
In other words, in any case, the number of information (words) per page is intended to be 2 ⁿ , and the time interval between information (words) is important, such as data stored on magnetic tape. It is difficult to record the data over multiple pages of magnetic bubble memory.

[Means for solving problems]

An object of the present invention is to improve magnetic bubble memory by using a data buffer such as FIFO that can input and output independently control valid information of a fixed period and invalid information between the valid information in synchronization with the drive frequency of the magnetic bubble memory. Based on the concept of transferring information in response to loops and defective loops, it is possible to record data in which the time interval of information (words) is important over multiple pages of magnetic bubble memory.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram of a magnetic bubble memory device as an embodiment of the present invention. In FIG. 1, 1 is a magnetic bubble memory, 2 is a data buffer, such as a FIFO, whose input and output can be controlled independently.
3 is a control circuit for generating the input clock signal CKI and the output clock signal CKO of the data buffer 2, and this control circuit 3 has the following information: the defective loop number of the magnetic bubble memory 1, the valid data period T 1 of the external device, and the invalid data period T ₁ of the external device. The data period T ₂ is stored in advance. The switch SW ₁ also performs a write operation (W) for inputting data D _io from an external device (not shown) to the magnetic bubble memory 1 as write data WD via the data buffer 2, and a write operation (W) for inputting data D io from an external device (not shown) to the magnetic bubble memory 1 as write data WD. This is for switching between a read operation in which the read data RD is sent to an external device as output data D _put via the data buffer 2, and is controlled by the control circuit 3.

An example of the control circuit 3 of FIG. 1 is shown in FIG. In FIG. 4, 31 is a memory for storing the defective loop number, 32 is an address scanning counter that generates the address of the memory, and 33 is a valid data cycle.
T ₁ is a period setting counter for setting the invalid data period T ₂ , and 34 is a write operation/read operation control circuit. In addition, switch SW ₂ is the switch shown in Figure 1.
It has the same configuration as SW ₁ , and switches the clock signals CKI and CKO depending on writing/reading.

The write operation of the circuit of FIG. 1 will be explained with reference to FIGS. 2a to 2e. In this case, each switch
SW ₁ and SW ₂ are tilted toward the upper terminal W. Drive pulse signal of the magnetic bubble memory 1 shown in FIG. 2a
Data _Dio is transferred from an external device to the data buffer 2 in synchronization with CLK (reference clock).
As shown in FIG. 2b, this data D _io is transferred at a constant period T in which valid data (period T ₁ ) and invalid data (period T ₂ ) are paired. this cycle
T ₁ and T ₂ are set in the cycle setting counter 33 in advance. Therefore, as shown in FIG. 2c, the control circuit 3 outputs a clock signal CKI (which is synchronized with the reference clock shown in _FIG . ))
is generated in the data buffer 2. As a result, only valid data will be stored in the data buffer 2. On the other hand, when a certain amount of data is accumulated in the data buffer 2, the control circuit 3 synchronizes with the reference clock shown in FIG. 2a, as shown in FIG.
The clock signal CKO (this
CKO (W)) occurs. For example, in this case, the loop “0”, “1”, “3”, “4”, “5”
,
“7”, … are good loops, and loops “2”, “6”
is a bad loop. As a result, as shown by write data WD in FIG. 2e, valid data from the external device is not written into the bad loop, but only into the good loop. In other words, invalid data inserted at regular intervals among the data D _io corresponds to being written into a defective loop of the magnetic bubble memory 1 .

Next, the read operation of the circuit shown in FIG. 1 will be explained with reference to FIG. In this case, each switch
SW ₁ and SW ₂ are tilted downward. The read data RD is read from the magnetic bubble memory 1 in synchronization with the reference clock CLK shown in FIG. 3a. but,
In this case, as mentioned above, the loop “0”, “1”,
"3", "4", "5", . . . are good loops, and loops "2", "6", . . . are bad loops. Therefore, the control circuit 3 samples the data of only good loops and stores them in the data buffer 2 using the clock signal CKI (hereinafter referred to as CKI(R)) shown in FIG. On the other hand, when a certain amount of data is accumulated in the data buffer 2, the control circuit 3 generates the clock CKO (hereinafter referred to as CKO(R)) shown in FIG. 3d. This clock CKO(R) repeatedly includes a predetermined valid data period _T1 and an invalid data period _T2 . Therefore, as shown in output data D _put in FIG. 3e, data RD from data buffer 2 is sent out as valid data periods T ₁ and each valid data period is accompanied by an invalid data period T ₂ .

Thus, during a write operation, the clock signal CKI is in the form of external data _Dio , that is,
It is matched with the output of the cycle setting counter 33, and
The clock signal CKO is the memory 31 for storing the good loop number of the magnetic bubble memory 1, that is, the bad loop number.
is adjusted to the output of Conversely, during a read operation, the clock signal CKI is applied to the memory 3 for storing the good loop or bad loop number of the magnetic bubble memory 1.
1 output, and the clock signal CKO
is matched with the format of the external data D _put , that is, the output of the cycle setting counter 33. Therefore, if the sum of valid data and invalid data is set as a factor of the capacity for one page, the data buffer 2 will never become full or empty, and will be able to pass through multiple pages. Then data transfer becomes possible. Note that one page here usually refers to the number of minor loops; for example, if it is 512, 512=
2 ⁹ , so the factors are 2, 4, 8, 16,
..., 256.

In the above embodiment, information is transferred between the magnetic bubble memory device and the external device in a serial format, but valid data is converted to parallel data and data is transferred in parallel at each block transfer time of serial data. Even if the data is transferred to an external device in this format and the data transferred from the external device is subjected to the above-mentioned inverse conversion, the effects of the present invention will not be lost.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to record large-scale data in which the intervals between information (words) have important meanings in a magnetic bubble memory. Furthermore, normally, in a major-minor type magnetic bubble memory device, the position of the defective loop differs from device to device, so parallel operation cannot be performed without a spare device for the defective loop. Since the data is converted into invalid data, parallel operation is possible without using extra spare devices, and the data transfer speed can also be improved. It is also possible to keep the word interval constant by considering the number of devices and the number of devices. Furthermore, it is also possible to record for a long time by seamlessly switching between a large number of devices one by one.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a magnetic bubble memory device as an embodiment of the present invention, FIGS. 2 and 3 are timing diagrams for explaining the circuit operation of FIG. 1, and FIG. 4 is a diagram of the circuit shown in FIG. FIG. 2 is a circuit diagram showing an example of a control circuit of FIG. 1...Magnetic bubble memory, 2...Data buffer (FIFO), 3...Control device, WD...Write data, RD...Read data, CKI...FIFO2 input clock signal, CKO...FIFO2 output clock signal .

Claims (1)

[Claims] 1. A major-minor type magnetic bubble memory comprising a magnetic bubble memory 1 and a data buffer 2 that temporarily stores input/output information of the magnetic bubble memory and can control input/output independently. In the device, between the data buffer and the external device, effective information _T1 of the external device is synchronized with the drive clock CLK of the magnetic bubble memory and has a constant period T.
Data is transferred using clocks CKI (W) and CKO (R) synchronized with valid information T ₁ of invalid information T ₂ , and between the data buffer and the magnetic bubble memory, a driving clock of the magnetic bubble memory is used.
A clock that is synchronized with CLK and synchronized with the good minor loop of page 1 T' of the magnetic bubble memory.
An information transfer method for a magnetic bubble memory device, in which data is transferred using CKO (W) and CKI (R), and invalid information of the external device is made to correspond to a defective minor loop of the magnetic bubble memory. 2 Valid information _T1 and invalid information of the external device
Claim 1: The number of driving clocks CLK of the magnetic bubble memory included in a constant period T of _T2 is a factor of the number of driving clocks CLK of the memory corresponding to one page T' of the magnetic bubble memory. The information transfer method of the magnetic bubble memory device described in .