JPS6328337B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming interdigital electrodes having an electrode width in the submicron range.

(Prior Art and Problems to be Solved by the Invention) In recent years, in semiconductor devices and the like, a technology for forming electrodes having a width in the submicron region has been required in order to improve the degree of integration and high speed. However, when it comes to forming interdigital electrodes with line widths in the submicron range, the electrode width is different from the exposure width due to the density of the electrodes due to the proximity effect of exposure, making it impossible to form good interdigital electrodes. There was a problem. (For example, "Proceedings of the 26th Applied Physics Association Conference," 29p-S-6, Spring 1979).

An object of the present invention is to provide a method for forming interdigital electrodes with good electrode width accuracy.

(Means for solving the problem) According to the present invention, simply repeated lines and
The process of forming a conductor pattern consisting of and spaces, and the process of forming a first conductor pattern that covers the area other than the butt
forming a resist pattern, etching the conductor pattern, then removing the first resist pattern, and forming a second resist pattern covering areas other than the external connection electrodes on the etched conductor pattern. A method for forming interdigital electrodes is obtained, comprising the steps of depositing a layer of conductive material thereon and then removing the second resist pattern.

(Example) Hereinafter, a method for forming interdigital electrodes according to the present invention will be described in detail with reference to the drawings.

Assume that we want to obtain interdigital electrodes as shown in FIG. Here, 1 is an external connection electrode, 2 is an interdigital electrode, and 3 is an abutting portion. Interdigital electrode width is 1
When forming conventional interdigital electrodes of micron size or larger, exposure is performed according to the pattern shown in Figure 1.
A resist pattern as shown in the figure was formed. However, as the width of the interdigital electrodes becomes finer in the submicron range, the interaction between the exposure patterns of the interdigital electrodes (the influence of exposure fog) cannot be ignored. (This is called the proximity effect). That is,
As shown in Fig. 7a, even though the interdigital electrode width is on the order of submicrons, if the shaded area in Fig. 1 is exposed and developed in the same way as when the width is 1 micron or more, Fig. 7a In areas where the interdigital electrodes are close to each other, such as the shaded area, the electrode width becomes thicker as shown in 701, and due to normal process variations such as exposure and development variations, the electrode fingers are partially connected to their neighbors. more likely to become defective. On the other hand, if the overall exposure amount is reduced, the electrode fingers will not be connected, but as shown in 702 in Figure 7b, the electrode width next to the abutting part will become narrower, and the exposure and development There has been a problem in that the electrode fingers tend to be partially disconnected due to normal process variations such as variations in the electrodes, making them more likely to be defective.

The present invention solves this problem of proximity effect as follows.

First, a simply repeated line and space pattern as shown in FIG. 2 is formed using a conductive material on a substrate. 11 is a conductive material portion, and 12 is a substrate. Line and space like this
Since the pattern has only one pattern parameter to be controlled, it is relatively easy to form the pattern even if the pattern width is on the order of submicrons.

Next, a resist is applied thereon and exposed to light so as to form a resist pattern (first resist pattern) covering areas other than the butt portions as shown in FIG.
Here, 14 is a region where the resist remains, and 15 is a region (space portion) from which the resist is removed.
At this time, the conductor pattern as shown in FIG. 2 and the first resist pattern as shown in FIG. 3 are aligned as shown in FIG. 4, and the conductor material 11 in the space part of the first resist pattern is After removing the resist 14, the resist 14 is peeled off to form a conductive pattern in which the conductive material in the abutting portions and unnecessary external areas is removed.

Next, a resist is applied thereon and exposed to light so as to form a resist pattern (second resist pattern) covering areas other than the external connection electrodes as shown in FIG. Here, 17 is the area where the resist remains, and 18
is the area (space part) from which the resist is removed. The second resist pattern shown in FIG. 5 is aligned with the conductor pattern as shown in FIG. 6. Second
A desired interdigital electrode is obtained by depositing a conductive material in the space portion 18 of the resist pattern by a lift-off method, an electrodeposition method, or the like, and then peeling off the resist 17.

In order to form a conductor line and space pattern in the above process, a resist is applied onto the substrate, a line and space pattern of the resist is formed by exposure and development, and then a line and space pattern of the resist is formed by electrodeposition. A method of forming a conductive material is desirable.

(Effects of the Invention) As described above, according to the present invention, the pattern with the narrowest line width is formed from a simply repeated line and space pattern, so there is no adverse effect of the proximity effect due to exposure fog, and the line width is It becomes possible to form interdigital electrodes with high precision.

[Brief explanation of the drawing]

Figure 1 is a plan view showing the desired interdigital electrodes;
The figure is a plan view showing a simple repeating line and space conductor pattern, Figure 3 is a plan view showing a complex first pattern, and Figure 4 is a plan view showing the alignment of the conductor pattern and the first pattern. Fig. 5 is a plan view showing the second pattern; Fig. 6 is a plan view showing the second pattern;
The figure is a plan view showing the state of alignment between the second pattern and the conductor pattern, and FIGS. 7a and 7b are plan views showing examples of defective patterns when formed by the conventional method. In the figure, 1 is an electrode for external connection, 2 is an interdigital electrode,
3 is a butting part, 11 is a conductive material part of a conductor pattern, 12 is a substrate, 14 is a resist remaining part of a complicated first pattern, 15 is a space part of the first pattern, and 17 is a resist remaining part of a second pattern. Department,
18 is a space part of the second pattern, 701 is a part near the interdigital electrodes, and 702 is a finger electrode part.

Claims (1)

[Claims] 1. A step of forming a conductor pattern consisting of simply repeated lines and spaces, forming a first resist pattern covering areas other than the butt portions thereon, and etching the conductor pattern,
Thereafter, the first resist pattern is removed, a second resist pattern is formed on the etched conductor pattern to cover areas other than the external connection electrodes, and a conductor material layer is deposited thereon.
1. A method for forming interdigital electrodes, comprising the step of removing a resist pattern.