JPS6329437B2 - - Google Patents
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- Publication number
- JPS6329437B2 JPS6329437B2 JP58197692A JP19769283A JPS6329437B2 JP S6329437 B2 JPS6329437 B2 JP S6329437B2 JP 58197692 A JP58197692 A JP 58197692A JP 19769283 A JP19769283 A JP 19769283A JP S6329437 B2 JPS6329437 B2 JP S6329437B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- bonding
- electrode
- substrate
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000463 material Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910000846 In alloy Inorganic materials 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910020174 Pb-In Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 231100000252 nontoxic Toxicity 0.000 description 1
- 230000003000 nontoxic effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 231100000167 toxic agent Toxicity 0.000 description 1
- 239000003440 toxic substance Substances 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、計算機用演算記憶回路を構成するス
イツチング素子、微小磁場測定素子あるいは電圧
標準器などとして応用され、かつスイツチング時
間や測定精度などの点においてすぐれた性能を有
する超電導ジヨセフソン素子を利用した超電導デ
バイスのボンデイングパツドの改良に関するもの
である。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is applied as a switching element constituting an arithmetic storage circuit for a computer, a micromagnetic field measuring element, a voltage standard, etc. This invention relates to improvements in bonding pads for superconducting devices that utilize superconducting Josephson elements that have excellent performance.
従来実用に供されている超電導材料例えば、
Nb、Pb、Pb−In、Pb−Au−In、Mo−Re、
V3Si、Pb−Bi等のボンデイングパツドと外部金
属端子間の接合部の断面構造を、第１図に示す。
超電導デバイスでは、基板１の上にベース電極層
のパツド２、トンネル接合部３、対向電極層のパ
ツド４、絶縁層５を介して制御線電極層のパツド
６を有する。さらに、この上に保護膜７として
SiOもしくはSiO2層が被着される。また、外部電
極端子のパツド８と接合するために、ボンデイン
グパツド用のスルホール９が必要である。この接
合材料１０には、通常Hgが用いられている。し
かし、Hgは、有毒物質であり、しかも、室温で
は液体状であるために、ボンデイング時に接合部
から流出することが多くシヨートの原因となる。
また、極めて取りあつかいに対して危険性が高
い。
Superconducting materials that have been put into practical use include, for example:
Nb, Pb, Pb-In, Pb-Au-In, Mo-Re,
FIG. 1 shows a cross-sectional structure of a joint between a V 3 Si, Pb-Bi, etc. bonding pad and an external metal terminal.
The superconducting device has on a substrate 1 a pad 2 of a base electrode layer, a tunnel junction 3, a pad 4 of a counter electrode layer, and a pad 6 of a control line electrode layer via an insulating layer 5. Furthermore, a protective film 7 is added on top of this.
A layer of SiO or SiO 2 is deposited. In addition, a through hole 9 for a bonding pad is required for bonding with the pad 8 of the external electrode terminal. This bonding material 10 usually uses Hg. However, since Hg is a toxic substance and is in a liquid state at room temperature, it often flows out from the joint during bonding, causing shoots.
It is also extremely dangerous to handle.
他の欠点は、動作温度である液体He温度
（4.2K）と室温との熱サイクルを経験することに
よつてボンデイングパツドの一部が欠損を生じ特
性の劣化を生ずることが、しばしばあつた。 Another drawback is that part of the bonding pad is often damaged due to thermal cycling between the operating temperature of liquid He (4.2K) and room temperature, resulting in deterioration of characteristics. .
本発明は、従来の欠点をなくし、信頼性の高い
超電導デバイス素子のボンデイングパツドを提供
しようとするものである。
The present invention aims to eliminate the conventional drawbacks and provide a highly reliable bonding pad for superconducting device elements.
〔発明の概要〕
第２図に示すように、接合部の接合材料１０に
Gaもしくは、Ga−In系合金（Inを０〜90at％含
む）を用いることを特徴とするものである。これ
らの金属は、室温では、固体であるが、38〜70℃
に熱することにより、液体状になる。すなわち、
ボンデイング直前に各パツド部、２，４，６上に
Gaの金属粒を乗せ外部金属端子８とパツド部の
位置合せをした後、基板温度40℃に加熱し、30秒
間保持すれば接合部の接合材料が流れ出すことな
く完全な接合を得ることが出来る。また、この時
にわずかな荷重（３〜５ｇ）を加えてやれば、接
合強度が大きくなる。[Summary of the Invention] As shown in FIG.
It is characterized by using Ga or a Ga-In alloy (containing 0 to 90 at% In). These metals are solid at room temperature, but at 38-70℃
When heated, it becomes liquid. That is,
Immediately before bonding, place on each pad, 2, 4, and 6.
After placing the Ga metal grains and aligning the external metal terminal 8 and the pad part, heat the substrate to 40℃ and hold it for 30 seconds to obtain a perfect bond without the bonding material flowing out of the bonding area. . Moreover, if a slight load (3 to 5 g) is applied at this time, the bonding strength will be increased.
以下には、実施例について詳細に述べる。 Examples will be described in detail below.
実施例 １
超電導デバイスとしては、Nb〜Nb酸化物−
Pb合金（Pb−Au−In系）からなる素子のボンデ
イングパツドを次のようなプロセス工程により作
製した。まず、ベース電極用のマスクを、
AZ1350J（米国、シプレイ社の商品名）ホトレジ
ストを用いて600nｍの厚さに作製した後、ポス
トベークを120℃×20分間で処理した。Example 1 As a superconducting device, Nb to Nb oxide
A bonding pad for an element made of a Pb alloy (Pb-Au-In system) was fabricated using the following process steps. First, the mask for the base electrode,
After fabricating to a thickness of 600 nm using AZ1350J (trade name of Shipley, USA) photoresist, post-baking was performed at 120° C. for 20 minutes.
次に、真空装置内で電子ビームによるNb膜を
350nｍの厚さに蒸着した。蒸着時の真空度を５
×10-7Torr、基板温度は室温とし、基板には、
直径50mmφ、厚さ450μ、＜100＞ｎ型のSi基板を用
いた。なお、Si基板上には300nｍの熱酸化膜が施
してある。蒸着後を真空室から取り出して、アセ
トン中でリフトオフを行う。この時点では、ベー
ス電極とパツドのみが残され、マスクに用いたホ
トレジストは完全に除去される。次に、対向電極
用のマスクをベース電極と同様な方法で作製し、
真空装置内において、Nbベース電極面のクリー
ニングをDC法による不活性Arガスを用いたライ
トスパツタにより行つた。この時の条件は、圧力
50ｍTorr、負電圧400eV、放電電流10mA、スパ
ツタ時間10分である。引続いて、ベルジヤ内に
O2ガスを注入し、50ｍTorrになるように圧力を
調節した後、次の条件でNbのトンネリング用酸
化膜を作製した。負電圧600eV、放電電流
10mA、酸化時間10分である。次いでベルジヤ内
の真空度を２×10- 6Torrに減圧した後、抵抗加
熱ヒータによりPb膜を250nｍの厚さに蒸着し、
引続いてAu膜を5nｍの厚さに蒸着し、さらに、
この上にIn膜を50nｍの厚さに蒸着し三層構造と
した。蒸着後、真空室から取り出してアセトン中
でリフトオフを行う。この時にはすでにトンネル
接合部が作製されており、対向電極とパツドのみ
が残る。次に、再びリフトオフ法を用いてSiOの
絶縁層を250nｍの厚さに抵抗加熱ヒータにより
低温蒸着をする。この際、ベース電極および対向
電極のパツドは、露出するように蒸着する。次に
制御線用のマスクをベース電極および対向電極と
同様な方法で作製し、真空室内の真空度を２×
10-6Torr以下で抵抗加熱ヒータによりPb膜を
300nｍの厚さに蒸着し、引き続いてInを100nｍ
の厚さに蒸着し二層構造とした。蒸着後真空室か
ら取り出してアセトン中でリフトオフを行う。こ
の時、制御線電極とパツドのみが残る。最後に、
SiOのリフトオフ法による保護膜が1μの厚さに形
成される。この保護膜を作製する際、ベース電
極、対向電極および制御線の各パツドは、外部金
属端子と接続するために露出している。このよう
にして超電導デバイス素子を作製した後、外部電
極端子と接合する前に各パツドの表面を不活性
Arガスを用いてライトスパツタを行いクリーニ
ングを行つた。 Next, the Nb film is deposited using an electron beam in a vacuum device.
It was deposited to a thickness of 350 nm. The degree of vacuum during vapor deposition is 5.
×10 -7 Torr, the substrate temperature is room temperature, and the substrate is
A <100> n-type Si substrate with a diameter of 50 mmφ and a thickness of 450 μm was used. Note that a 300 nm thick thermal oxide film is formed on the Si substrate. After vapor deposition, the sample is removed from the vacuum chamber and lift-off is performed in acetone. At this point, only the base electrode and pad remain, and the photoresist used for the mask is completely removed. Next, a mask for the counter electrode is made in the same way as for the base electrode,
In a vacuum apparatus, the Nb-based electrode surface was cleaned by light sputtering using inert Ar gas using the DC method. The conditions at this time are pressure
50mTorr, negative voltage 400eV, discharge current 10mA, sputtering time 10 minutes. Subsequently, in Belgiya
After injecting O 2 gas and adjusting the pressure to 50 mTorr, a Nb tunneling oxide film was produced under the following conditions. Negative voltage 600eV, discharge current
10mA, oxidation time 10 minutes. Next, after reducing the vacuum inside the bell gear to 2 × 10 - 6 Torr, a Pb film was deposited to a thickness of 250 nm using a resistance heater.
Subsequently, an Au film was deposited to a thickness of 5 nm, and
On top of this, an In film was deposited to a thickness of 50 nm to form a three-layer structure. After vapor deposition, it is removed from the vacuum chamber and lift-off is performed in acetone. At this time, the tunnel junction has already been made, and only the counter electrode and pad remain. Next, using the lift-off method again, an insulating layer of SiO is deposited at a low temperature using a resistance heater to a thickness of 250 nm. At this time, the pads of the base electrode and counter electrode are deposited so as to be exposed. Next, a mask for the control line is made in the same way as the base electrode and counter electrode, and the degree of vacuum in the vacuum chamber is adjusted to 2×.
The Pb film is heated using a resistance heater at less than 10 -6 Torr.
Deposited to a thickness of 300nm, followed by 100nm of In.
The film was deposited to a thickness of , creating a two-layer structure. After vapor deposition, it is removed from the vacuum chamber and lift-off is performed in acetone. At this time, only the control line electrode and pad remain. lastly,
A protective film with a thickness of 1 μm is formed using the SiO lift-off method. When producing this protective film, the pads of the base electrode, counter electrode, and control line are exposed for connection to external metal terminals. After fabricating a superconducting device element in this way, the surface of each pad is inertized before being bonded to an external electrode terminal.
Cleaning was performed by light sputtering using Ar gas.
接合法は、通常用いられているボンデイング装
置を用いた。各電極のパツドにGaの金属粒を乗
せる。各ボンデイングパツドはスルホールになつ
ているために、接合材料であるGaの金属粒を乗
せても落ちない。これらの作業は、すべて真空ピ
ンセツトを使用して行つた。一方、外部電極端子
は、基板１２にエポキシーを用いてAl蒸着によ
り作製した対向電極パツドを用いた。超電導デバ
イス素子のパツド部と外部電極パツドとの位置合
せをした後に、基板温度40℃に加熱し、30ｇの荷
重をゆつくりと加えながら30秒間この状態を保持
する。この後に基板温度を下げることにより接合
部は、完全に超電導デバイス素子のパツド部と
Gaを介してAl外部端子との接合ができた。この
方法により作製した素子のＶ−Ｉ特性を測定した
結果、良好な特性が得られた。また、動作温度で
ある液体He温度（4.2K）と室温との熱サイクル
に対しても極めてＶ−Ｉ特性の再現性が高く、接
合部の劣化は見られなかつた。また、トンネリン
グ用の酸化膜の作製を、ライトスパツタ後に、
O2ガスを真空室内へ注入し１気圧とした後、基
板温度を50℃に１時間保持する熱酸化法にしても
同様な特性が得られた。また、前述したプロセス
を通して接合部に接合材料としてGa−In合金
〔Ga30at％、In70at％〕を用いても、Gaを用いた
接合と同じ結果を得ることが出来た。第３図に
は、実施例により作製した接合部の断面構造を示
す。 For the bonding method, a commonly used bonding device was used. Ga metal particles are placed on each electrode pad. Since each bonding pad is a through hole, it will not fall off even when the Ga metal particles used as the bonding material are placed on it. All of these operations were performed using vacuum tweezers. On the other hand, as external electrode terminals, counter electrode pads were used which were fabricated by Al vapor deposition using epoxy on the substrate 12. After aligning the pad portion of the superconducting device element and the external electrode pad, the substrate temperature is heated to 40°C, and this state is maintained for 30 seconds while slowly applying a load of 30 g. After this, by lowering the substrate temperature, the bonded part is completely connected to the pad part of the superconducting device element.
A connection with the Al external terminal was made through Ga. As a result of measuring the VI characteristics of the device manufactured by this method, good characteristics were obtained. Furthermore, the reproducibility of the VI characteristic was extremely high even during thermal cycles between the operating temperature of liquid He (4.2 K) and room temperature, and no deterioration of the joint was observed. In addition, the production of the oxide film for tunneling was performed after light sputtering.
Similar characteristics were obtained using a thermal oxidation method in which O 2 gas was injected into the vacuum chamber to create a pressure of 1 atmosphere, and then the substrate temperature was maintained at 50° C. for 1 hour. Further, through the process described above, even when a Ga-In alloy [Ga30at%, In70at%] was used as a bonding material in the bonding portion, the same results as bonding using Ga could be obtained. FIG. 3 shows a cross-sectional structure of a joint made according to an example.
以上のように、本発明の超電導デバイスは接合
材料に毒性がなく且つ接合部の信頼性も高いもの
である。
As described above, in the superconducting device of the present invention, the bonding material is non-toxic and the bonding portion is highly reliable.
第１図は、従来の超電導デバイスのボンデイン
グパツドと外部金属端子間の接合部にHgを用い
た場合の断面構造である。第２図は本発明の超電
導デバイスのボンデイングパツドと外部金属端子
間の接合部にGaあるいは、Ga−In合金系を用い
た場合の断面構造である。第３図は、本発明の一
実施例の断面構造である。
１……基板（Siウエーハ）、２……ベース電極
層のパツド、３……トンネル接合部、４……対向
電極層のパツド、５……絶縁層（SiO）、６……
制御線電極層のパツド、７……保護膜（SiO）、
８……外部電極端子のパツド（Al）、９……ボン
デイングパツド用のスルーホール、１０……接合
部分、１１……絶縁層（熱酸化膜）、１２……外
部電極端用基板（エポキシー）。
FIG. 1 shows a cross-sectional structure of a conventional superconducting device in which Hg is used in the joint between the bonding pad and the external metal terminal. FIG. 2 shows a cross-sectional structure of a superconducting device according to the present invention in which Ga or Ga-In alloy is used for the bonding portion between the bonding pad and the external metal terminal. FIG. 3 is a cross-sectional structure of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Substrate (Si wafer), 2... Pad of base electrode layer, 3... Tunnel junction, 4... Pad of counter electrode layer, 5... Insulating layer (SiO), 6...
Control line electrode layer pad, 7...protective film (SiO),
8... Pad for external electrode terminal (Al), 9... Through hole for bonding pad, 10... Joint part, 11... Insulating layer (thermal oxide film), 12... Substrate for external electrode end (epoxy ).
Claims (1)
接合材料としてGa又はGa−In系合金を用いるこ
とを特徴とする超電導デバイス。1. A superconducting device characterized in that Ga or Ga-In alloy is used as a bonding material for a bonding portion between a superconducting material portion and an external metal terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58197692A JPS5994480A (en) | 1983-10-24 | 1983-10-24 | Superconductive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58197692A JPS5994480A (en) | 1983-10-24 | 1983-10-24 | Superconductive device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5994480A JPS5994480A (en) | 1984-05-31 |
| JPS6329437B2 true JPS6329437B2 (en) | 1988-06-14 |
Family
ID=16378761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58197692A Granted JPS5994480A (en) | 1983-10-24 | 1983-10-24 | Superconductive device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5994480A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2936329B2 (en) * | 1987-05-28 | 1999-08-23 | 京セラ株式会社 | Oxide superconductor with conductive material |
| US11309479B2 (en) * | 2019-12-06 | 2022-04-19 | International Business Machines Corporation | Computing devices containing magnetic Josephson Junctions with embedded magnetic field control element |
-
1983
- 1983-10-24 JP JP58197692A patent/JPS5994480A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5994480A (en) | 1984-05-31 |
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