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JPS633036B2 - - Google Patents
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JPS633036B2 - - Google Patents

Info

Publication number
JPS633036B2
JPS633036B2 JP61014434A JP1443486A JPS633036B2 JP S633036 B2 JPS633036 B2 JP S633036B2 JP 61014434 A JP61014434 A JP 61014434A JP 1443486 A JP1443486 A JP 1443486A JP S633036 B2 JPS633036 B2 JP S633036B2
Authority
JP
Japan
Prior art keywords
gold
plating
cobalt
plated
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP61014434A
Other languages
Japanese (ja)
Other versions
JPS61222143A (en
Inventor
Terukichi Nagashima
Akio Takami
Akyo Kasugai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP61014434A priority Critical patent/JPS61222143A/en
Publication of JPS61222143A publication Critical patent/JPS61222143A/en
Publication of JPS633036B2 publication Critical patent/JPS633036B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/013Manufacture or treatment of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor

Landscapes

  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

[産業上の利用分野] 本発明は金メツキされた電子部品、詳しくは薄
い金メツキ層でも高品質である電子部品とその製
法に関するものである。 [従来の技術および問題点] 金はその優れた物理的性質により、各種の電子
部品に金メツキを施し、広く利用されている。金
はセラミツクにメタライズを施こした電子部品に
用いた場合には、ボンデイング、ろう付、ソルダ
リング等の接続性に良い特性を有しているが、極
めて高価であるためにできるだけメツキ層を薄く
して使用したい。従来よりこのような要望は強か
つたにもかかわらず、実現できなかつた。という
のは薄くすると、下地のNi、Cu、などのメツキ、
またはメタライズ層が緻密質にできないため金メ
ツキ面に拡散したり、Auのピンホールを通して
下地の変質により耐熱変色、シリコンチツプの剥
離、ボンデイング性の劣化、Au/Snシールによ
る蓋付け不良の発生など耐熱性及び接続の性能が
劣つてしまうからである。そこでやむをえず、コ
スト高になるにもかかわらずメツキ層を厚くして
使用していた。 [問題点を解決するための手段及び作用] 本発明者らは、かかる現状を鑑み、薄い金メツ
キ層でも性能劣化が起きない電子部品について鋭
意検討した結果、金メツキの下地として特殊な合
金のメツキを施せばよいことを見出し本発明を完
成した。 すなわち本発明の要旨は、金属面上に金メツキ
が施されたICパツケージのシリコンチツプマウ
ント部に、金メツキの下地としてコバルト2〜60
重量%、残部がニツケルの合金のメツキを施し、
この合金のメツキ上に2μ厚以下の金メツキを施
すことを特徴とする金メツキされた電子部品とそ
の製法にある。 以下に本発明を詳細に説明するに、本発明は金
属面上に金メツキを施した電子部品に関するもの
である。適用できる金属面としては特に制限はな
く、通常の電子部品を構成する金属、例えば銅、
鉄、アルミニウム等で良く、これらのみならずセ
ラミツク基板表面をタングステン、モリブデン等
若しくはこれらの混合物を主体とした材料でメタ
ライジングしたものでも良い。金メツキを施した
電子部品としては、ICパツケージのシリコンチ
ツプマウント部を挙げることができ、Auの機能
としては、電子部品のワイヤボンデイング、チツ
プである。 さて本発明はICパツケージのシリコンチツプ
マウント部において、金メツキの下地としてコバ
ルト2〜60重量%、残部がニツケルの合金のメツ
キを施し、この合金のメツキ上に、2μ厚以下の
金メツキを施すことを特徴とする。合金のメツキ
を施す方法にも制限がなく、電気メツキ、無電解
メツキなどの方法により、厚さ0.1〜10μ、好まし
くは、厚さ0.5〜5μ施される。合金中のコバルト
の含有量は2〜60%(重量%、以下同じ)が好ま
しく、7〜40%が特に好ましい。2%よりも少な
いと耐熱性及び接続性がそれ程向上しない。また
55%よりも多くなると、半田付け性が劣るように
なるし、またコバルトはニツケルと比較すると、
かなり高価であるのでコスト面でも有利ではな
い。なお合金のメツキ後、非酸化雰囲気700℃以
上で処理するとメツキ被膜が緻密となり、またメ
ツキ層の下地との密着性が良好となるので更に好
ましい。 なお本発明者らは、合金メツキ液中でのCo/
Ni比を種々変化させた場合の合金メツキ被膜中
に含まれるCo/Ni比を調べたところ、第1図に
示すようにコバルトはニツケルよりも優先的に析
出することが判つた。そこで合金メツキ被膜中の
Ni/Co比を一定に保つためには、Coの補充が必
要でありその補充液としてはNiとCoを溶液中に
含有ししかも合金メツキ液中のNi/Co比よりも
常に小さいNi/Co比であることが必要である。
そのような補充液を添加しつつ合金のメツキを施
せば、品質の一定したメツキ被膜が得られるので
好ましい。またNi、Coは液以外に陽極からも供
給することができる。 以上のようにして合金のメツキを施したならば
公知の方法で金メツキをする。従来の電子部品に
おけるICパツケージのシリコンチツプマウント
部では、用途によつても異なるが通常2〜4μ厚
に金メツキされている。これに対し本発明では下
地としてコバルト2〜60重量%、残部がニツケル
の合金のメツキを施しているので、従来よりも厚
さを1〜2μ薄くしても同一性能が得られる。す
なわちLSI用セラミツクパツケージでは、下地と
してニツケルメツキを施した場合通常3〜4μ厚
に金メツキしていた。これに対し、本発明では
1.5〜2μ厚に金メツキすれば充分である。金メツ
キ層を薄くしても従来品と変わらぬ性能を得るこ
とができるのは、下地層にコバルトを含んでいる
ので、金への下地層からの拡散、例えば金へのニ
ツケルの拡散が大幅に抑制され、金メツキ層の純
粋性が保たれるからではないかと考えられる。 [発明の効果] このように特許請求の範囲第1項の発明によれ
ば、ICパツケージのシリコンチツプマウント部
は2μ以下の薄い金メツキ層であるにもかかわら
ず、シリコンチツプをAu/Si共晶合金により確
実に固定することができる。また、金メツキは
2μ以下と薄いために、コストを低く抑えること
ができ、極めて実用的なものである。 また、特許請求の範囲第4項の発明によれば、
ニツケルとコバルトを含有するメツキ液に、メツ
キ溶液中のニツケル/コバルト比より小さい比の
ニツケルとコバルトを含有する補充液を添加して
メツキ処理をしているので、品質の一定したメツ
キ被膜が得られる。 [実施例] 以下に本発明を実施例に従い、更に詳細に説明
するが、本発明はその要旨を越えないかぎり以下
の実施例により限定されるものではない。すなわ
ち、金メツキの下地とした合金は、コバルト2〜
60重量%、残部がニツケルとする成分であるが、
その性質を変えない範囲において、Feなどの他
の元素を含有したものも含むものである。 実施例 1 アルミナと樹脂から成形されたグリーンテープ
上にWを主体とするメタライズを印刷し、各グリ
ーンテープを積層焼結して標準的なサイドブレー
ズ型のLSIセラミツクパツケージを製造した。こ
れにワツト浴をベースに硫酸コバルトを添加して
表に記載の種々のNi/Co比のメツキを2μ厚に施
し金メツキの下地とした。次に市販の金メツキ液
(田中貴金属(株)製商品名『Tempelex401』)によ
り金メツキを1.5μ厚に施し種々の特性をそれぞれ
10回評価した。 (テスト方法) (1) ダイアタツチテスト シリコンチツプをN2ガス中450℃でスクライ
ブしながらボンデイングし、ボンデイング後チ
ツプ周辺の90%以上Au/Si共晶合金で漏れて
いるものを合格とした。 (2) エージングテスト ダイボンドしたサンプルをN2ガス中で300℃
にて放置し、0、15、30、50、75、150、200時
間毎にチツプを500gの力で押し、チツプの剥
れがどの時間に発生するか調べた。30時間以上
剥れないものを合格とした。 (3) 高温放置テスト サンプルをi75℃250時間(大気中)放置後、
サビの発生しないものを合格とした。 (結果) 上記(1)〜(3)テストのうち、不合格品の個数及び
発生時間を表に示す。表より明らかなように、ニ
ツケルメツキ中にコバルトを含有すると各テスト
における成績が向上する。 参考例 実施例1においてNi/Co合金中に5%のFeを
含有させて同様にメツキしテストしたところ実施
例1とほぼ同様な結果が得られた。
[Industrial Field of Application] The present invention relates to a gold-plated electronic component, and more particularly to an electronic component that is of high quality even with a thin gold-plated layer, and a method for manufacturing the same. [Prior Art and Problems] Due to its excellent physical properties, gold is widely used in gold plating of various electronic parts. Gold has good properties for bonding, brazing, soldering, etc. when used in electronic parts made of metallized ceramic, but it is extremely expensive, so it is important to keep the plating layer as thin as possible. I want to use it. Although such a demand has been strong for some time, it has not been possible to realize it. This is because when it is thinned, the plating of the underlying Ni, Cu, etc.
Or, because the metallized layer cannot be made dense, it may diffuse onto the gold-plated surface, or pass through pinholes in the Au and cause deterioration of the underlying layer, resulting in heat-resistant discoloration, peeling of silicon chips, deterioration of bonding properties, and poor lid attachment due to Au/Sn seals. This is because heat resistance and connection performance will be inferior. Therefore, we had no choice but to use a thicker plating layer, even though it increased the cost. [Means and effects for solving the problem] In view of the current situation, the inventors of the present invention have conducted intensive studies on electronic components that do not cause performance deterioration even with a thin gold plating layer, and have developed a method using a special alloy as a base for gold plating. They found that it was sufficient to apply plating and completed the present invention. In other words, the gist of the present invention is to apply cobalt 2 to 60% as a base for gold plating to the silicon chip mount portion of an IC package whose metal surface is plated with gold.
Weight%, the balance is nickel alloy plating,
The present invention relates to a gold-plated electronic component and a method for manufacturing the same, characterized in that gold plating with a thickness of 2 μm or less is applied on the plating of this alloy. The present invention will be described in detail below. The present invention relates to an electronic component having a metal surface plated with gold. There are no particular restrictions on the metal surfaces that can be applied, and metals that make up ordinary electronic components, such as copper,
It may be made of iron, aluminum, etc., and in addition to these materials, the surface of the ceramic substrate may be metallized with a material mainly composed of tungsten, molybdenum, etc., or a mixture thereof. Examples of gold-plated electronic components include silicon chip mounts in IC packages, and Au functions include wire bonding and chips for electronic components. Now, in the present invention, the silicon chip mount part of the IC package is plated with an alloy of 2 to 60% by weight of cobalt and the balance is nickel as a base for gold plating, and on top of this alloy plating, gold plating with a thickness of 2μ or less is applied. It is characterized by There are no restrictions on the method of plating the alloy, and the plating is performed to a thickness of 0.1 to 10 μm, preferably 0.5 to 5 μm, by a method such as electroplating or electroless plating. The content of cobalt in the alloy is preferably 2 to 60% (by weight, the same hereinafter), particularly preferably 7 to 40%. If it is less than 2%, heat resistance and connectivity will not improve significantly. Also
If it exceeds 55%, the solderability will be poor, and cobalt will have poor solderability when compared to nickel.
Since it is quite expensive, it is not advantageous in terms of cost. It is more preferable to treat the alloy at 700° C. or higher in a non-oxidizing atmosphere after plating the alloy, since this will result in a dense plating film and good adhesion of the plating layer to the base. In addition, the present inventors have discovered that Co/
When the Co/Ni ratio contained in the alloy plating film was investigated when the Ni ratio was varied, it was found that cobalt was preferentially precipitated over nickel, as shown in Figure 1. Therefore, in the alloy plating film,
In order to keep the Ni/Co ratio constant, it is necessary to replenish Co, and the replenishing solution contains Ni and Co, and the Ni/Co ratio is always smaller than the Ni/Co ratio in the alloy plating solution. It needs to be a ratio.
It is preferable to plate the alloy while adding such a replenisher, since a plated film of constant quality can be obtained. In addition to the liquid, Ni and Co can also be supplied from the anode. Once the alloy has been plated as described above, it is then plated with gold using a known method. The silicon chip mounting portion of an IC package in a conventional electronic component is usually gold plated to a thickness of 2 to 4 microns, although this varies depending on the application. On the other hand, in the present invention, the base material is plated with an alloy of 2 to 60% by weight of cobalt and the remainder is nickel, so the same performance can be obtained even if the thickness is reduced by 1 to 2 microns compared to the conventional method. That is, in ceramic packages for LSIs, when nickel plating is applied as the base, the gold plating is usually 3 to 4 microns thick. In contrast, in the present invention
Gold plating to a thickness of 1.5 to 2 μm is sufficient. The reason why it is possible to obtain the same performance as conventional products even if the gold plating layer is made thinner is because the base layer contains cobalt, which greatly reduces the diffusion of nickel into the gold from the base layer. This is thought to be because the purity of the gold plating layer is maintained. [Effects of the Invention] According to the invention set forth in claim 1, although the silicon chip mounting portion of the IC package is a thin gold plating layer of 2μ or less, it is possible to mount the silicon chip with Au/Si. It can be fixed securely by crystal alloy. Also, gold plating is
Because it is thin, less than 2μ, it is possible to keep costs low, making it extremely practical. Furthermore, according to the invention of claim 4,
Since the plating process is performed by adding a replenisher containing nickel and cobalt at a ratio smaller than the nickel/cobalt ratio in the plating solution to the plating solution containing nickel and cobalt, a plating film of consistent quality can be obtained. It will be done. [Examples] The present invention will be described in more detail below with reference to Examples, but the present invention is not limited to the following Examples unless the gist thereof is exceeded. In other words, the alloy used as the base for gold plating is cobalt 2~
60% by weight, the balance being nickel,
It also includes those containing other elements such as Fe as long as the properties are not changed. Example 1 A metallization mainly consisting of W was printed on a green tape molded from alumina and resin, and each green tape was laminated and sintered to produce a standard side blaze type LSI ceramic package. To this, cobalt sulfate was added to the Wat bath as a base, and plating with various Ni/Co ratios listed in the table was applied to a thickness of 2μ to serve as a base for gold plating. Next, gold plating was applied to a thickness of 1.5μ using a commercially available gold plating liquid (trade name: “Tempelex 401” manufactured by Tanaka Kikinzoku Co., Ltd.), and various properties were determined.
Evaluated 10 times. (Test method) (1) Die attach test A silicon chip was bonded while scribing in N 2 gas at 450°C. After bonding, a chip with leakage of 90% or more of the Au/Si eutectic alloy around the chip was considered to have passed. (2) Aging test The die-bonded sample was heated at 300℃ in N2 gas.
The chips were left to stand for 0, 15, 30, 50, 75, 150, and 200 hours, and the chips were pressed with a force of 500 g to determine at what time the chips peeled off. Those that did not peel off for more than 30 hours were considered acceptable. (3) High temperature storage test After leaving the sample at i75℃ for 250 hours (in the atmosphere),
Those with no rust were considered acceptable. (Results) Among the tests (1) to (3) above, the number and occurrence time of failed products are shown in the table. As is clear from the table, the inclusion of cobalt in the nickel metal improves the performance in each test. Reference Example When a Ni/Co alloy containing 5% Fe was plated and tested in the same manner as in Example 1, almost the same results as in Example 1 were obtained.

【表】【table】

【表】【table】 【図面の簡単な説明】[Brief explanation of the drawing]

第1図は合金メツキ液中でのCo/Ni比を種々
変化させた場合の合金メツキ被膜中に含まれる
Co/Ni比の変化を示すグラフである。
Figure 1 shows the amount of Co/Ni contained in the alloy plating film when the Co/Ni ratio in the alloy plating solution was varied.
It is a graph showing changes in Co/Ni ratio.

Claims (1)

【特許請求の範囲】 1 金属面上に金メツキが施されたICパツケー
ジのシリコンチツプマウント部に、金メツキの下
地としてコバルト2〜60重量%、残部がニツケル
の合金のメツキを施し、この合金のメツキ上に
2μ厚以下の金メツキを施すことを特徴とする金
メツキされた電子部品。 2 金属面が、セラミツク基板表面をメタライジ
ングしたものである特許請求の範囲第1項に記載
の金メツキされた電子部品。 3 合金が、コバルト7〜40重量%、残部がニツ
ケルである特許請求の範囲第1項ないし第2項の
いずれかに記載の金メツキされた電子部品。 4 金属面上に金メツキが施されたICパツケー
ジのシリコンチツプマウント部を製造するに際
し、ニツケルとコバルトを含有するメツキ液に、
メツキ液中のニツケル/コバルト比より小さい比
のニツケルとコバルトを含有する補充液を添加し
つつ、金属面上にコバルト2〜60重量%、残部が
ニツケルの合金のメツキを金メツキの下地として
施すことを特徴とする金メツキされた電子部品の
製法。 5 合金のメツキ後に、700℃以上の非酸化雰囲
気で処理する特許請求の範囲第4項記載の金メツ
キされた電子部品の製法。
[Scope of Claims] 1. The silicon chip mount part of the IC package, which has been plated with gold on the metal surface, is plated with an alloy of 2 to 60% by weight of cobalt and the balance of nickel as a base for the gold plating. on top of
A gold-plated electronic component characterized by applying gold plating with a thickness of 2μ or less. 2. The gold-plated electronic component according to claim 1, wherein the metal surface is obtained by metallizing the surface of a ceramic substrate. 3. The gold-plated electronic component according to claim 1, wherein the alloy contains 7 to 40% by weight of cobalt and the balance is nickel. 4. When manufacturing the silicon chip mount part of an IC package with gold plating on the metal surface, a plating solution containing nickel and cobalt is used.
While adding a replenisher containing nickel and cobalt at a ratio smaller than the nickel/cobalt ratio in the plating solution, plating an alloy of 2 to 60% by weight cobalt and the balance nickel is applied to the metal surface as a base for gold plating. A manufacturing method for gold-plated electronic parts, which is characterized by: 5. The method for producing gold-plated electronic components according to claim 4, which comprises treating in a non-oxidizing atmosphere at 700° C. or higher after plating the alloy.
JP61014434A 1986-01-25 1986-01-25 Electronic part plated with gold and manufacture thereof Granted JPS61222143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61014434A JPS61222143A (en) 1986-01-25 1986-01-25 Electronic part plated with gold and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61014434A JPS61222143A (en) 1986-01-25 1986-01-25 Electronic part plated with gold and manufacture thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP53108976A Division JPS6013078B2 (en) 1978-09-05 1978-09-05 Gold-plated electronic components and their manufacturing method

Publications (2)

Publication Number Publication Date
JPS61222143A JPS61222143A (en) 1986-10-02
JPS633036B2 true JPS633036B2 (en) 1988-01-21

Family

ID=11860911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61014434A Granted JPS61222143A (en) 1986-01-25 1986-01-25 Electronic part plated with gold and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS61222143A (en)

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* Cited by examiner, † Cited by third party
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TW200943330A (en) * 2008-03-06 2009-10-16 Ceramtec Ag Metallized coil bodies (inductor) having high q-value
CN103887183B (en) * 2012-12-21 2017-09-12 华为技术有限公司 Gold/gold/silicon eutectic die welding method and transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54145476A (en) * 1978-05-06 1979-11-13 Toshiba Corp Package for semiconductor
JPS6013078B2 (en) * 1978-09-05 1985-04-04 日本特殊陶業株式会社 Gold-plated electronic components and their manufacturing method

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JPS61222143A (en) 1986-10-02

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