JPS6330806B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an FM demodulation circuit suitable for integrated circuits that can accurately demodulate when a frequency modulation signal (hereinafter referred to as FM signal) arrives and at the same time easily vary the demodulation output level. It is.

Conventionally, demodulation methods such as the pulse count detection method, PLL detection method, and quadretcher detection method have been used as FM demodulation circuits, but among these, the pulse count detection method has the advantage that the obtained demodulated signal has a low distortion rate, and It is often used in integrated circuits because it has the advantage of a simple circuit configuration and no adjustment.

An FM demodulation circuit using a pulse count detection method, which has been commonly used in the past, will be explained with reference to FIGS. 1 and 2.

By inputting the FM signal to the limiter amplifier 1, a limiter FM signal 5 (FIG. 2a) is obtained. This FM signal 5 is input to the differentiating circuit 2, and a trigger signal 6 (Fig. 2b) is generated at the rising and falling edges of the FM signal 5. This trigger signal 6 drives the monostable multi-circuit 3 in the next stage. This monostable multi-circuit output signal 7 generates a pulse with a constant pulse width synchronized with the trigger signal 6.
(FIG. 2c) is integrated by the integrating circuit 4 to obtain the demodulated signal 8 (FIG. 2d). When changing the demodulated output level in this pulse count detection method, one possible method is to change the division ratio by dividing the demodulated signal 8 by resistors. However, the audio FM signals in current FM radio broadcasts and TV broadcasts are pre-emphasized to emphasize high frequencies to improve the S/N ratio.
De-emphasis is required on the receiver side to correct the demodulated signal to suppress high frequencies. For this reason, at present, the time constant of the integrating circuit is made to be the same as the de-emphasis time constant so that the integrating circuit functions as a de-emphasis circuit. Therefore, in order to vary the demodulated output level by resistor division at the output of the integrating circuit, the output must be output via a buffer amplifier or variable gain amplifier after the integrating circuit, otherwise the time constant of the de-emphasis described above will change. , it is not an appropriate method.

An optimal method would be to vary the demodulated output level by varying the pulses generated by the monostable multicircuit 3, which would eliminate the above problem. There are two ways to change the transmission energy of the pulses generated by the monostable multicircuit 3, by changing the pulse width or the amplitude level of the pulses.
When changing the amplitude level of the pulse, the variable level is limited by the power supply level used and is also affected by power supply ripples, so the pulse width is changed as shown by the dotted line in Figure 2c. Figure d
A method that changes the demodulation output as shown in the following is suitable.

The method shown in FIG. 3 is used as one method for changing the pulse width. The difference between Fig. 1 and Fig. 3 is that the capacitors used in the circuit from the output of the limiter amplifier 1 to the integration circuit 4 are
In the method shown in FIG. 1, at least two differentiating circuits 2 and a simple multi-circuit 3 are required, but in the method shown in FIG. Only one piece is enough.
It is certain that the number of capacitors can be reduced compared to FIG. 1, making it effective for integrated circuits, and can be achieved with just one capacitor and this external terminal.

The operating principle in Figure 3 is the FM of limiter amplifier 1.
The signal 13 obtained by applying the signal 5 to the delay circuit at the resistor 10 and the capacitor 11 (Fig. 4b) and the regular FM
The comparator 9 compares the signal 5 (FIG. 4 a) with the signal 5 (FIG. 4 a), and the difference (delay) 14 (FIG. 4 c) is passed through the waveform shaping circuit 12 to the monostable multi-circuit output signal 7 shown in FIG. Integrating circuit 4 obtains a pulse signal of
It is given to This waveform shaping circuit 12 is an amplifier and does not change the pulse width.
In this method, the delay time is due to the charging and discharging of the capacitor 11 through the resistor 10.
is determined by the capacitor 11. Therefore, when changing the pulse width, it is convenient to change the resistance 10. However, when the system shown in FIG. 3 is constructed using an integrated circuit, it becomes necessary to attach the delay elements 10 and 11 externally, and therefore at least two external terminals are required in this part.

The purpose of the present invention is to configure the system from the output of the limiter Amp1 to the input of the integrator circuit 4 with one capacitor, which is an advantage of the method shown in FIG. The present invention provides a demodulator that is suitable for integrated circuits and has a reduced number of external elements and terminals.

According to the present invention, the first and second channels alternately generate a predetermined current according to a frequency demodulated input signal.
A current source, a capacitive element whose charging current is the current from the first current source and a discharging current from the second current source, and the voltage of this capacitive element is compared with two different reference voltages. a circuit unit for controlling the operating states of the first and second current sources; a circuit unit for combining currents from the first and second current sources and generating an output according to the combined output; A conversion circuit is provided which includes an integrating means for integrating an output and converts a frequency-modulated input signal into a voltage amplitude corresponding to the degree of modulation.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 5 shows a configuration block diagram for explaining the operating principle of the present invention. FIG. 6 shows the input/output signal waveforms of each part when the resistor 15 of the resistor 15 and capacitor 16, which are time constant elements in FIG. 5, is shorted, that is, the resistance value R=0.

The input FM signal e ₁ is limiter amplified by the limiter amplifier 1 and applied to the first constant current source 17 and the second constant current source 18 . The first constant current source 17 and the second constant current source 18 alternately supply currents i ₁ and i ₂ to the series circuit of the resistor 15 and capacitor 16, respectively, in synchronization with the input FM signal e ₁ . Operate. However, the current i ₁ is connected to the capacitor 16 as shown in FIG.
flows in the charging direction, and current _i2 flows in the opposite direction as a discharging current. The series circuit of these resistors 15 and capacitors 16 has two levels: high level and low level.
A Schmitt trigger circuit 19 having two reference voltages is connected, and the output of the Schmitt trigger circuit 19 further controls conduction between the first constant current source 17 and the second constant current source 18.

First, when the first constant current source 17 starts to flow the current i 1 in the positive half cycle of the input signal e ₁ shown in FIG. 6a, the capacitor ₁₆ is charged over time and the voltage shown in FIG. As the charging voltage e ₂ increases. When the charged voltage e ₂ reaches the high level threshold of the Schmitt trigger circuit 19, the output of the Schmitt trigger circuit 19 stops conducting the first constant current source 17, so that the current i ₁ no longer flows. At this time, the second constant current source 18, which has not been operating up to now, is made conductive by the output of the Schmitt trigger circuit 19. Therefore, the input signal e ₁
The voltage _e2 charged in the capacitor 16 is maintained at the high level until the end of the positive half cycle.

Next, when a negative half cycle of the input signal e ₁ is applied and the second constant current source 18 starts flowing current i ₂ , the charge in the capacitor 16 is discharged over time.
The voltage e ₂ drops as shown in FIG. 6b. When the voltage e ₂ reaches the low level threshold of the Schmitt trigger circuit 19 due to discharge, the output of the Schmitt trigger circuit 19 stops the conduction of the second constant current source 18, and the current i ₂ stops flowing. The voltage of the capacitor 16 is kept at a low level until the end of the negative half cycle of the input signal e ₁ , and charging is performed by the current i ₁ at the start of the next positive half cycle. In this way, a trapezoidal wave e ₂ is formed as an input signal to the Schmitt trigger circuit 19 by repeating charging, high level holding, discharging, and low level holding.

At this time, as shown in FIG. 6c and d, the current i ₁
The current is supplied in a pulsed manner during the charging period of the trapezoidal wave _e2 , and the current _i2 corresponds to the discharging period. The charging period and discharging period corresponding to this pulse width are determined by the respective peak current values I ₁ and I ₂ and the capacitance value C of the capacitor 16.
and the reference voltage difference between high level and low level V
CV/I ₁ and CV/I ₂ , respectively. This pulse width is naturally set to be smaller than the minimum half-cycle value of the input signal e ₁ , and the peak current values I ₁ and I ₂ are usually selected to be equal. If this current i ₁ or i ₂ is shaped and extracted as a voltage and integrated, it becomes so-called pulse count detection. In FIG. 5, the first constant current source 17 and the second constant current source 18 Currents equal to the currents i ₁ and i ₂ are respectively taken out from , added to the adder circuit 20 , synthesized and shaped into a pulse voltage, and passed through the integrator circuit 4 .
The output is FM demodulation.

In this way, when operating with only the capacitor 16, the pulse width is given by CV/I ₁ , so by changing the capacitance value C, the pulse width, i.e.
FM demodulation output level is variable. However, making the capacitance value C variable is not desirable in practice since it causes problems such as increased cost. Therefore, a case will be described with reference to FIG. 7 in which the pulse width is made variable by inserting the resistor 15 shown in FIG. 5 and changing the resistance value R.

In FIG. 7, the trapezoidal wave e ₂ in FIG. 6b causes a voltage shift due to the presence of the resistor 15, and becomes a modified trapezoidal wave e _2R . When the current i ₁ is supplied, the capacitor 16 is charged and at the same time a voltage drop I ₁ R occurs across the resistor 15, which is added to the charging waveform.
Then, when the constant current I ₁ disappears and the holding state is reached,
The voltage drop I ₁ R naturally disappears, leaving only the charging voltage to the capacitor 16, and the voltage drop I ₁ R decreases from the above-mentioned high level.
is maintained at a reduced voltage. Next, when the constant current I ₂ flows, a voltage drop I ₂ R occurs across the resistor 15, and this is added to the discharge waveform. and,
The result is a modified trapezoidal wave _{e 2R shown} in FIG. 7, which is held at a voltage that is increased by I 2 R from the low level. The charging period and discharging period in this case are given by C/I ₁ (V-I ₁ R - I ₂ R) and C/I ₂ (V-I ₁ R-I ₂ R), respectively, and I ₁ = I ₂ , both become CV/I ₁ −2CR. This indicates that the charging and discharging pulse widths can be adjusted by changing the resistance value R of the resistor 15. As described above, the pulse width is made variable by inserting a resistor in the constant current charging/discharging switching and generating a trapezoidal wave in which the reference voltage difference V is equivalently reduced. Therefore, this variable amount is determined by the product of the resistance value R and the capacitance value C, and can be set independently of the values of the constant current _I1 and the reference potential difference V.

FIG. 8 shows a specific embodiment of the present invention. Supply voltage is applied to terminal 30, and terminal 3
1 is given a stabilized bias voltage. An input signal _e1 amplified by a limiter is applied to the input terminal 35 of a differential amplifier composed of transistors 32, 33 and a current source 34, and is connected to a current mirror 36 connected to the collector of the transistor 32 and the collector of the transistor 33. current mirror 37
A current that alternately switches in synchronization with the input signal is supplied to the input signal. The current mirror 36 corresponds to the first constant current source 17 in FIG. The current mirror 37 constitutes a second constant current source 18 with transistors 38 and 39, and operates to cause a discharge current to flow. A differential amplifier composed of transistors 40, 41 and a current source 42 constitutes a Schmitt trigger circuit 19 together with a current mirror 43, a transistor 44, and resistors 45, 46, and 47, and is set to a high level by a bias voltage applied to the base of the transistor 41. Two low level reference voltages are set. The charging current from the current mirror 36 increases the base voltage of the transistor 40,
When the voltage reaches a high level, which is the base voltage of the transistor 41, the transistor 40 becomes conductive, causing current to flow through the current mirror 48 connected to the collector. The output of current mirror 48 is connected to the collector of transistor 32 and supplies collector current, so current mirror 36 is cut off and future charging current i ₁ is stopped. At this time, the base voltage of the transistor 41 of the Schmitt trigger circuit is also switched to a low level. Charging and discharging are not performed until a discharge current flows through the current mirror 37 in the next half cycle of the input signal, and the battery is in a holding state. current mirror 3
7 causes a discharge current to flow through the transistor 39,
When the base voltage of the transistor 40 is lowered and the voltage reaches a low level, the transistor 41 becomes conductive, and the current mirror 4 connected to the collector
3,49. current mirror 49
The output of the transistor 33 is connected to the collector of the transistor 33, and supplies a collector current, so the current mirror 37 is cut off and the discharge current stops. At the same time, due to the conduction of the current mirror 43, the base voltage of the transistor 41 is also switched to a high level.

As described above, the modified trapezoidal wave e _2R explained in FIG. 7 is generated at the base of the transistor 40.
Current mirrors 36, 37 and transistor 3
If the current transfer ratio of 8 and 39 is 1, the charging current will be equal to the current supplied from the current source 34. Further, in order to cut off the current mirrors 36 and 37, the output currents of the current mirrors 48 and 49 are set so that a value sufficiently larger than the current of the current mirrors 36 and 37 flows.

The current mirrors 36 and 37 each have an output terminal for taking out a current equal to the charging/discharging current, which are connected to a resistor 50 to be combined, and added to the base of a transistor 51 for switching to take out a shaped pulse output. The collector of the transistor 51 is connected to the bias voltage terminal 31 via a resistor 52, and a pulse output whose amplitude is given by the bias voltage and whose pulse width corresponds to the charging/discharging period is obtained from the output terminal 53.

As described above, the FM demodulation circuit according to the present invention is an FM demodulation circuit that can vary the output level without affecting the characteristics with only one terminal and a series circuit of a capacitor and a resistor, which is particularly advantageous when integrated into an integrated circuit, and has a low distortion rate. can be realized.

Although the present invention has been described above as an FM demodulation circuit, it goes without saying that the present invention is not limited to the FM demodulation circuit, and can also be applied to other application circuits such as frequency-voltage conversion circuits. Further, although the embodiment has been described in which the constant current I ₁ =I ₂ , the two do not necessarily have to be equal.

[Brief explanation of the drawing]

Figure 1 is a block configuration diagram of the conventionally used pulse count detection method, Figure 2 is a signal waveform diagram at each part of Figure 1, and Figure 3 is a block diagram of an improved version of the pulse count detection method. 4 is a signal waveform diagram at each part of FIG. 3, FIG. 5 is a block diagram showing the basic configuration of the present invention, FIG. 6 is a signal waveform diagram when the resistor 15 in FIG. 5 is 0, and FIG. FIG. 5 is a signal waveform diagram when the resistor 15 has a finite value, and FIG. 8 is a circuit diagram showing an example of a specific circuit configuration of the present invention. 1... Limiter Amp, 2... Differential circuit, 3...
... Monostable multi, 4... Integrating circuit, 5... Limiter Amp output, 6... Differentiating circuit output, 7... Monostable multi, 8... Integrating circuit output, 9... Comparator, 10... Variable resistor, 11... Capacitor,
12...Waveform shaping, 13...Delay circuit output, 14
... Comparator output, 15 ... Variable resistor, 16
... Capacitor, 17 ... First constant current source, 18
... second constant current source, 19 ... Schmitt trigger circuit, 20 ... addition circuit, i ₁ ... current from first constant current source, I ₁ ... peak current value of i ₁ , i ₂ ... Current from the second constant current source, I ₂ ... peak current value of i ₂ , V ... high level of Schmitt trigger circuit,
Low level reference voltage difference.

Claims (1)

[Claims] 1. A first and second current source that alternately generates a predetermined current according to a frequency-modulated input signal, and the current from the first current source is used as a charging current and the current from the second current source is discharged. a capacitive element that generates a current; circuit means that compares the voltage from the capacitive element with two different reference voltages to control conduction states of the first and second current sources; A circuit section that synthesizes currents from sources and generates an output according to the synthesized output, and an integrating means that integrates the output of the circuit section, the frequency modulated input signal is adjusted according to the frequency modulation. A conversion circuit characterized by converting into voltage amplitude.