JPS6330830B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a vertical synchronization signal detection circuit for detecting a vertical synchronization signal of a television signal.

<Summary of the Invention> Conventionally, automatic channel selection devices that automatically perform channel selection operations on television receivers have been proposed and some have been put into practical use. The present invention provides a vertical synchronization signal detection circuit suitable for use in the present invention.

<Prior art> Conventionally, this type of signal discrimination circuit detects a vertical synchronization signal from a received signal in order to reliably receive a television signal that arrives mixed with various interferences and noises.
The number of synchronization signals is counted to determine whether the signal is a regular television signal or not.

<Problems to be Solved by the Invention> However, such a signal discrimination circuit has the disadvantage that when a vertical synchronization signal with a sag is supplied, the synchronization signal may not be detected, causing the automatic channel selection device to malfunction. Note that this sag refers to the case where waveform distortion occurs in the synchronization signal part (especially the vertical synchronization signal) in the composite video signal, and this is caused by an abnormality in the transmission system or repeater, or if the video amplification characteristics in the receiver are poor. occurs in

An object of the present invention is to provide a vertical synchronization signal detection circuit that can reliably detect a vertical synchronization signal even when there is such a sag.

<Means for Solving the Problems> Therefore, the present invention synchronously detects a synchronous signal obtained from a synchronous separator circuit with a flyback pulse in a synchronous detection circuit, adds this detection output to a synchronous amplifier circuit, and vertically detects a synchronous signal obtained from a synchronous separator circuit with a flyback pulse. This is to obtain a synchronization signal.

<Example> The present invention will be described below according to an example shown in the drawings.

FIG. 1 shows a circuit configuration diagram of an embodiment of the present invention, where 1 represents transistors Q ₁ to Q ₃ , resistors R ₁ to _{R 9} ,
It is a normal synchronous separation circuit consisting of capacitors C ₁ and C ₂ , 2 is a waveform shaping circuit consisting of resistors R ₁₀ and R ₁₁ and capacitors C ₃ and C ₄ , and 3 is a transistor Q ₄ and Q ₅ and a resistor. _R12 ~ _R16 , capacitor _C5
and a synchronous detection circuit consisting of a diode _D1 , 4 a transistor _Q6 , resistors _R17 , _R18 , and a capacitor.
This is a synchronous amplifier circuit consisting of C _6. When a composite video signal is supplied to the input terminal T ₁ here, only the horizontal and vertical synchronous signals are amplitude-separated and derived from this video signal in the synchronous separation circuit 1, and this is the waveform. The horizontal synchronizing signal is passed through the shaping circuit 2, delayed slightly so that it matches the phase of the flyback pulse, and then supplied to the base of the transistor _Q4 of the synchronous detection circuit 3, where the flyback signal is supplied to the input terminal _T2. It is synchronously detected with the pulse, and this detection output is supplied to the synchronous amplifier circuit 4, where it is synchronously amplified and sent to the output terminal.
The vertical synchronization signal is extracted from _T3 .

To describe the operation of each of the above circuits in more detail with waveform diagrams, Fig. 2a shows the waveform during the vertical retrace period in a normal composite video signal without sag, and Fig. 4a shows the waveform during the same period when there is sag. The waveform of is shown.

Now, the _second
When a sag-free composite video signal as shown in Figure a is supplied, horizontal and vertical synchronizing signal components are separated in the synchronization separation circuit 1, and a negative polarity signal as shown in Figure 2b is sent to the collector of transistor _Q3 . A synchronization signal is derived. This synchronization signal is used by the waveform shaping circuit 2.
After being waveform-shaped with a slight delay through the synchronous detection circuit 3, the signal is applied to the base of the transistor _Q4 of the synchronous detection circuit 3. On the other hand, a positive flyback pulse as shown in Fig. _2c is applied to the input terminal T2.
Transistor through resistor R ₁₆ and diode D ₁
The phase of the positive flyback pulse applied to the emitter of transistor Q ₄ matches the phase of the negative horizontal synchronization pulse applied to the base of transistor Q ₄ , and the potential on the emitter side of transistor Q _{4 matches the phase of the negative polarity horizontal synchronizing pulse applied to the base of transistor Q 4} . Transistor Q ₄ and diode D ₁ are conductive only during the period when they are at a higher potential than the side, and accordingly capacitor C ₅ is charged. During other periods, the diode D ₁ and the transistor Q ₄ are cut off, and the charge in the capacitor C ₅ is discharged through the resistor R ₁₂ , resulting in the emitter follower output of the transistor Q ₅ in FIGS. 2d and 3. An output waveform as shown in a is obtained. Note that the waveform in FIG. 3a is shown by compressing the waveform in FIG. 2d on the time axis, and is substantially the same waveform. As can be seen from this waveform, during period 3H of the vertical synchronization signal, the horizontal synchronization signal part has the same polarity as the flyback pulse, so even if both phases match, transistor _Q4 is not conductive during this period, and the slave Therefore, the charge in capacitor _C5 continues to be discharged with a constant discharge time constant determined by resistor _R12 and capacitor _C5 , and at this time, the detected output voltage obtained at the emitter of transistor _Q5 is as shown in the figure. A depression is created.
During the subsequent equivalent pulse period, whenever the phases of the horizontal synchronizing pulse and the flyback pulse match, transistor _Q4 is turned on again and the capacitor is turned on each time.
_C5 is charged, but since this charging period is short and the charging current associated with one charging operation is limited,
The charging voltage of capacitor _C5 does not recover all at once, but returns to a steady value through repeated charging and discharging. As a result of this, the output of the synchronous detection circuit 3 is as shown in FIG.
An output waveform as shown in FIG. 3a is obtained. The detected output thus obtained is supplied to the synchronous amplifier circuit 4, and the transistor Q ₆ is turned on at a level below the level shown by the dashed line in _FIG . I get a signal.

At this time, the third signal obtained from the synchronous detection circuit 3
The detection output shown in figure a is connected to diode D ₂ , resistor R ₁₉ ,
Capacitor C ₇ rectifies and smoothes other circuits, e.g. horizontal
It may also be used for AFC circuits, etc.

On the other hand, when a synthesized video signal with a sag as shown in _FIG . 4
An output as shown in FIG. b is obtained, and at this time, the vertical synchronization signal for 3H is missing. Furthermore, the fourth
If the bias level shown by the dashed line in FIG. However, the fourth
When the synchronous signal shown in Figure b is supplied to the synchronous detection circuit 3 via the waveform shaping circuit 2, where it is synchronously detected with the flyback pulse supplied to the input terminal _T2 , this detection output is free from the sag mentioned above. An output waveform as shown in Fig. 2d is obtained, which is the same as in the case, and therefore, regardless of the presence or absence of sag, the output waveform from output terminal _T3 is
A vertical synchronization signal as shown in Figure b is obtained.

The values of the resistors, capacitors, etc. used in the embodiment shown in FIG. 1 above are illustrated below for reference.

+B ₁ …15 volts, +B ₂ …5 volts, R ₁₀ …5.6KΩ, R ₁₁ …10KΩ, R ₁₂ …390KΩ, C ₃ …470PF, C ₄ …0.0047μF, C ₅ …0.001μF, C ₆ …0.022μF <Effects of the Invention> According to the vertical synchronization signal detection circuit of the present invention, the synchronization signal obtained from the synchronization separation circuit as described above is detected synchronously with the flyback pulse, and this detection output is added to the synchronization amplifier circuit to detect the vertical synchronization signal. Since the signal is obtained, the vertical synchronization signal can be reliably detected even when a composite video signal with sag due to transmission distortion etc. is received.

Therefore, if the vertical synchronization signal detection circuit of the present invention is used in the signal discrimination circuit of an automatic tuning device and the number of vertical synchronization signals obtained from this detection circuit is counted, the automatic tuning device will not malfunction. It disappears.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of an embodiment of the present invention;
4 through 4 are signal waveform diagrams for explaining the operation of the same embodiment. 1...Synchronization separation circuit, 2...Waveform shaping circuit, 3
...Horizontal synchronous detection circuit, 4...Synchronous amplifier circuit,
Q ₁ to Q ₆ ……transistor, R ₁₂ ……discharge resistor,
C ₅ ... Charging capacitor.

Claims (1)

[Claims] 1 When a composite video signal without sag is input,
The reference bias level is set to separate the horizontal and vertical synchronization signal components in the composite video signal, and to separate only the horizontal synchronization signal component where the vertical synchronization signal component is missing when a composite video signal with sag is input. a waveform shaping circuit for shaping the horizontal and vertical synchronizing signals obtained from the synchronization separation circuit, at least one transistor, a charging capacitor, and a discharging resistor; The horizontal and vertical synchronizing signals obtained from the waveform shaping circuit are applied, and a flyback pulse having a polarity opposite to that of the horizontal and vertical synchronizing signals is applied to the emitter, and when the horizontal synchronizing signal and the flyback pulse match in phase, the transistor conduction to charge the capacitor connected to the collector and obtain a synchronous detection output based on the charging voltage of this capacitor; A vertical synchronization signal detection circuit comprising: a synchronization amplifier circuit that conducts a transistor to obtain a vertical synchronization signal from a collector when a predetermined level is exceeded.