JPS6331101B2 - - Google Patents

Abstract

PURPOSE:To contrive to reduce the maximum conduction resistance by a method wherein metallic wiring layers are provided (=side surface metallize) on the wall surface of a recess called a cavity and further connected to the second metallic wiring layer. CONSTITUTION:The electrode of a semiconductor element 1 and the first metallic wiring layers 2 are connected by Al wires, after the semiconductor element 1 is fixed on the metal surface (=island) 8 plated by Au at the bottom of the cavity 7 with the eutectic alloy of Au/Si. It is power source pins and earth pins that are restricted in the value of conduction resitance. The power source and the earth are surface-metallized on a semi-circular cutout 12 and connected to the second metallic wiring layers 5, resulting in the reduction of conduction resistance. The second metallic wiring layers are used only for the power source and the earth, and accordingly each can be formed wider than the wiring width of the first layers. Therefore, the wiring resistance of the power source and the earth can be reduced at least to less than 1/2, normally 1/4-1/5. After finishing in connection of all the wires, a sealing ring 9 is covered with a metallic cap and sealed by a seam welding method or Au/Sn alloying method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to ceramic substrates, and particularly to ceramic substrates used in semiconductor devices.

2. Description of the Related Art In recent years, semiconductor devices, especially those used in computers, are required to have high calculation speeds, and as a result, semiconductor devices have become highly integrated. However, higher integration of semiconductor devices means an increase in the number of input/output pins, and accordingly, the dimensions of ceramic substrates on which semiconductor elements are mounted have also become larger. The enlargement of the ceramic substrate is
As a result, the conduction resistance between the semiconductor element and the external lead pin increases, and the resulting potential shift becomes a cause of operational malfunction.

In order to solve this kind of problem, conventionally, as shown in Figure 1, two metal wiring layers were connected using through holes drilled in the ceramic substrate and external lead pins.
By placing two metal wiring layers in parallel, the conduction resistance was reduced.

That is, the electrodes of the semiconductor element 1 provided in the cavity 7 and the first metal wiring layer 2 are made of aluminum (Al).
In addition to setting a current path to the external lead pin 4 by connecting with a wire 3 whose main component is gold (Au), a metal wiring layer 5 is also provided in the second layer to connect the first and second metals. We have attempted to reduce the conduction resistance by connecting the wiring layers with through holes 6 and parallelizing the current paths.

However, in this conventional method, the portion of the first metal wiring layer where the wire is connected (= bonding
Because the wiring is so dense that there is no space to drill through holes in bonding pads, the bonding pads are usually drilled outside the bonding pad, which shortens the length of the two metal wiring layers in parallel, which increases the conduction resistance. There was a drawback that the reduction was not sufficient.

A feature of the present invention is that a first metal wiring layer is provided on the upper surface of the upper ceramic layer having openings, a second metal wiring layer is provided on the upper surface of the lower ceramic layer, and the upper and lower ceramic layers are connected to each other. By integrating, the opening in the upper ceramic layer and the lower ceramic layer below it form a recess, and the second metal wiring layer extends to the center of the opening. In the ceramic substrate in which the first metal wiring layer and the second metal wiring layer are both connected to the same external lead pin, the first metal wiring layer is connected to the first metal wiring layer in the vicinity of the opening. and branching into a second tip;
The tip of the hole is used as a bonding pad for bonding a metal wire, and the second tip is connected to the second metal wiring layer through a metallized layer formed in a notch provided on the wall of the opening. It is on a ceramic substrate. Here, the above-mentioned notch is created by providing a through hole in the ceramic sheet before firing, pouring a liquid in which metal particles are dispersed into the through hole, and then cutting a part of the through hole to metallize the side surface. By overlapping this sheet with another ceramic sheet and firing it, a ceramic substrate whose side surfaces are metallized can be obtained.

The present invention will be explained in detail below. FIG. 2 shows a typical embodiment of the present invention in a perspective view. As in the conventional method, the semiconductor element 1 is fixed onto the gold (Au)-plated metal surface (=island) 8 at the bottom of the cavity 7 using an Au/Si eutectic alloy, and then the semiconductor element 1 is assembled. an electrode (not shown) and a first
is connected to the metal wiring layer 2 by an aluminum wire. In a semiconductor device, the values of conduction resistance are most restricted at power supply pins and ground pins. Therefore, in this example, the signal input/output wiring is formed using only one layer as before, but the power supply and grounding are formed by metallizing the sides of the semicircular notch 12 as shown in the figure, and then using a second metal layer. It is connected to the wiring layer 5 to reduce conduction resistance. Since the second metal wiring layer is only for power supply and grounding, each metal wiring layer can be formed to have a wider wiring width than the first layer. Therefore, the wiring resistance for power supply and grounding is at least 1/2 or less, usually 1/4 to 1/2
It is possible to lower it to 5. In the present invention, as shown in the upper right corner of FIG. 2, the first metal wiring layer 2 is branched into a first tip 2' and a second tip 2''.The first tip 2' Wire bonding is applied to the second tip 2'', while the second tip 2'' is grounded to the second metal wiring layer 5 through the side metallization of the notch 12. In this way, the first tip can be brought closer to the semiconductor element regardless of the presence of the notch, so the wire can be shortened and the conduction resistance can be reduced accordingly. After all the wires have been connected, the seal ring 9 is covered with a metal cap and sealed by a seam weld method, an Au/Sn alloy method, or the like.

Next, a method of metalizing the side surface of the notch will be explained using FIG. 3.

Ceramic substrates that have one or more layers of metal wiring inside are usually made by kneading fine particles of alumina Al ₂ O ₃ with a binder into an elastic sheet (= green sheet), which is then drilled and metal wiring is applied. It is then made by stacking several green sheets together and firing them. The side surface metallization on the cutout portion of the present invention is formed as follows.

First, as shown in FIG. 3a, a desired metal wiring pattern is formed on a green sheet 10 with a thickness of about 0.5 mm by screen printing. The ink used for printing is usually a liquid in which fine particles of tungsten W are dispersed. Next, as shown in FIG. 3b, through holes 11 and 11' having a diameter of about 200 μm are opened. The order of the above printing process and hole punching process may be reversed. Furthermore, as shown in FIG. 3c, ink is dropped onto the through holes 11 and 11',
Apply ink to the wall inside the through hole by suction from the back side. Next, as shown in FIG. 3d, when holes that will later become cavities are punched out, including parts of the through holes 11 and 11', the through holes 11 and 11' become notches 12, and there A metalized pattern is obtained. Furthermore, another green sheet 1
0b and 10b are overlapped as shown in Fig. 3e, cut into an appropriate shape, printed with ink on the outer circumferential side and fired, a notch 12 as shown in Fig. 3f is formed.
A ceramic substrate with metallized sides is produced. After this, nickel plating is performed as usual, the external lead pin and seal ring are brazed, and then nickel (Ni) and gold (Au) plating is applied.

Although the description has been made using a typical example, the metal wiring pattern, the form of the ceramic substrate, the materials used, the method of assembling the semiconductor device, etc. are not limited to this example.

Moreover, although the shape of the notch is explained as being semicircular in the above example, it goes without saying that it can be made in a rectangular, V-shaped, oval, or any other arbitrary shape.

Furthermore, the format of ceramic substrates is not only dual inline (DIP), but also plug-in (also known as area array), flat, QIP (Quadle-inline Package), and single inline. Of course, the present invention is applicable to any shape.

In addition, the materials used are ceramic and alumina.
It is possible to use not only Al ₂ O ₃ but also beryllia BeO, silicon carbide SiC, etc. as the main ingredients, and various external lead pins, seal rings, caps, and metal wiring materials can also be used.

Furthermore, as for the assembly method, not only can similar results be obtained by using the TAB method instead of the wire bonding method described above, but also because the conduction resistance of the leads connected to the semiconductor element is small, the overall conduction resistance is lower. can be lowered even further.

As described in detail above, according to the present invention, not only can the conduction resistance of the metal wiring of a ceramic substrate be significantly reduced, but also the ceramic substrate can be manufactured easily and with a high yield.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional ceramic substrate, Figure 2 is a cross-sectional view of a conventional ceramic substrate.
The figure is a perspective view showing an embodiment of the invention, and FIG. 3 is a sectional view showing the manufacturing method of the invention. In the figure, 1... Semiconductor element, 2... First metal wiring layer, 3... Wire, 5... Second metal wiring layer, 8... Island, 10... Green sheet, 11, 11 '...Through hole, 12... Notch.

Claims (1)

[Claims] 1. A first metal wiring layer is provided on the upper surface of the upper ceramic layer having openings, a second metal wiring layer is provided on the upper surface of the lower ceramic layer, and the upper and lower ceramic layers are integrated. A recess is formed by the opening in the upper ceramic layer and the lower ceramic layer below the opening, and the second metal wiring layer does not extend to the center of the opening. In the substrate, the first
Both the metal wiring layer and the second metal wiring layer are connected to the same external lead pin, and the first metal wiring layer is connected to the first and second metal wiring layers in the vicinity of the opening.
The first tip is a bonding pad for bonding a metal wire, and the second tip is a metallized layer formed in a notch provided on the wall of the opening. A ceramic substrate characterized in that the ceramic substrate is connected to the second gold layer wiring layer through the ceramic substrate.