JPS6331113B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device suitable for a programmable ROM in which data can be electrically erased.

EP-ROM (Erasable Programmable-ROM)
Data can be written or erased after manufacturing, and there are two main types: ultraviolet erasable type and electrically erased type. Among these, UV-erasable EP-ROM has one memory cell.
Since it can be configured with one transistor, it is possible to achieve high integration, and to date, devices with 32K bits and 64K bits of integration have been developed. However, this ultraviolet-erasable type requires a package that allows ultraviolet light to pass through, making it expensive. On the other hand, the electrically erasable type (especially E ² P-ROM (Electrically Erasable P-ROM)
(referred to as ROM), one memory cell is divided into at least two
Because it consists of only one transistor, it is not possible to increase the degree of integration very high, and to date only 16K bits of integration have been announced. However, this electrically erasable type has the advantage of being able to use inexpensive plastic as a package, thereby reducing manufacturing costs.

Of these, FIG. 1 is a configuration diagram showing one memory cell portion of a conventional E ² P-ROM, which was announced at the ISSCC in February 1980, in which one memory cell is composed of two transistors. In the figure 1
is a digit line, 2 is a selection line, and 3 is a data program line. Between the digit line 1 and the ground potential point, there is a MOS transistor 4 for bit selection, a control gate and a floating gate for data storage. A double gate type MOS transistor 5 is connected in series. The gate of the one MOS transistor 4 is connected to the selection line 2.
The control gate of the other MOS transistor 5 is connected to the data program line 3.

The conventional E ² P-ROM having such a configuration has the following drawbacks.

As is clear from Figure 1, since one memory cell is made up of two transistors, the number of elements is twice as high as that of the ultraviolet erasable type, and the degree of integration is half. It is disadvantageous to become

When writing and erasing data, voltages with both positive and negative polarities are required, and when mounted on a printed wiring board or the like, a power source with both positive and negative polarities is required to electrically rewrite data.

It is difficult to erase data simultaneously in word units or all bit units.

It is difficult to erase all bits of data in a short time.

It is impossible to erase data with a single 5 volt power supply.

The present invention has been made in view of the above-mentioned circumstances, and although the above-mentioned drawbacks can be eliminated,
It is an object of the present invention to provide a semiconductor memory device in which the efficiency of writing data into memory cells is high and the amount of charge held in the memory cells can be easily checked.

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 2a to 2d show the structure of a memory cell according to a first embodiment of the present invention, and only four bits of memory cells are shown. Of these, Fig. 2a is a pattern plan view, Fig. 2b is a structural sectional view taken along the -' line of Fig. 2a, and Fig. 2c is a pattern plan view.
FIG. 2d is a structural cross-sectional view taken along the line -' in FIG. 2A.

In FIG. 2, reference numeral 11 denotes a semiconductor substrate made of P-type silicon. On the surface of this substrate 11, gate insulating films 12a, 12b, 12c, and 12d are arranged at regular intervals in an XY matrix.
Further, on the surface of the substrate 11, gate insulating films 12a and 12 are formed at two locations adjacent to each other in the vertical direction in the figure.
c, 12b and 12d are paired, and a field insulating film 13 is formed between the pair of gate insulating films. Moreover, on this field insulating film 13, P
Alternatively, a first conductor layer 14 made of polysilicon containing As is formed. Furthermore, each of the gate insulating films 12a, 12b, 12c, 12d
Above, second conductive layers 15a, 15b, 15c, and 15d made of polysilicon are formed separately from each other. 2 located on the left side of the first conductor layer 14 in the figure.
The right end portions of the second conductive layers 15a and 15c overlap the left end portions of the first conductive layer 14 with the insulating film 16 interposed therebetween. Further, the left end portions of the two second conductive layers 15b and 15d located on the right side with respect to the conductive layer 14 are connected to the right end portions of the conductive layer 14 via the insulating film 16. It overlaps with Furthermore, second conductor layers 15a and 1 adjacent in the left and right direction in the figure
A third conductor layer 18A made of polysilicon and having a width set to be approximately the same as both conductor layers 15a and 15b is formed on the conductor layer 5b via an insulating film 17 so as to cover it. Similarly, the second conductor layer 1 adjacent in the left and right direction in the figure
5c, 15d are covered with conductive layers 15c, 15d via the insulating film 17.
Another third conductor layer 18B made of polysilicon and having a width set to be approximately the same as that is formed. And also, 2 adjacent vertically in the figure
An N ⁺ type semiconductor layer 19A is formed in the surface region of the substrate 11 between the gate insulating films 12a and 12c at two locations, and similarly the gate insulating film 12 at two locations is formed.
In the surface area of the substrate 11 between b and 12d,
An N ⁺ type semiconductor layer 19B is formed. Furthermore, each gate insulating film 12a, 12b, 12c, 12d
In contrast, the N ⁺ type semiconductor layer 19A or 1
A continuous N ⁺ -type semiconductor layer 19c is formed in the surface region of the substrate 11 on the opposite side from the side where 9B is formed. Further, the third conductive layer 18A, 18
A fourth layer made of Al is placed on B with an insulating film 20 interposed therebetween.
Conductive layers 21A and 21B are formed, one of which is connected to the N + type semiconductor layer 19A through a contact hole 22A, and the other conductive layer 21B is connected to the N ⁺ type semiconductor layer 19A through a contact hole 22A. N ⁺
type semiconductor layer 19B through another contact hole 22B. and said
The N ⁺ type semiconductor layer 19c is connected to a reference potential point, for example, a ground potential point.

In addition, in FIG. 2a, the area surrounded by broken lines with the symbol ABCD indicates a memory cell for one bit of this semiconductor memory device, and as is clear from FIG. 2b, this memory cell is The second conductor layer 15 is a floating gate,
The third conductor layer 18 is a control gate, the first conductor layer 14 is an erase gate, the N ⁺ type semiconductor layer 19A is a drain, and the N ⁺ type semiconductor layer 19c is an erase gate. source
It is composed of MOS transistors, and when looking at the 2 bits shown in Figure 2b, the control gate and erase gate are each common, and it is composed of a pair of MOS transistors configured symmetrically with respect to the erase gate. .
The control gate is provided on the semiconductor substrate 11 via an insulating film, and the floating gate and erase gate are arranged in parallel in the insulating film sandwiched between the control gate and the substrate 11. There is. Furthermore, since the erase gate is formed on the field insulating film 13,
The overlapping portions of each floating gate and erase gate exist within the field region. Further, as shown in FIG. 2b, in the overlapping portion, the second conductor layer 15, ie, the floating gate, is located above the first conductor layer 14, ie, the erase gate. , the distance between the substrate 11 and the conductor layer 14 is shorter than the distance between the substrate 11 and the conductor layer 15.

FIG. 3 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 2 above. In the figure, 31 and 32 are digit lines made up of the fourth conductor layers 21A and 21B, and 33 and 34 are the first conductor layers 1.
4 is an erase line formed by being extended, and 35 and 36 are selection lines (row lines) formed by extending the third conductor layers 18A and 18B. Also M1
~M4 is a memory cell, and each memory cell has a control gate CG, a floating gate FG,
Erase gate EG, drain D and source S
The drains D of the memory cells M1 and M2 are connected to one of the digit lines 31, and the drains D of the memory cells M3 and M4 are connected to the other digit line 3.
2, and the sources S of all memory cells are respectively connected to the ground potential point.

Next, the operation of the semiconductor memory device of the present invention will be explained using the equivalent circuit shown in FIG. 3 above. Now, paying attention to the memory cell M1 in FIG. 3, in the initial state, no electrons are injected into the floating gate FG of this memory cell M1, and its threshold voltage V _TH is in a low state.

When writing data to this memory cell M1, by applying a positive high voltage, e.g., +20 volts, to the selection line 35 and a positive high voltage, e.g., +20 volts, to the digit line 31,
A flow of hot electrons occurs from the source S to the drain D of the memory cell M1, and the hot electrons are injected into the floating gate FG from between the source and drain, that is, from the channel region. This increases the threshold voltage V _TH of this memory cell M1. When writing data, the erase line 33 may be applied with a pulse of a high voltage, for example, +20 volts, or may be applied with a DC voltage of +5 volts or 0 volts, or may be left open.

Next, when reading data from this memory cell M1, the selection line 35 is selected and the memory cell M
A high level signal (+
5 volts) is applied. When this high level signal is applied, if the threshold voltage V _TH is low, this memory cell M1 is turned on and one digit line 3 is turned on.
A current flows from M1 to the ground potential point through memory cell M1. On the other hand, if the threshold voltage V _TH is high when the high level signal is applied, this memory cell M1 is turned off and no current flows. At this time,
A state in which current flows through memory cell M1 is a logic "1" level, and a state in which no current flows is a logic "0" level.
level, this device can be used as a storage device. Also floating gate
As mentioned above, the FG is surrounded by an insulating film and is isolated from others, so
Once the electrons are injected here, they cannot escape under normal usage conditions, so it can be used as a non-volatile data storage device.

Further, when erasing data that has been written once, the selection line 35 and the digit line 31 are each set to 0 volts, and a high voltage, for example, a pulse voltage of +40 volts, is applied to the erase line 33. By applying such a voltage, field emission occurs between the floating gate FG and the erase gate EG of the memory cell M1, and the electrons that had been accumulated in the floating gate FG are removed. is leaked to the outside via the erase gate EG and the erase line 33. As a result, the threshold voltage V _TH of this memory cell M1 returns to a low state similar to the initial state.

In this way, in the semiconductor memory device of the above embodiment,
Since the erase gate is arranged in parallel to the floating gate of a normal double-gate type MOS transistor to form a memory cell for one bit, various effects such as those described below can be obtained.

One memory cell can be composed of one transistor, and data can be electrically erased. Therefore, electrically erasable EP−
It is possible to realize a ROM with the same degree of integration as the ultraviolet erasable type. Furthermore, since inexpensive plastic can be used as the package, the cost is low.

Writing, erasing, and reading data can be performed using a single polarity power supply. That is,
For example, you only need a positive polarity power supply of +20 volts for writing, +40 volts for erasing, and +5 volts for reading.Also, if you obtain +20 volts and +40 volts from the +5 volt voltage with a booster circuit, the power supply will be +5 volts. You can also do it with just one bolt. Therefore, data can be written, erased, and read while mounted on a printed wiring board or the like.

Since there is no transistor for bit selection, data can be erased simultaneously in units of words and units of all bits.

Since field emission is used to erase data, data can be erased in a short time.

Since only a three-layer polysilicon structure is formed and no other process is required, it can be manufactured using a normal silicon gate process.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 2 is shown in FIG.
This will be explained using the pattern plan views shown in FIGS. First, Figure 4a and Figure 5a
As shown in FIG.
An insulating film 1 μm thick is grown on the surface of 1 by photolithography to form field insulating films 13, 13', and P or
As is diffused by an implantation method or a diffusion method to form an N-type semiconductor layer 19C'.
After the completion of the diffusion, the field insulating films 13, 1
After exposing the surface of the substrate 11 in the area other than the 3' forming area, a 1000 Å to 2000 Å layer is applied here by thermal oxidation.
Then, a relatively thin oxide film is formed to form the gate insulating film 12. Next, the whole board 11
After growing polysilicon to a thickness of 6000 Å and doping it with P or As, a first conductive layer 14 is formed in the solid line region in FIG. 4b by photolithography. Although an example is shown in which the first conductor layer 14 is not formed on the adjacent field insulating films 13', it may be formed if necessary. Next, after forming the first conductive layer, as shown in FIGS. 4c and 5c, an insulating film 16 with a thickness of 500 Å is grown by thermal oxidation, and then By CVD method
A polysilicon film with a thickness of 5000 Å is grown, and a photolithography method is applied to this to form second conductor layers 15a, 15b, 15 as floating gates.
c, 15d are formed. As is clear from the figure, FIG.
An example has been shown in which only one end portion extending over the first conductive layer 14 overlaps with the first conductive layer 14 with the insulating film 16 interposed therebetween. and conductor layer 15
The other ends of a and 15b do not overlap with the conductor layer 14. After forming the floating gate,
As shown in FIG. 4d and FIG. 5d, an insulating film 17 with a thickness of 1000 to 2000 Å is formed by thermal oxidation, polysilicon is deposited thereon, and then photolithography is applied to this. is applied to form the third conductor layers 18A, 18B which will become control gates, and at the same time, the second conductor layers 15a, 15b, 15 are formed.
c and 15d are formed by self-alignment. Next, P or
By diffusing As, N ⁺ type semiconductor layers 19A, 19B, 1
Forms 9C. Furthermore, Figures 4e and 5e
As shown in FIG.
A fourth conductor layer 21A, 21B is formed by continuously depositing an Al film and applying a photolithography method to this Al film.
and contact portions 22A, 22
This semiconductor memory device is completed by connecting each of the N ⁺ type semiconductor layers 19A and 19B with B.

6a to 6c show the configuration of a memory cell according to a second embodiment of the present invention, and FIG.
is a pattern plan view, and Fig. 6b is -' in Fig. 6a.
A cross-sectional view of the structure along the line, Fig. 6c, is - in Fig. 6a.
FIG.

In FIG. 6, 111 is a semiconductor substrate made of P-type silicon, and gate insulating films 112a to 112f are formed at regular intervals on the surface of this substrate 111.
They are arranged in an XY matrix. Further, on the surface of the substrate 111, gate insulating films 112a and 112d are formed at respective locations adjacent to each other in the vertical direction in the figure.
112b and 112e and 112c and 112f are paired, and field insulating films 113 and 113' are formed between the gate insulating film pairs. Further, a first conductive layer 114 made of polysilicon containing P or As is formed on the field insulating film 113 at one location. Further, on each of the gate insulating films 112a to 112f, second conductor layers 115a to 115a made of polysilicon are formed.
115f are formed separately from each other. The right end portions of the two second conductor layers 115b and 115e located on the left side with respect to the first conductor layer 114 in the figure are connected to the insulating film 1.
It overlaps with the left end portion of the first conductor layer 114 via the conductor layer 16 . In addition, the conductor layer 114
The left end portions of the two second conductor layers 115c and 115f located on the right side of the conductor layer 115 overlap the right end portion of the conductor layer 114 with the insulating film 116 interposed therebetween. . Furthermore, second conductor layers 115a and 11 adjacent in the left and right direction in the figure
5b, 115c, each of these conductive layers 115a, 1
A third conductive layer 118A made of polysilicon and having a width set to be approximately the same as that of 15b and 115c is formed, and similarly a second conductive layer 118A adjacent to the third conductive layer 118A in the left and right direction in the figure is formed. 115d, 115
The conductor layers 115d, 115f are formed on the conductor layers 115d, 115f via the insulating film 117 so as to cover them.
Another third conductor layer 118B made of polysilicon is formed and has approximately the same width as 115e and 115f. Furthermore, there are two gate insulating films 112 adjacent to each other in the vertical direction in the figure.
In the surface area of the substrate 111 between a and 112d,
An N ⁺ type semiconductor layer 119A is formed, and an N ⁺ type semiconductor layer 119B is formed in the surface region of the substrate 111 between the two gate insulating films 112b and 112e.
Similarly, there are two gate insulating films 112c and 112e.
An N ⁺ type semiconductor layer 119C is formed in the surface region of the substrate 111 between the substrate 111 and the substrate 111. Furthermore, for each ^gate insulating film 112a to 112e, a continuous
An N ⁺ type semiconductor layer 119D is formed. Further, a wiring layer 1 made of Al is placed on the third conductive layer 118A, 118B with an insulating film 120 interposed therebetween.
21A, 121B, 121C, and 121D are formed, of which one wiring layer 121A and the above wiring layer 121A are formed.
Contact hole 1 is connected to N ⁺ type semiconductor layer 119A.
22A, and is connected to the wiring layer 121B by N ⁺
type semiconductor layer 119B is the contact hole 122.
B, and the wiring layer 121C and the first
The contact hole 12 is connected to the conductor layer 114 of the second layer.
2C, and is also connected to the wiring layer 121D.
The contact hole 1 is connected to the N ⁺ type semiconductor layer 119C.
22D. and said N ⁺
The type semiconductor layer 119D is connected to a reference potential point, such as a ground potential point.

In addition, in FIG. 6a, the area surrounded by broken lines with the symbol ABCD indicates a memory cell for one bit of this semiconductor memory device, and this memory cell flows through the second conductor layer 115. floating gate, third conductor layer 118
The first conductive layer 114 is an erase gate, the N ⁺ type semiconductor layer 119B is a drain, and the N ⁺ type semiconductor layer 119D is a source. Furthermore, when looking at the two bits shown in FIG. 6b, the control gate and erase gate are common, and are composed of a pair of MOS transistors that are symmetrically arranged with respect to the erase gate. The control gate is connected to the semiconductor substrate 11 through an insulating film.
1, and the floating gate and erase gate are provided on the control gate and the substrate 1.
They are arranged in parallel in an insulating film sandwiched by 11. Furthermore, since the erase gate is formed on the field insulating film 113, the overlapping portion of each floating gate and erase gate exists within the field region. Further, as shown in FIG. 6b, in the overlapping portion, the second conductive layer 1
15, that is, the floating gate is located above the first conductive layer 114, that is, the erase gate, and the distance between the substrate 111 and the conductive layer 114 is the same as the distance between the substrate 111 and the conductive layer 115. It's shorter than that. Further, as is clear from FIG. 6a, the first conductor layer 114 has four
Only one location is provided for each bit memory cell, and each one location of the conductor layer 114 is connected to the wiring layer 121C through one contact hole 122C.

The equivalent circuit diagram of the semiconductor memory device shown in FIG. 6 is the same as that shown in FIG. 3, and its operation is also the same, so a description thereof will be omitted.

Further, in addition to the effects of the semiconductor memory device of the embodiment described above, the following effects can also be obtained.

Erase gate (first conductor layer) 11
Since the wiring layer 121C made of Al is used to form the erase line instead of using the polysilicon that constitutes 4, the thickness of the insulating film between the erase line and the substrate is can be made relatively thick, so even if a high voltage is applied to the erase line, leakage will not occur.

Since one contact hole connecting the erase gate and the wiring layer 121C needs to be provided for every four bits of the memory cell, the number of contacts per one bit is 1/4, and high integration is possible.

Since hot electron injection is used when writing data and field emission is used when erasing data, a relatively thick insulating film can be used around the floating gate, resulting in good non-volatile characteristics, that is, data retention characteristics.

Next, an example of a manufacturing method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 6 is shown in FIG. 7a.
This will be explained using pattern plan views shown in FIGS. 8a to 8e and sectional views taken along the line -' shown in FIGS. First, Figure 7a and Figure 8a
As shown in FIG. 2, field insulating films 113 and 113' are formed by growing an insulating film to a thickness of 1 μm on the surface of a semiconductor substrate 111 made of P-type silicon by photolithography. Note that at this time, the field insulating film 11
A thin insulating film 123 is formed between 3 and 113'. Next, polysilicon is grown to a thickness of 6000 Å on the entire surface of the substrate 111, and after doping it with P or As, the field insulation is formed in the above one place as shown by the solid line in FIG. A first conductor layer 114 is formed on the film 113. Here, adjacent field insulating films 11
Although an example is shown in which the conductor layer 114 is not formed on the conductor layer 3', it may be formed if necessary. Next, after forming the first conductor layer 114,
As shown in FIGS. 7c and 8c, an oxide film with a thickness of 500 Å is grown by a thermal oxidation method to form the gate insulating films 112a to 112f and the insulating film 1.
16, and then by CVD method.
Polysilicon is grown to a thickness of 5000 Å, and a photolithography method is applied to the polysilicon to form second conductor layers 115a to 115f as floating gates. As is clear from the figure, FIG. 8c shows a conductive layer 115 that becomes a floating gate.
An example has been shown in which only one end of the field insulating film 113 extending over the field insulating film 113 at least partially overlaps with the first conductive layer 114 with the insulating film 116 interposed therebetween. And conductor layer 115b, 1
The other end of 15c does not overlap with conductor layer 114. After forming the floating gate,
As shown in FIG. 7 d and FIG. 8 d, an insulating film 117 with a thickness of 1000 Å to 2000 Å is formed by thermal oxidation, polysilicon is deposited thereon, and then photolithography is applied to this. is applied to form the third conductive layers 118A and 118B which will become control gates, and at the same time, the second conductive layers 115a to 11 are formed.
5f is formed by self-alignment. Next, the seventh
N ⁺ type semiconductor layer 119A, 1 which becomes a drain by diffusing P or As into the shaded region in Figure e
19B, 119C and an N ⁺ type semiconductor layer 119D which will serve as a source are formed. Further, as shown in FIGS. 7e and 8e, an insulating film 120 and an Al film are successively deposited over the entire substrate 111, and a photolithography method is applied to this Al film to form a wiring layer 120.
1A, 121B, 121C, and 121D are formed. Note that at this time, the contact hole 122 is
A, 122B, 122C, 122D are opened and contact holes 122A, 122B, 12
N ⁺ type semiconductor layer 119A,
119B, 119C and wiring layers 121A, 121
B, 121D, respectively, in the contact hole 12
This semiconductor memory device is completed by connecting the first conductor layer 114 and the wiring layer 121C with 2C.

FIG. 9 shows an embodiment of the present invention, in which an M.times.N bit semiconductor memory device is constructed using the semiconductor memory device shown in FIG. 2 or FIG. 6. In the figure, M ₁₁ …M _1M …M _N1 …M _NM is
1-bit memory cells each arranged in a matrix of M cells in the column direction and N cells in the row direction;
Each of these memory cells is composed of a control gate CG, a floating gate FG, an erase gate EG, a drain D, and a source S as described above. The drain D of each memory cell arranged in the same column is connected to each N digit line 41.
₁ to 41 _N are commonly connected to each other. Further, for the N digit lines 41 ₁ to 41 _N , a column address is input, and one output terminal is selected according to the column address when reading or writing data, and a high level signal is output from only the selected output terminal. , e.g., +5, +20 volts, and outputs a low level signal, e.g., 0 volts, from all unselected outputs. Furthermore, the control gate CG of each N memory cells arranged in the same row is
It is commonly connected to each of M row selection lines 43 ₁ to 43 _M. Furthermore, the M row selection lines 43 ₁ to
43 _M selects one output terminal according to the row address when a row address is input and data is read or written, and outputs a high level signal only from this selected output terminal, and outputs a high level signal from all unselected output terminals. It is connected to the output end of the row decoder 44 which outputs a low level signal. In addition, the erase gates EG of all memory cells are commonly connected, and the erase terminal 46 is further connected via a protective resistor 45.
It is connected to the. The sources S of all memory cells are commonly connected and further connected to a ground potential point.

The erase terminal 46 is connected to a data erase voltage when erasing the gate stored in each memory cell.
For example, +40 volts is applied.

In a memory device with such a configuration, if the capacitance between the floating gate FG and the control gate CG is _CFC , if a charge (electron) of -Q enters the floating gate FG, the transistor of the memory cell will The amount of change in the threshold voltage ΔV _T is ΔV _T =Q/C _FC (1). Therefore, due to the charge of -Q,
Since the threshold voltage changes as shown in equation (1), the memory
It is possible to determine whether the stored data in the cell is "1" or "0".

On the other hand, when the voltage V _E is applied to the erase gate EG via the erase terminal 46, ΔV _T is expressed as ΔV _T =Q−C _FE V _E /C _FC (2). Here, C _FE is the capacitance between the floating gate FG and the erase gate EG. In this way, ΔV _T is expressed by equation (2), and the apparent charge -Q accumulated in the floating gate can be reduced or increased by applying voltage V _E to the erase gate EG. , the amount of voltage injected into the floating gate FG can be quantitatively known from the voltage applied to the erase gate EG. In other words, the erase gate applied voltage V _E required to obtain a certain ΔV _T can be measured, and from equation (2), Q
I understand.

To give a specific example of the method for measuring the amount of charge Q described above, when a memory cell is selected by the decoders 42 and 44 and the voltage V _E of the erase terminal 46 is changed, the data on the digit line of the selected memory cell is inverted. All you need to know is the voltage V _E. In addition, by first measuring the amount of charge Q immediately after data is written, and then measuring the amount of charge Q again after a predetermined period of time, it is possible to quantitatively predict the amount of charge decay due to aging from both measurement results. Therefore, since the retention characteristics of each memory cell can be estimated, bits with poor retention characteristics of memory cells can be screened in advance.

On the other hand, in order to efficiently know the amount of charge Q, it is better to use C _FE C _FC ... (3) from equation (2), but from the viewpoint of writing efficiency, the tendency is C _FC > C _FE ... (4) It is better to have a larger value, and therefore, the capacitance C _FE is required to have a certain size or more. Therefore, from the above writing efficiency and charge amount check, C _FC > C _FE ≧ C _FC /5 ...It is desirable to satisfy (5).

FIG. 10 is a configuration diagram of a first modified example of the embodiment shown in FIG. The ends are connected. With such a configuration, even if the erase terminal 46 becomes open when data is not erased, the resistor 4
7, the erase gate EG of each memory cell is set to the ground potential and does not go into a floating state, so malfunctions due to noise can be prevented. Furthermore, when data is not erased, the erase gate EG is set to the ground potential, so the coupling at the overlapping portion between the floating gate FG and the erase gate EG biases the floating gate FG to a potential closer to the ground potential. As a result, the threshold voltage V _TH of the memory cell becomes deeper.

FIG. 11 is a configuration diagram of a second modification of the embodiment shown in FIG. 9, in which, instead of the resistor 47 in FIG.
One end of the resistor 48 is connected to the positive polarity power supply voltage V _CC (+5 volts) application point, and the other end thereof is connected to the resistor 48 . With this configuration, even if the erase terminal 46 is open when data is not erased, the erase gate EG of each memory cell is set to the V _CC potential by the resistor 48 and becomes a floating state, as described above. Since there is no noise, malfunctions due to noise can be prevented. In addition, when data is not erased, the erase gate EG is set to the V _CC potential, so the floating gate FG is
is biased closer to the V _CC potential, resulting in a shallower threshold voltage of the memory cell.

FIG. 12 is a block diagram of a third modification of the embodiment shown in FIG. 9, in which both the resistor 47 in FIG. 10 and the resistor 48 in FIG. 11 are provided in the circuit in FIG. This is what I did. With this configuration,
When data is not erased, the erase gate EG is set to a potential between the ground potential and the V _CC potential.

Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, the second
In the figure or FIG. 6, the second conductive layer 15
The case has been described in which only the right end portion or the left end portion of the conductor layer 115 overlaps at least a portion of the first conductor layer 14 or 114; The conductor layer 14 or 114 may be overlapped with the conductor layer 14 or 114.

As explained above, the semiconductor memory device of the present invention includes
One memory cell can be configured with one transistor, and data can be erased electrically, which improves the conventional problems in terms of integration density and cost, and also reduces the capacitance between each gate of the memory cell. Since it is set optimally, the efficiency of writing data into the memory cell is high, and the amount of charge held in the memory cell can be easily checked.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one memory cell portion of a conventional E ² P-ROM, and FIGS. 2a is a pattern plan view, FIG. 2b is a structural cross-sectional view taken along line -' in figure a, FIG. 2c is a structural cross-sectional view taken along line -' in figure a, and figure 2d is
3 is an equivalent circuit diagram of the device shown in FIG. 2, and FIGS. 4 a to 5 e and 5 a to e are the device shown in FIG. 4A to 4E are pattern plan views, and FIGS. 5A to 5E are pattern plan views.
Cross-sectional views along lines -' of Figures 6a to 6c.
6 shows the configuration of a memory cell according to a second embodiment of the present invention, and FIG. 6a is a pattern plan view;
Fig. 6b is a structural cross-sectional view taken along -' of Fig. 6a;
Fig. 6c is a structural sectional view taken along the -' line of Fig. 6a;
7a to 8e and 8a to 8e are for explaining an example of a manufacturing method for manufacturing the device shown in FIG. 6, respectively, and FIGS. 7a to 7e are pattern plan views, 8a to 8e are sectional views taken along the lines -' of FIGS. 7a to 7e, FIG. 9 is a circuit configuration diagram of an embodiment of the present invention, and FIG.
The figure is a circuit configuration diagram of a first modification of the above embodiment, FIG. 11 is a circuit diagram of a second modification of the above embodiment, and FIG. 12 is a circuit diagram of a third modification of the above embodiment. It is a diagram. 11,111...Semiconductor substrate, 12,112...
...Gate insulating film, 13,113...Field insulating film, 14,114...First conductor layer (erase gate), 15,115...Second conductor layer (floating gate) ,16,116,
17,117,20,120,123...Insulating film, 18,118...Third conductor layer (control gate), 19,119...N ⁺ type semiconductor layer, 21...Fourth layer conductor layer, 121... wiring layer, 22, 122... contact hole, 3
1, 32...digit line, 33, 34...erasure line, 35, 36...selection line, M1, M2, M3,
M4...memory cell, CG...control gate, FG...floating gate, EG...erase gate, D...drain, S...source, _M11 ~
M _1M ~M _N1 ~M _NM ...Memory cell, 41...Digit line, 42...Column decoder, 43...Row selection line, 44...Row decoder, 45, 47, 48...
Resistor, 46... Erase terminal.

Claims (1)

[Claims] 1. A control gate provided on a semiconductor substrate via an insulating film, an erase gate provided in the insulating film sandwiched between the control gate and the base, and a control gate provided in parallel with the erase gate in the insulating film. The memory cell includes a floating gate whose end overlaps with at least a portion of the erase gate via an insulating film, a source and a drain, and the memory cell includes the floating gate and the control gate. C _FC is the capacitance between the floating gate and the erase gate, and C _FE is the capacitance between the floating gate and the erase gate.C _FC ＞C _FE ≧
A semiconductor memory device characterized by having a configuration that satisfies the relationship C _FC /5.