JPS6331139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a constant envelope linear quadrature phase modulator suitable for digital mobile communications.

When applying digital modulation to mobile communications such as car telephones, cordless telephones, and police radios, it is necessary to use as narrow a band as possible in order to effectively use the frequency band, and also to prevent fading and the effective use of electric power for mobile devices. It is desirable that the modulation waveform has a constant envelope linear shape so that nonlinear amplification is possible. As narrowband digital modulation methods aimed at application to such mobile communications, several phase modulation methods have been proposed in which the occupied spectrum bandwidth is made as narrow as possible while keeping the modulation waveform constant.
For example, there is a phase modulation method that calculates and optimizes the locus of phase change based on data of several time slots before and after the baseband signal so as to minimize the leakage power outside the band while keeping the deterioration of the aperture ratio of the eye pattern small. be. A quadrature phase modulator is one of the phase modulators used in such a modulation method. In this method, two carrier waves having equal amplitudes and mutually orthogonal phases are balanced-modulated using two signal-processed baseband signals, and then phase modulation is performed by adding these signals together. An example of a conventional quadrature phase modulator using a balanced modulator is shown in FIG.

In FIG. 1, a baseband signal φ(t) from an input terminal 10 is converted into a sine component sinφ(t) and a cosine component cosφ(t) of the baseband signal by waveform conversion circuits 11 and 12, and is balanced modulated. Vessel 1
3 and 14, respectively. On the other hand, oscillator 1
A carrier wave is outputted from 5 and applied to a balanced modulator 13 and also applied to a balanced modulator 14 via a 90° shifter 16. The outputs of the balanced modulators 13 and 14 are added by an adder circuit 17, and then made into a constant envelope by a limiter 18 and sent to an output terminal 19.
is output as a phase modulated signal.

Now, if the carrier wave applied from the oscillator 15 to the balanced modulator 13 is cosω _c t, then the carrier wave applied to the balanced modulator 14 from the 90° phase shifter 16 is sinω _c t, which is the output A, B of the balanced modulators 13 and 14. becomes as follows.

A=sinφ(t)・cosω _c t...(1) B=cosφ(t)・sinω _c t...(2) After these outputs A and B are added by the adder circuit 17, the limiter 18 This _{output P 0 is} output as _follows . ) This is a signal obtained by phase modulating the carrier wave of angular frequency ω _c with the baseband signal φ(t). Here, the limiter 18 is for removing amplitude changes that occur when the orthogonality of carrier waves is poor.

In other words, in such a quadrature phase modulator, amplitude changes and phase distortion occur in the phase modulation signal output due to carrier wave orthogonality error and carrier wave leakage, so when used in a narrowband digital modulation method, A limiter 18 removes amplitude changes to provide a constant envelope. At this time, the amplitude change is removed, but the phase distortion remains and increases out-of-band spurious. Therefore, in the orthogonal phase modulator used in the narrowband digital modulation method, the orthogonality error of the carrier wave, that is, the amplitude deviation and phase orthogonality error of the carrier wave applied to the balanced modulators 13 and 14 are reduced to zero, and , carrier wave leakage must also be reduced to zero. The output P ₁ of the adder circuit 17 when there is a carrier wave orthogonality error and carrier wave leakage is:
Based on the amplitude and phase of the carrier wave applied to the balanced modulator 14, when the carrier wave amplitude deviation is Δx, the phase orthogonality error is Δθ, the carrier wave leakage level is Δy, and its phase is Φ, it is expressed by the following equation.

P ₁ = (1+Δx) sinφ(t)・cos(ω _c t+Δθ)+co
sφ(t)・sinω _c t+Δy sin(ω _c t+Φ) = (1+Δx) sinφ(t) {cosω _c t・cosΔθ−sin
ω _c t・sinΔθ} +cosφ(t)・sinω _c t+Δy{sinω _c t・cosΦ+c
osω _c t・sinΦ} = sinφ(t)・cosω _c t+cosφ(t)・sinω _c t + {(1+Δx)cosΔθ・sinφ(t)−sinφ(t)
+Δy sinΦ}cosω _c t +{Δy cosΦ−(1+Δx)sinΔθ・sinφ(t)}
sinω _c t = sin {ω _c t+φ(t)} + [{(1+Δx) cosΔθ−1} sinφ(t)+Δy s
inΦ〕cosω _c t + {Δy cosΦ−(1+Δx) sinΔθ・sinφ(t)}
sinω _c t...(4) In equation (4), the first term is an ideal phase modulated wave, and the second and third terms are components that indicate spurious components that cause phase distortion. It can be displayed as a vector. In FIG. 2, vector 21 represents the first term of equation (4), vector 22 represents the second term, and vector 23 represents the third term. Therefore, from equation (4), P ₁ = {1 + A (t)} sin {ω _c t + φ (t) + α (t)
}
...(5) When expressed as, α(t) represents the phase distortion. If |Δx|≪1, |Δθ|≪1, |Δy|≪1, then |α(t)|≪1, which can be expressed approximately as follows from FIG.

α(t) [{(1+Δx)cosΔθ−1}sin
φ(t)+Δy sinΦ〕cosφ(t) −{Δy cosΦ−(1+Δx)sinΔθ・sin
φ(t)}・sinφ(t)……(6) If we omit the squares of Δx, Δθ, Δy and their mutual products in equation (6), we get becomes. If there is an orthogonality error or carrier leakage as shown in equation (5), the output of the adding circuit 17 is also subjected to amplitude modulation, but the amplitude modulation is removed by the limiter 18. The phase modulated wave _P2 that has passed through the limiter 18 is expressed by the following equation.

According to the addition theorem of trigonometric functions, when |y|≪1, sin(x+y)=sin x cos y+cos x
Since sin ysin x+y・sin x, applying this to equation (8) yields the following.

In Equation (9), the fourth and fifth terms represent signals phase-modulated by the second and third harmonics of the baseband signal, which increases the leakage power outside the band in the narrowband digital modulation method. let As described above, in the conventional quadrature phase modulator, the output of the adder circuit 17 is not constant due to carrier wave orthogonality error and carrier wave leakage, and when it is passed through the limiter 18 to make it a constant envelope, phase distortion occurs. As a result, an out-of-band spectrum is generated, making it difficult to reduce adjacent channel leakage power when used in a narrowband digital phase modulation system. In particular, when the carrier frequency becomes high, it becomes difficult to reduce Δθ, making adjustment difficult.

The present invention has been made in view of these points, and its purpose is to provide a quadrature phase modulator with small carrier wave orthogonality error and carrier wave leakage, which are necessary when used in narrowband digital modulation. It's about doing.

The present invention uses a digital arithmetic circuit to perform two types of multiplications of the sine and cosine components of the baseband signal and the sine and cosine components of the carrier wave alternately at a period that is an integer multiple of the carrier wave. It is characterized by extracting the multiplication result as a time division multiplexed signal and smoothing it to obtain a phase modulated signal output.

Therefore, in the present invention, since the baseband signal and carrier wave are multiplied by digital calculation, carrier wave leakage unlike in analog calculation does not occur in principle, and the multiplication result is a binary time division multiplexed signal. Therefore, even if an orthogonality error occurs at the multiplexing stage, it can be easily removed by timing recovery (retiming), and phase distortion can be minimized.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a waveform diagram for theoretically explaining the digital multiplication of a baseband signal and a carrier wave in the present invention, that is, the processing corresponding to one of the balanced modulators in FIG. 1. In this example, the baseband signal expressed as a digital signal is 3 bits, and the case where a signal of "100" (=4) is input is shown. a is a carrier wave of an analog waveform, but when performing multiplication with 2 ³ = 8 periods as a unit period of calculation, a carrier wave with a number of periods corresponding to the digital code representing the baseband signal is output within the 8 periods. , by smoothing this with a bandpass filter or the like, it is possible to perform multiplication of the carrier wave and the baseband signal. b shows an output waveform when this multiplication is performed in an analog manner, and only four periods out of eight periods of the carrier wave are output. However, in order to obtain the waveform b, it is necessary to use an analog gate or a switch whose carrier wave is a rectangular wave and outputs three values, which is not preferable in terms of circuit configuration. In general, binary circuits are often used in digital arithmetic circuits, so in the present invention, a rectangular carrier wave as shown in c is used, and this is converted by using, for example, a 1/8 frequency divider and a binary rate multiplier. The digital value of the baseband signal obtained as d is ANDed with the corresponding number of pulse trains to obtain the waveform e. Then, if necessary, the sign of the signal d is changed and the "1" level of the signal f is converted to "0" every other period of the carrier wave to create a signal g. By performing a logical OR with the signal, a signal equivalent to b shown in h is obtained. That is, the average level of the signal e over eight periods is (8/4)×(1/2), and by adding the average level of the signal g, the average level of h becomes 1/2. Since the pulse width of g is the same as the carrier wave period, no carrier wave component is included.

FIG. 4 is a waveform diagram for explaining the operation of the digital arithmetic circuit according to the present invention. In FIG. 4, the absolute values of the sine and cosine components of the baseband signal are expressed as 3-bit digital codes for ease of viewing. Therefore, 2 ³ of the conveyance in Fig. 3
The unit period of calculation is twice the period. This 2
Time slots T _sio and T _cps are assigned to the sine and cosine components of the baseband signal for each cycle of the carrier wave during the × ²³ period. That is, FIG. 4a represents a carrier wave of sinω _c t, where the carrier wave angular frequency is ω _c , and b represents cosω _c t. c.
is the cosine component cosφ of the 8 time slots assigned to the cosine component cosφ(t) of the baseband signal.
"101" representing (t) is a waveform in which only 5 time slots are "1", and d is the sine component sinφ(t) of the 8 time slots assigned to the sine component sinφ(t) of the baseband signal. “110” representing
This is a waveform in which only the =6 time slots are set to "1". As explained in Fig. 3, the waveform of e is the logical product of the waveform of a and the waveform of c, which is the product of the sine component sinω _c t of the carrier wave of a and the cosine component cosφ(t) of the baseband signal of c. , and a part of the baseband signal component is added so that the average level is 1/2. Similarly, the waveform of f is the cosine component cosω _c of the carrier wave of b, the sine component of the baseband signal of t, and the sine component of the baseband signal of d.
A part of the baseband signal component is added to the multiplication result with sinφ(t). The waveforms of e and f are c
It has meaning only in the respective time slots shown in and d. The output of the phase modulation signal is basically g
It is expressed as the logical sum of the waveforms of e and f as shown in , and is smoothed by adding it to a D flip-flop and regenerating the timing if necessary, and then passing it through a smoothing circuit such as a bandpass filter. In other words, interpolation is performed.

FIG. 5 is a block diagram of a phase modulator according to one embodiment of the present invention using the multiplication and time division method described in FIGS. 3 and 4. In FIG. 5, a baseband signal φ(t) represented by a digital code is inputted to an input terminal 30, and its sine component sinφ is converted by waveform conversion circuits 31 and 32.
(t) and a cosine component cosφ(t).
These waveform conversion circuits 31 and 32 are, for example, ROM
Composed by.

40 is a carrier wave generation circuit, which includes an oscillator 41, frequency dividing circuits 42, 43, 44, and a phase selection circuit 4.
5,46. That is, the oscillator 41 oscillates at a frequency four times the carrier wave frequency _c ,
The output is divided into 1/4 by the frequency dividing circuit 42, further divided by 1/2 by the frequency dividing circuit 43, and then divided by the frequency by the frequency dividing circuit 44.
added to. The frequency dividing circuit 42 is composed of, for example, a two-stage D flip-flop, and divides the frequency of the output of the oscillator 41 by 1/4 to produce four outputs with a phase difference of 90 degrees, that is, a cosine component of the carrier wave. ±cosω _c t and sine component ±sinω _c t are generated. Among these, ±cosω _c t is the phase selection circuit 45
In addition, ±sinω _c t is applied to a phase selection circuit 46, and one of them is selected by the bit (MSB) indicating the polarity of the output of the waveform conversion circuits 31 and 32, respectively. When the digital codes sinφ(t) and cosφ(t) output from the waveform conversion circuits 31 and 32 are composed of polarity bit (1 bit) + absolute value bits (N bits), the frequency dividing circuit 44 N
This is a 1/2 ^N divider circuit consisting of a bit binary counter.

50 is sinφ(t)・cosω _c t and cosφ(t)・
This is a digital arithmetic circuit that executes multiplication of sinω _c t and time-division multiplexing thereof by digital arithmetic operations, and is configured as follows. That is, N-bit digital codes excluding the polarity bits of the outputs of the waveform converting circuits 31 and 32, that is, representing the absolute values, are applied to binary rate multipliers 51 and 52 each having an N-bit configuration, and the input signal of the frequency dividing circuit 44 is Waveform conversion circuit 31, 3 in 1/2 ^N period
“1” is output for a number of cycles corresponding to the output of “2”. The outputs of the binary rate multipliers 51 and 52 are applied to one input terminal of AND gates 53 and 54, respectively, and the non-inverted output of the frequency divider circuit 43 is applied to the other input terminal of the AND gate 53, and The inverted output of the frequency divider circuit 43 is applied to the input terminal of the frequency divider circuit 43. Therefore, AND gate 53,5
At the outputs of 4, signals corresponding to those shown in FIG. 4 d and c are obtained, respectively. The output of AND gate 53 is AND
The output of the AND gate 54 is applied to one input terminal of the AND gate 56 and the baseband component reproduction circuit 58. The outputs of the phase selection circuits 45 and 46 are input to the other input terminals of the AND gates 55 and 56, respectively. Therefore, the outputs of the AND gates 55 and 56 have signals corresponding to f and e in FIG. 4, that is, sinφ
The multiplication results of (t)·cosω _c t and cosφ(t)·sinω _c t are obtained. The outputs of the AND gates 55 and 56 are added together with the outputs of the baseband reproduction circuits 57 and 58 in an OR gate 59, and are combined together as shown in FIG.
It becomes a time division multiplexed signal corresponding to . The baseband component reproducing circuits 57 and 58 output baseband signal component signals for compensating the average level of the output of the OR gate 59 to be 1/2 of the logic "1" level, as shown in FIG. 3g. This is a circuit that creates
The output of the OR gate 59 is a D flip-flop 60.
The timing is recovered by the output of the oscillator 41, which is the base of the carrier wave. Therefore, the output of the D flip-flop 60 is transmitted to the carrier wave generation circuit 40.
Carrier wave orthogonality errors that occur within the carrier wave or during the multiplication and time division multiplexing processes have been removed.

The time-division multiplexed signal whose timing has been recovered by the D flip-flop 60 is smoothed by a band pass filter 61 in the pass band, and is smoothed by the output terminal 62.
is extracted as the phase modulation signal output P ₀ shown by equation (3).

As described above, in the present invention, the digital arithmetic circuit multiplies the sine and cosine components of the baseband signal by the sine and cosine components of the carrier wave alternately at intervals of integral multiples of the carrier wave, for example, every cycle. By time-division multiplexing the multiplication results of It is possible to make it smaller. In addition, in the above embodiment, all processing is performed by digital circuits except for the bandpass filter, so it is easy to integrate the circuit and is suitable for the low voltage required in mobile communications.

Note that the present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, an N-bit digital code representing the absolute value of the sine component and cosine component of the baseband signal and the cosine component and sine component of the carrier wave are combined. Multiplication and time-division multiplexing were performed using an N-bit binary rate multiplier and an AND gate, but we divided these N bits into multiple groups and performed multiplication and time-division multiplexing for each group. It's okay.

FIG. 6 shows an example in which N bits are divided into two groups, upper M bits and lower L bits, and multiplication and time division multiplexing are performed. In FIG. 6, a 1/2 ^M frequency divider circuit 441 and a 1/2 ^L frequency divider circuit 442 correspond to the 1/2 ^N frequency divider circuit 44 in FIG. 522 is the fifth
51 and 52 in the figure are AND gates 531 and 532
and 541, 542 and 551, 552 are located at 53, 54, and 55 in FIG. At 59 in the figure, D flip-flops 601, 60
2 corresponds to 60 in FIG. 5, respectively. Since the time-division multiplexed signals corresponding to the upper M bits and lower L bits obtained at the outputs of the D flip-flops 601 and 602 have different weights, for example, in the case of M=L=N/2, the outputs of the D flip-flop 602 After the output is multiplied by a coefficient of 1/2N/2 in an attenuator 603, the two are added together in an adder 604 and input to the band pass filter 61. According to this embodiment, the actual circuit scale (number of elements) is reduced compared to the embodiment shown in FIG.

In addition, the present invention can be implemented with various modifications; for example, in the embodiments shown in FIGS. 4 and 5, two types of multiplication are performed by the sine component and cosine component of the baseband signal and the sine component and cosine component of the carrier wave. Although these are performed using separate circuits, these two types of multiplication and time division multiplexing may be performed by using the same circuit and switching its inputs alternately. In that case, D flip-flops 60, 601, 60 for timing recovery
2, it is possible to remove carrier wave orthogonality errors. It goes without saying that these two types of multiplication may be performed between sine components and cosine components of the baseband signal and carrier wave.

Further, in the embodiment, two types of multiplication are performed alternately every period of the carrier wave, but it may be performed every integer multiple period.

Furthermore, the smoothing circuit is not limited to a bandpass filter, but may also be a phase-locked loop (PLL) with a built-in analog oscillator such as a VCO, or an injection period oscillator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a quadrature phase modulator, FIG. 2 is a vector diagram showing the basic operation of the quadrature phase modulator, and FIG. 3 is a diagram for explaining the digital multiplication in the present invention. FIG. 4 is a waveform diagram for explaining the state of time division multiplexing in the present invention, and FIGS. 5 and 6 are diagrams showing the configuration of a phase modulator according to an embodiment of the present invention. 30...Baseband signal input terminal, 31,3
2... Waveform conversion circuit, 40... Carrier wave generation circuit,
50...Digital arithmetic circuit, 61...Band pass filter (smoothing circuit), 62...Phase modulation signal output terminal.

Claims (1)

[Claims] 1. Two types of multiplication of the sine and cosine components of the baseband signal and the sine and cosine components of the carrier wave are performed alternately at every integer multiple period of the carrier wave, and these multiplication results are calculated over time. 1. A quadrature phase modulator comprising: a digital arithmetic circuit that performs division and multiplexing; and a smoothing circuit that smoothes the output of the digital arithmetic circuit to obtain a phase modulated signal output. 2. The quadrature phase modulator according to claim 1, wherein the digital arithmetic circuit regenerates the timing of the time-division multiplexed signal using a signal that is the basis of a carrier wave and outputs the result. 3. The quadrature phase modulator according to claim 1 or 2, wherein the digital arithmetic circuit adds a part of the baseband signal component to each multiplication result and time-division multiplexes the result. 4. The digital arithmetic circuit divides the digital code representing the absolute value of the sine component and cosine component of the baseband signal into a plurality of bits, and multiplies each group with the cosine component and sine component of the carrier wave, and multiplies these components. The results are time-division multiplexed, and the time-division multiplexed signals for each group are multiplied by coefficients corresponding to respective weights, then added and combined and output. The quadrature phase modulator according to any one of . 5. The quadrature phase modulator according to claim 1, wherein the smoothing circuit is a bandpass filter. 6. The quadrature phase modulator according to claim 1, wherein the smoothing circuit is a phase synchronization circuit. 7. The quadrature phase modulator according to claim 1, wherein the smoothing circuit is an injection-locked oscillator.