JPS6331810B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a master (main) CPU (Central
Processing unit = central processing unit, hereinafter simply referred to as "CPU". ) and a slave CPU started by the master CPU
This invention relates to a test control method for an apparatus.

(2) Background of the technology Normally, in this type of device, when the power is initially turned on, a test program is run to check whether the input/output devices, memory, etc. connected to the CPU are in a state where they can operate normally. It is necessary to check using

(3) Conventional technology and problems Conventionally, the slave CPU is
Checking each input/output device under the control of the CPU was started by giving a test command from the mask CPU to the slave CPU, but with this method, the connection line between the master CPU side (slave CPU) If a failure occurs in the I/O device under the control of the slave CPU and the input/output device under control of the slave CPU does not operate normally, there is a drawback that it is not possible to determine whether the failure is on the master side or the slave side. Ta.

(4) Purpose of the Invention In order to eliminate the above-mentioned drawbacks, the present invention aims to solve
The purpose of this invention is to provide a test control method for a multi-CPU device that can accurately determine whether a fault is caused by a fault occurring on the CPU side or a fault occurring on the master CPU side including the connection line. It is.

(5) Structure of the Invention That is, the present invention provides an input means for directly giving a test command to a slave CPU, and first sends a check based on a test program for hardware under control of the slave CPU from the master CPU to the slave CPU.
The test starts by outputting a test command to the CPU via the connection line, and if an abnormality is detected, the test is started by operating the input means.
The configuration is such that the slave CPU independently performs a hardware check again based on the test program.

(6) Embodiments of the Invention The present invention will be specifically described below based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing an example of a multi-CPU device to which the present invention is applied.

The multi-CPU device 1, as shown in FIG.
It has a master CPU 2, and a slave CPU 5 activated by the master CPU 2 is connected to the master CPU via a connection line 3. slave
A memory 6 storing a test program TPR and an input/output port 7 are connected to the CPU 5, and input/output devices 9A and 9 such as printers are connected to the input/output port 7.
B and switch 10 are connected.

Since the multi-CPU device 1 has the above configuration, it is connected to the slave CPU 5 and
When checking the hardware under the control of the CPU 5, that is, the memory 6 and the input/output devices 9A, 9B, etc., the master CPU 2 issues a test command TC at regular intervals or at the initial power-on.
is output to the slave CPU 5 via the connection line 3. Upon receiving the command TC, the slave CPU 5 reads the test program TPR stored in the memory 6, and checks the memory 6, input/output devices 9A, 9B, etc. based on the program TPR. As a result of the check, if any abnormality is found in the input/output devices 9A, 9B, etc., the operator presses the switch 10. Then the slave
The CPU 5 detects the press of the switch 10, reads the test program TPR from the memory 6 again, and performs the same check as described above on the input/output devices 9A, 9B, etc. under the control of the slave CPU 5, independently of the master CPU 2. Do it against At this time, if an abnormality is found in the same location as the previous check, the fault can be determined to be the relevant input/output device 9A, 9B, etc.; conversely, if no abnormality is found, It is determined that the fault exists on the master CPU 2 side including the connection line 3.

It should be noted that the switch 10 for instructing the slave CPU 5 to re-check does not need to be provided separately for instructing a check; instead, a switch that is used for other purposes during normal operation may be used for instructing a check only at the time of a check. Of course, this is a good thing.

(7) Effects of the Invention As explained above, according to the present invention, the hardware such as the memory 6 and input/output devices 9A, 9B under the control of the slave CPU 5 can be checked by first connecting the master CPU 2 to the slave CPU 5. The test starts by outputting the test command TC via the line 3, and if an abnormality is detected, the slave CPU independently controls the slave CPU by operating the switch 10 connected to the slave CPU 5.
Since the hardware connected to CPU5 is checked again, the test program
If any abnormality is detected in the hardware under the control of the slave CPU 5 based on TPR, whether it is caused by a failure in the hardware, that is, the slave CPU 5, or a failure in the master CPU 2. Slave based on the test program TPR, which can accurately determine whether
This can contribute to improving the reliability of checking the hardware under the control of the CPU 5.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a multi-CPU device to which the present invention is applied. 1...Multi-CPU device, 2...Master CPU,
3... Connection line, 5... Slave CPU, 6...
Hardware (memory), 9A, 9B...Hardware (input/output device), 10...Switch, TPR
...Test program, TC...Test command.

Claims (1)

[Claims] 1 It has a main processing unit and a sub-processing unit that starts input/output devices under its own control based on the commands of the main processing unit, and the sub-processing unit starts up the input/output devices under its control based on the commands of the main processing unit. In a multiprocessing device system in which an operation test of input/output devices under control is performed, an input means for inputting the test command to the sub-processing device without going through the main processing device is provided, and the test command from the main processing device is 1. A test control method in a multi-processing device system, characterized in that the input means causes the operation test to be performed again if an abnormality occurs in the operation test.