JPS6331815B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device for an information processing device. In particular, it relates to a device capable of storing memory words longer than the fixed word length of the memory device.

Data words and instruction words are stored in a storage device installed in a conventional information processing device, and the address and unit word length of this storage device where the data words and instruction words are stored are uniquely fixed. ing. For example, one address is fixed to one word length of 8 bits. Therefore, the word length of data words and instruction words can only be increased by a multiple of the unit word length. A data word defined with a length of two words spans two addresses,
Each bit is 8 bits, and the data length is 16 bits.

Therefore, if the required data length is 12 bits,
4 bits per data are invalid. If 128
When processing data of 128×4=
The storage device is equipped with a storage capacity of 512 bits in an unused state. This reduces the efficiency of use of the storage device, and further has the disadvantage that the storage device must be accessed twice to process one piece of data, increasing the number of program steps and processing time.

SUMMARY OF THE INVENTION An object of the present invention is to improve this drawback, and to provide an information processing apparatus that can efficiently use a storage device and reduce the number of program steps and processing time.

The present invention provides a first storage section in which a memory word of a fixed word length is stored for each address and from which the storage contents of an address designated for reading are read out, and a second storage section that has fewer addresses than the first storage section. In an information processing device comprising a part of an address of the first storage unit and a second storage unit which is designated for reading in parallel and the storage contents of the address are read out, the memory word length of the second storage unit is means for converting the address designation input in the second storage section from a corresponding part of the address designation input in the first storage section; The memory contents read from the memory section are combined with the memory contents read from the address of the first memory section which is specified for reading in parallel, and converted into information with a word length longer than the fixed word length, and this long word length information is converted into information with a word length longer than the fixed word length. The invention is characterized by comprising a control means for performing information processing.

The present invention will be explained based on the drawings.

FIG. 1 is a configuration diagram of an embodiment of the present invention. An address designation signal from a central processing unit (hereinafter referred to as "CPU") 1 is given to an address decoder 3 via an address 2. The output of this address decoder 3 is connected to a storage device 6 via a signal line 5. This storage device 6 consists of a first storage section 7 and a second storage section 9. The first storage section 7 is 4095 from address 0.
The entire range can be accessed with a memory word length of 8 bits per address. The second storage section 9 starts from address 3072 of the first storage section 7.
Addresses from address 0 to 1023, which correspond to address 4095, are numbered. Subtracted from address 3072 of the first storage section 7 and placed at address 0 of the second storage section 9,
The addresses in the first storage section are converted and assigned, such as from address 4095 to address 1023. The signal lines at addresses 0 to 1023 are connected in parallel to the corresponding signal lines at addresses 3072 to 4095 in the first storage section 7 through signal lines 5', respectively. This second storage section 9 has a memory word length of 4 bits per address, and each address can be accessed. The first storage section 7 and the second storage section 9 are constituted by ROM devices in this embodiment. The output of the first storage section 7 is sent to the CPU 1 via buses 11 and 12. The output of the second storage section 9 is sent to the CPU 1 via buses 13 and 12.

The relationship between the read operation of the above structure and the read word length bit will be explained based on FIG. FIG. 2 is a diagram showing the relationship between read address and word length. When accessing each address from address 0 to address 3071 of the first storage section 7, only the first storage section 7 is used, and data of 8-bit word length is sent to the CPU 1 via the buses 11 and 12. When accessing addresses 3072 to 4095 of the first storage section 7, when a signal is input from the address decoder 3 to each address via the signal line 5, data with an 8-bit word length is transferred from the first storage section 7 to the bus. 1
1 and 12 to the CPU 1. At this time, the signal from the signal line 5 is also input to the signal line 5', and 4-bit word length data is sent from the second storage section 9 to the CPU 1 via the buses 13 and 12. The 8-bit word length data from the first storage section 7 and the 4-bit word length data from the second storage section 9 are processed by the CPU 1 as 12-bit word length data.

Now, as a specific application example, we will explain an example in which a dot matrix type printer is controlled by a microcomputer. The character shape to be printed is assumed to be represented by a dot matrix of 12 rows and 8 columns as shown in FIG. The printing operation completes one character by printing 12 rows in parallel, 8 columns in sequence, column by column.
The number of glyph types is 128, and the glyph information is stored in the storage device. The memory word length of the storage device is
Since it matches the basic word length of the CPU instruction word,
In this example, the length of one word is 8 bits.

However, as shown in FIG. 3, the matrix of this character has 8 columns and 12 rows, so 12-bit parallel processing is required. Conventional devices allocate 2 words of storage for this purpose, and 12 of the 16 bits are allocated for this purpose.
Only bits were used. In other words, in the part where this character shape is stored, 4 bits each are wasted. According to the present invention, only the address where a glyph is stored has a word length of 12 bits, so one column of glyph data can be stored corresponding to one address, and one character's worth of data can be stored corresponding to one address. The data can be represented by 8 addresses. FIG. 4 is a diagram showing this state, starting from address 3072 in the first storage section 7.
It shows the relationship between the shape of one character stored at address 3079 and the first storage section 7 and second storage section 9 of this storage location.

Note that although the above example shows an example of a ROM device, the present invention may be implemented with a RAM device.

According to the present invention, since the storage device of the information processing device is a variable storage word length storage device that includes a first storage section and a second storage section, it is possible to improve the usage efficiency of the storage device. Furthermore, storage elements can be saved. Furthermore, it has the advantage of being able to reduce the number of program steps and processing time. Also, the address designation of the first storage section is converted and becomes the address designation input of the second storage section,
Since the address of the second storage section can be specified, it is possible to increase the storage capacity at any address of the first storage section. In particular, a memory device with one semiconductor element,
This effect is particularly evident in the one-chip microcomputer that constitutes the CPU.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention. FIG. 2 is a diagram showing the relationship between the read address and the read word length in the above example. Figure 3 is a dot matrix configuration diagram. FIG. 4 is a storage state diagram of the one-character data shown in FIG. 3 in the storage device of the above embodiment. 1...CPU, 2...Address path, 3...Address decoder, 5...Signal line, 6...Storage device, 7...First storage section, 9...Second storage section, 11
~13...Bus.

Claims (1)

[Scope of Claims] 1. A first storage section in which a memory word of a fixed word length is stored for each address and from which the storage contents of an address specified for reading are read out; In an information processing device comprising at least a part of the address of the first storage unit and a second storage unit which is designated for reading in parallel and from which the memory content at that address is read out, the memory word of the second storage unit is the length is shorter than the first memory word length, and means for converting the address designation input of the second storage section from a corresponding part of the address designation input of the first storage section; The memory content read from the memory unit is combined with the memory content read from the address of the first memory unit specified for reading in parallel, and converted into information with a word length longer than the fixed word length. An information processing apparatus comprising: a control means for performing information processing using the information.