JPS6331840B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a detector that operates a switching element in response to a change in temperature or the opening/closing of a door, etc. A detection point recognition device comprising: a plurality of child devices capable of receiving a predetermined number of switching signals from a switching device; and a parent device that recognizes which one of the plurality of detectors is receiving a switching signal. It is related to.

In general, fire alarm systems, security devices, etc. are designed to quickly notify that an abnormality has occurred at a predetermined detection point, and also to be able to clearly identify which detection point the abnormality has occurred at. What is being done is extremely important. In order to reliably perform such an important function, it is clear that the most reliable results will be obtained if an independent device is provided for each detection point. However, when attempting to centrally monitor a large number of detection points, installing an independent device for each detection point as described above is not recommended due to dimensional limitations of the device, difficulty in installation work, and cost. This is not practical from various points of view. For this reason, conventional devices have been installed corresponding to each of a large number of detection points to receive detection signals from the detection points and send detection signals to the main device for intensive monitoring, and to detect abnormalities on the main device side. A device was used that was designed to be able to recognize which detection point the detection signal was emitted from.
However, even in the conventional device for centralized monitoring as described above, there is a power line between each child device and the parent device that supplies power from the parent device to the child device to operate the circuit of the child device. Usually, it is connected by at least three conductive wires: a signal line for transmitting signals to and from the parent device, and a grounding wire. Furthermore, each slave unit was specifically equipped with a circuit that generated a discrimination signal to tell the parent unit to distinguish itself from other slave units, making the device as a whole complicated and expensive, and reducing the reliability and durability of the device. There were problems from the perspective of gender, etc. Further, if a battery is provided for each slave unit as a power source for each slave unit, the size of the slave unit becomes large and the device as a whole becomes very expensive, which is impractical.

The present invention has been made in view of the above points,
The present invention aims to provide a detection point recognition device that has an extremely simple structure, consumes little power, is inexpensive, and has excellent durability. The present invention will be made clear by describing embodiments of the present invention in detail below based on the drawings.

Figure 1 shows one parent device and an n device that receives two (i.e., 2m, m=1) switching signals.
2 is a schematic diagram showing the configuration of a slave device L of a detection point recognition device as an embodiment of the present invention having two slave devices. In FIG. 1, 10 is a connection terminal to a first conducting wire that serves as both a signal line and a power supply line led out from the parent device, which will be described in detail later, and 20 is a ground line (common potential line) led out from the parent device. It is a connection terminal to the second conducting wire. Between the two terminals 10 and 20 is a power supply circuit 30 that supplies power for the operation of the circuit of the child device L.
is provided. The discrimination pulse signal inputted from the connection terminal 10 to the first conducting wire is passed through a Schmitt trigger circuit 40 and an inverter 50 to a frequency dividing circuit 60 in the form of a flip-flop circuit that divides the frequency of the discrimination signal by 1/2. Connected to input. The output signal of the frequency dividing circuit 60 is counted by subtracting the signal, and when the count value becomes 0, the subtraction counter 71 which issues an output signal and the address code assigned to the child device L are set and the code is converted to a predetermined value. The subtraction counter 7 at the timing
1, and a gate circuit 73 (in this example, a NAND gate) that generates a pulse output in synchronization with the timing at which both the output signal of the Schmitt trigger circuit 40 and the output signal of the subtraction counter 71 coincide. Discrimination circuit 70
is connected so that it is input to the The output of the gate circuit 73, which is the output of the discrimination circuit 70, is connected to the first gate circuit G1 and the second gate circuit G2.
The complementary output of the frequency divider circuit 60 (in this example, the flip-flop circuit Q and output) are connected to each other. The drive signal that is the output of the first gate circuit G1 is connected to the switching element S1 (a contact in this example) of the external first detector and the load resistor RL ₁ in series between the terminals 10 and 20. The switching element (in this example,
The signal is connected via a resistor R to a switching circuit 81 having an NPN type transistor. The drive signal that is the output of the second gate circuit G1 is applied to a switching circuit connected between the terminals 10 and 20 by inserting the switching element S2 of the external second detector and the load resistor RL ₂ in series. A switching circuit 82 having a resistor
It is connected to be input via R'. On the other hand, resistors R ₁ and R ₂ and a capacitor C are connected between the output side of the Schmitt trigger circuit 40 and the terminal 20.
A series circuit according to the above-mentioned order is connected, and a diode D is arranged in parallel to the resistor R ₂ so as to be in a forward direction toward the capacitor C than the resistor R ₁ . The resistor R ₂ , diode D and capacitor C constitute a time constant circuit 90. The output from the connection point between the resistor _R2 and the capacitor C, which is the output of the time constant circuit 90, and the output of the inverter 50 are connected to the gate circuit GR (in this example,
A preset signal generated from the gate circuit GR at the same timing input to the NOR gate) is transmitted to the frequency dividing circuit 60 and the subtraction counter 7.
It is connected to be input to the reset input terminal of No. 1. The above is the slave device L as an embodiment of the present invention.
The structure is as follows.

FIG. 2 is a block diagram showing the structure of the main unit B of the apparatus of the present invention. In FIG. 2, 1100 is an oscillator that generates a predetermined pulse signal, and the output signal of the oscillator 100 is sent to a binary coded decimal counter 200 and a sending pulse forming circuit 300 that forms a pulse signal to be sent to the outside from the parent device B. They are connected to each input. The binary coded decimal counter (hereinafter abbreviated as B/C/D counter) 200
is also connected so that a reset pulse signal generated when the count value reaches a predetermined value is input to the reset signal generation circuit 400. The reset signals output from the reset signal generating circuit 400 are connected to be applied to the B, C, and D counters 200 and a sending pulse forming circuit 300 that forms a pulse signal consisting of a predetermined voltage pulse train. The output signal of the sending pulse forming circuit 300 is generated by amplifying the power of the signal and connecting the first conductor SL, which serves as both a signal line and a power supply line, and the second conductor, which is a ground line.
It is connected to be input to a power amplification circuit 500 that sends out to the outside through a conductor GL, and is also connected to be input to an identification circuit 600. The identification circuit 600 is connected to receive a current signal based on the current flowing through the first conducting wire SL from the power amplification circuit 500, and includes a voltage signal forming circuit 610 that converts the current signal into a voltage signal, and the sending pulse forming circuit. A reference pulse forming circuit 620 receives the output signal of 300 and forms a reference pulse, and is connected to receive the output signal of the voltage signal forming circuit 610 and the output signal of the reference pulse forming circuit 620, respectively, so that the two signals match. It is comprised of a coincidence detection circuit 630 that detects and issues a coincidence signal. On the other hand, a latch circuit 700 is added to the B, C, D counter 200 to hold the count value of the B, C, D counter 200 when the coincidence signal of the coincidence detection circuit is applied. A display 800 is connected so that the count value held at 700 is displayed. The above is the configuration of the parent device B. It should be noted that each of the slave devices L described above is connected in parallel between the first conductive wire SL and the second conductive wire GL led out from the power amplifying circuit 500, as shown in the figure.

The operation of the apparatus of the present invention described above based on FIGS. 1 and 2 will be explained in detail using the timing chart shown in FIG. In FIG. 3, each signal waveform is given the same reference numeral as the corresponding points ○I to ○○ and i ₁ , i ₂ in FIG. Incidentally, the timing chart in FIG. 3 relates to the operation of the slave device L to which "1" is assigned as the address and the address setting circuit 72 is set to "1". Further, the number at the top of this timing chart is the address number assigned to the corresponding slave unit, and the number at the next stage is the serial number of the discrimination pulse signal input from the terminal 10 of the slave unit.

The signals sent from the parent unit B to the first conducting wire SL and input to the slave unit L from the terminal 10 are a series of n signals (n is the number of detectors) as shown in Figure 3. This is a repetitive pulse signal having a rest period of a predetermined time (in this example, 15 pulses) after each voltage pulse train consisting of pulses (matched). The discrimination pulse signal (FIG. 3, ○A) consisting of this repetitive pulse signal passes through the Schmitt trigger circuit 40 and is inverted in phase by the inverter 50, as shown in FIG. 3, ○B. The output signal of the inverter 50 having a waveform as shown in ○B in FIG. get. The output signal (o) in FIG. 3 from the frequency dividing circuit 60 is subtracted and counted by a subtraction counter 71, and when the count value reaches "0", the subtraction counter 71 generates a pulse signal as shown in (o) in FIG. 3. This subtraction counter 71 includes a gate circuit which will be described in detail later.
Preset signal output from GR (Fig. 3)
The address code (in this example, "1") set in the address setting circuit 72 is preset in synchronization with the address code, and the subtraction count is performed from there. Output signal of the Schmitt trigger circuit 40 (Fig. 3)
and are input to the gate circuit 73, and a match is made between the two, and the output pulse signal of the gate circuit 73 as the output of the discriminator circuit 70 is obtained as shown in FIG. The output pulse signal of the discrimination circuit 70 (circle ○ in FIG. 3) and the output of one of the complementary outputs of the frequency dividing circuit 60 (output, circle ○ in FIG. 3) are both sent to the first gate circuit G1. The two signals are inputted and matched, and a drive signal having a waveform as shown in FIG. 3 is obtained as an output of the first gate circuit G1. Since the switching circuit 81 is driven by this drive signal (circle in FIG. 3), when the switching element S1 of the external first detector is in the "closed" state, "first conductor SL→terminal 10→ A pulse-like load current i ₁ as shown in FIG. 3 i ₁ flows through the circuit of “load resistor RL→switching circuit 81→switching element S1→terminal 20→second conductor GL”.

Similarly to the above, the difference between the output pulse signal of the discrimination circuit 70 (○C in FIG. 3) and the output of the other one of the complementary outputs of the frequency dividing circuit 60 (Q output, ○H in FIG. 3) A signal having a waveform as shown in FIG. 3 is obtained as a drive signal whose coincidence signal output is the output of the second gate circuit G2. Therefore, when the switching element S2 of the second external detector is in the "closed" state, "first conductor SL → terminal 10 → load resistance RI ₂ → switching circuit 82 → switching element S2 → terminal 20 → second A pulse-like load current as shown in Fig. 3 _i2 flows through the circuit of the conductor GL. As mentioned above, when the external detector is in the operating state (that is, in this example, the switching element of the detector is in the "closed" state), the discrimination pulse signals (voltage signals) in the order corresponding to the order of the detectors are transmitted. When the first conductor SL and the second conductor GL
During this period, a pulsed load current flows in complete synchronization with the discrimination pulse signal.

In the parent device B shown in FIG. 2, this pulse-like load current i ₁ or i ₂ is converted into a voltage signal by a voltage signal forming circuit 610 in the identification circuit 600. Then, in the coincidence detection circuit 630, the output signal of the reference pulse formation circuit 620, which is approximately synchronized with the discrimination pulse signal and whose duty cycle is smaller than this, and the output signal of the voltage formation circuit 610 are matched, and the output signal of the voltage formation circuit 610 is detected. 700 with a match signal. The latch circuit 700 holds the count value of the B/C/D counter 200 at the time of receiving the coincidence signal. Since the count value in the B, C, and D counters is the serial number of each pulse of the discrimination pulse signal sent from the first conductor SL through the sending pulse forming circuit 300 and the power amplifying circuit 500, As explained with respect to the time chart in FIG. 3, its serial number matches the number of the detector. Therefore, as described above, the active detector number is the latch circuit 70.
It is held at 0 and displayed on the display 800.
That is, the identification circuit 600 of parent device B identifies the detector in operation based on the generation of load current pulses and the timing of the generation.

The above is the operation of the device of the present invention. In this embodiment, in order to reduce the power consumption in the child unit as much as possible and to operate more reliably, a time constant circuit 90 having the above-mentioned configuration is provided, and the discriminator circuit 70 and the frequency divider circuit 60 are obtained. That is, in the time constant circuit 90, when the output of the Schmitt trigger circuit 40 (○A in FIG. 3) enters the pulse rest period (i.e., the period after the n-th pulse), the charge stored in the capacitor C is reduced. passes through a relatively large resistor R2 and then passes through a resistor R1
It then passes through the output stage elements of the Schmitt trigger circuit 40 and is gradually discharged with a large discharge time constant as shown in FIG. While this discharge is occurring, the output of the inverter 50 (Fig. 3, ○) is high.
level, and no output is obtained from the gate circuit GR (○D in Figure 3). Next, near the end of the rest period of the pulse, the output of the Schmitt trigger circuit 40 (○B in Figure 3) goes from the L level to H. Turning to the level,
The output of the inverter 50 (FIG. 3) immediately changes from the H level to the L level. At this time, the capacitor C of the time constant circuit 90 attempts to be charged with a relatively short charging time constant via the resistor R1 and the diode D in the forward direction (Fig. 3), but the voltage of the capacitor C is During the short period of time at the beginning of the rise of
The voltage does not reach the threshold voltage of the logic circuit and therefore the time constant circuit 90
The output of the inverter 50 (○C in Figure 3) and the output of the inverter 50 (○B in Figure 3) both become L level, and the gate circuit
A preset signal (○D in Figure 3) is obtained from the GR. The aforementioned preset signal is ensured each time near the end of the rest period of the pulse, thereby causing the frequency divider circuit 60 and the discrimination circuit 70 (subtraction counter 7
1) is reliably preset every time.

In the above embodiment, a 1/2 ¹ frequency divider using one flip-flop is used as the frequency divider 60, and one child unit ² is configured to receive signals from one detector. As an example of a frequency divider ^, a ^{1/2 m} frequency divider is used as a frequency divider. If ^2m gate circuits are provided that detect coincidence with one of the target output signals and output a drive signal,
The slave unit can receive signals from 2 ^m detectors.

As described above, according to the device of the present invention, the duty cycle of the discrimination pulse signal sent from the parent unit B may be constant except for the rest period. Therefore, the circuit configuration of the parent device can be extremely simplified. In addition, since the identification of an operating detector is done only by detecting the occurrence of a load current pulse and the timing of its occurrence, the slave unit must generate its own signal to identify the operating detector. There is no need for this at all, so configuration is easy.

Therefore, the power consumption of each child device is extremely small, so that the current flowing into the power supply circuit 30 in the child device is
i _PS will be extremely small. In general, in the above-mentioned device in which n slave devices are connected, when the load current flowing through the switching elements (S1, S2, etc.) of the detector in the operating state is i _L , i _L /n・i _PS = The larger the value of A in A, the easier it is to identify the detector in operation. However, in the device of the present invention, since the i _PS is minute, the value of A is sufficiently large, and the detector in the parent device is easily identified. Identification becomes very reliable. Moreover, it goes without saying that each child device can be provided at low cost. Furthermore, since the connection between the parent device and each child device is made only by the aforementioned two common conducting wires, the installation work is simple and inexpensive. This is a very great advantage in cases where the device of the present invention is to be added by using leftover cables or the like from existing equipment.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of a slave device of the device of the present invention, FIG. 2 is a block diagram showing the configuration of the master device of the device of the present invention, and FIG. 3 is a timing chart for explaining the operation of the device of the present invention. It is. L... Slave device, 30... Power supply circuit, 60... Frequency dividing circuit,
70... Discrimination circuit, 81, 82... Switching circuit, S1, S2... Switching element, RL ₁ , RL ₂
...Load resistance, 90...Time constant circuit, B...Main device, 30
0... Sending pulse forming circuit, 500... Power amplification circuit, 600... Identification circuit, 800... Display device.

Claims (1)

[Scope of Claims] 1. A plurality of slave units provided to receive a predetermined number of switching signals from detectors arranged at a plurality of predetermined points; In the detection point identification device equipped with a parent device that recognizes which detector is connected to the parent device, each of the slave devices has a first conducting wire that serves as both a signal line and a power supply line led out from the parent device. , are connected in parallel with a second conducting wire which is a grounding wire also led out from the parent device, and each of the child devices has a power supply circuit for operating its own circuit, and a power supply circuit that connects the main device to the second conductor. A frequency divider circuit that receives a discrimination pulse signal transmitted through a single conductor wire and divides the frequency into 1/2 ^m , and counts the output of the divider circuit and calculates the counted value and a preset code. and one of the 2 ^m complementary output signals obtained from the discrimination signal and the frequency dividing circuit.
2 ^m to detect a match with the signal and output a driving signal
a gate circuit, and a switching device that receives the drive signal and opens and closes a switching element connected by inserting a switching element of the detector and a load resistor in series between the first conductive wire and the second conductive wire. The configuration of the parent device includes a sending pulse forming circuit that forms a pulse signal consisting of a predetermined voltage pulse train, and a power amplifying the output pulse signal of the sending pulse forming circuit to generate a pulse signal consisting of a predetermined voltage pulse train. a load current pulse flowing through the first conductor that is generated based on the operation of the detector receiving the switching signal among the plurality of detectors; and an indicator for displaying which detector is identified by the identification circuit. A detection point identification device characterized by: 2. As the discrimination circuit, each slave device is charged in the forward direction with a relatively small time constant via a diode, and discharged with a relatively large time constant via a resistor arranged in parallel with the diode. 2. The detection point identification device according to claim 1, which is a child unit having a discrimination circuit configured to preset a counting circuit that performs the counting operation by an output of a time constant circuit having a capacitor.