JPS6331880B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and more particularly to a memory device equipped with a peripheral circuit that can be automatically diagnosed.

2. Description of the Related Art Conventionally, methods for diagnosing devices such as information processing devices include functional diagnosis, which focuses on the functions of the device to be diagnosed, and non-functional diagnosis, which focuses only on the circuit configuration.

Among these, the non-functional diagnostic method focuses on an arbitrary flip-flop in a logic circuit, traces the input signal for setting and resetting that flip-flop backwards, and detects when it reaches another flip-flop. , the device to be diagnosed is divided into such units, with a combinational circuit surrounded by the input flip-flop of the latter and the output flip-flop of the former as a unit. Next, set data in the input flip-flops for each divided combinational circuit, observe the results of that data being reflected in the output flip-flops, and diagnose the combinational circuit by comparing the expected values. . The data set in the input flip-flops during diagnosis may be created manually by human thought, but generally it is created automatically by a program.

As described above, since the non-functional diagnostic method targets the combinational circuit of the device, circuits including memory elements that cannot be divided into combinational circuits are excluded from the non-functional diagnosis. Therefore, when diagnosing the peripheral circuit of a memory element, only a manual functional diagnosis is performed.

On the other hand, diagnosis using a test program for the memory element itself involves applying worst-case patterns and other test patterns to the storage device using software.
This is read out and compared to perform the test.

Many memory elements are incorporated into electronic devices such as information processing equipment, and the number of memory elements is expected to increase in the future. However, when diagnosing memory peripheral circuits by function, it requires a lot of manual labor and time. Waste will increase. Further, since functional diagnosis requires a person who is familiar with the logic to be diagnosed and is performed manually, there is a risk of insufficient diagnosis and diagnosis errors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory device equipped with a peripheral circuit that can be easily diagnosed using automatically generated diagnostic data, in order to eliminate such conventional drawbacks.

A memory element of the present invention is a memory element having each line of an element selection signal, a write/read control signal, an address signal, an input data signal, and an output data signal. The device is characterized in that it is provided with a control circuit for extracting the contents of the address signal and stores the information of the address signal at the time of access.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a memory device showing an embodiment of the present invention.

In FIG. 1, a memory element having a storage capacity of 4 bits is shown for convenience, and the description will be made assuming that the storage circuit for storing data is a flip-flop 5.

The memory device shown in FIG. 1 includes an address decoder 1, a write control signal inversion gate 2, a data write clock signal generation AND gate 3 a data read control signal generation AND gate 4, a data storage flip-flop 5, and a data read selection gate. In addition to the AND gate 7, it is newly equipped with an address storage flip-flop 6, an address read selection AND gate 8, and an address write clock signal generation gate 9, which connect the address signals 40 and 41 to the decoder 1. This is input data to the flip-flop 6.

AND gate 3 is the memory element selection signal CS
A clock signal for the flip-flop 5 is created by inputting the write control signal WE and the output signal of the address decoder 1.

Also, AND gate 4 is AND gate 3
Instead of the write control signal WE, that signal
The same signals as those of AND gate 3 are input, except that an inverted signal of WE is input, and a read synchronization signal is given to AND gate 7.

The output of the AND gate 3 is connected to the clock terminal of the flip-flop 5, and the data signal DIN is connected to the data input terminal.
Flip-flop 5 stores information on data signal DIN when the clock is input.

AND gate 7 receives the output of flip-flop 5 and the output of AND gate 4, and
The output of the AND gate 4 selects one of the flip-flops 5 to take out the data output signal DOUT and send it out.

AND gate 9 is a memory element selection signal CS
and an inverted signal of the write control signal WE to create a clock signal for the flip-flop 6.

The output of the AND gate 9 is input to the clock terminal of the flip-flop 6, and address signals 40 and 41 are input to the data input terminal, respectively.

AND gate 8 inputs the output of data write clock signal generation AND gate 3 and the output of flip-flop 6, selects one of the flip-flops 6 by the output of AND gate 3, and generates the data output signal. Retrieve DOUT and send it out.

FIG. 2 is an explanatory diagram of the operation of FIG. 1.

"1" and "0" in FIG. 2 each indicate a truth value.

When the element selection signal CS is "0", write operations to all flip-flops 5 and 6 are prohibited, and the data output signal DOUT is "0".
It is.

When the element selection signal CS is “1” and the write control signal is “0”, the address signals 40, 4
1 selects one of the flip-flops 5, and at the same time the data output signal DOUT is taken out, the address signals 40 and 41 are respectively stored in the flip-flop 6.

When the element selection signal CS is "1" and the write control signal WE is "1", the address signal 4
Flip-flop 5 selected by 0,41
At the same time, one of the flip-flops 6 is selected and the data output signal DOUT is taken out.

As is clear from FIG. 2, in the present invention, address signal information is stored during the read operation of the memory element, and information on the address signal is stored during the write operation of the memory element.
The operational relationship is such that the information of the address signal stored during the read operation is read out.

By providing a flip-flop 6 corresponding to the address signal line, the memory element peripheral circuit can be divided into a combinational circuit using the address storage flip-flop 6 in the memory element as an output flip-flop. Circuits can also be diagnosed using automatically generated diagnostic data.

In FIG. 1, the number of address signal lines is two, but memory elements with three or more address signal lines can also be processed in exactly the same way.
An address storage flip-flop may be added corresponding to the address signal line. In addition, in FIG. 1, the address signal is stored without increasing the number of input/output signals to the memory element, but if a signal dedicated to address signal storage control is provided, the data storage flip Address signals can be stored without destroying the contents of the flop.

As explained above, according to the present invention, since a memory circuit is provided corresponding to the address signal line of a memory element, a combinational circuit is configured around the memory circuit, and peripheral circuits of the memory element are automatically created. Diagnosis can be made using the diagnostic data obtained. Therefore, non-functional diagnosis of a device in which a memory element is incorporated can be performed without any manual effort, saving labor and time and providing accurate diagnostic results.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory element showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation in FIG. 1. 1...Address decoder, 2...Inversion gate, 3, 4, 7, 8, 9...And gate,
5, 6...flip flop, A0, A1...
Address signal, WE...Write control signal, CS...
...Element selection signal, DIN...Data input, DOUT
...Data output.

Claims (1)

[Claims] 1. In a memory element having a first storage circuit that is accessed through each line of an element selection signal, a write/read control signal, an address signal, an input signal, and an output signal, a first storage circuit that stores the address signal a second memory circuit; a control circuit that takes out the contents of the second memory circuit; and a control circuit that takes out the contents of the second memory circuit; 1. A memory device comprising: a control means for reading out the address signal from the second storage circuit when data is written to the storage circuit; and a non-functional diagnosis.