JPS6331942B2 - - Google Patents
Info
- Publication number
- JPS6331942B2 JPS6331942B2 JP55161683A JP16168380A JPS6331942B2 JP S6331942 B2 JPS6331942 B2 JP S6331942B2 JP 55161683 A JP55161683 A JP 55161683A JP 16168380 A JP16168380 A JP 16168380A JP S6331942 B2 JPS6331942 B2 JP S6331942B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- substrate voltage
- substrate
- transistor
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 55
- 238000001514 detection method Methods 0.000 claims description 13
- 230000010355 oscillation Effects 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Dc-Dc Converters (AREA)
- Amplifiers (AREA)
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は基板電圧発生回路を有する半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a substrate voltage generation circuit.
従来、Ｎ（Ｐ）チヤネルIG−FET（絶縁ゲート
型電界効果トランジスタ）からなる集積回路にお
いては、基板効果を低減し、PN接合容量を減少
させ、高速動作を行なうために、半導体基板に負
（正）の電圧を外部から印加することは以前から
行なわれてきた。一方、使用電源が単一のものに
ついては、半導体チツプ上に基板電圧発生回路を
設け、チツプ自身で負（正）の電圧を発生させる
ことが行なわれるようになつた。 Conventionally, in integrated circuits consisting of N(P) channel IG-FETs (insulated gate field effect transistors), negative ( Applying a positive (positive) voltage from the outside has been practiced for some time. On the other hand, for devices that use a single power source, a substrate voltage generation circuit is provided on the semiconductor chip, and the chip itself generates a negative (positive) voltage.
第１図は前記基板電圧発生回路の従来例を示
す。この基板電圧発生回路は、発振回路１、増幅
回路２及びチヤージパンプ回路３よりなる。増幅
回路２は、電源VCCとVSS間にＤ型（デプレツシ
ヨン型）トランジスタQ1、Ｅ型（エンハンスメ
ント型）トランジスタQ2を直列接続し、同じく
電源間にＤ型トランジスタQ3、Ｅ型トランジス
タQ4を直列接続し、発振回路１の出力をトラン
ジスタQ2，Q4のゲートに接続し、トランジスタ
Q1のゲートを自己のソースに接続し、このソー
スをトランジスタQ3のゲートに接続し、該トラ
ンジスタQ3の駆動能力を高めている。チヤージ
パンプ回路３は、増幅回路２から与えられる信号
（パルス）に応じて回路点４付近に正負の電荷を
発生するキヤパシタ５と、回路点４付近に生じる
例えば正の電荷を電源VSS（接地）側に排出するＥ
型の整流用トランジスタQ5と、回路点４付近に
生じる例えば負の電荷を基板側へ導出するＥ型の
整流用トランジスタQ6を有する
この基板電圧発生回路にあつては、基板は電源
が立ち上がり、発振回路１が発振を始めるに従が
い、トランジスタQ6及び寄生のダイオードD1を
通じて負にバイアスされ始め、一担定常状態に達
した後はトランジスタQ6及びダイオードD1には、
基板電圧がリーク電圧により高くなろうとするの
を補償するだけの電流が流れるだけである。従つ
て基板電圧発生路は、一度安定状態に達した後
は、基板のわずかなリーク電流を補償する程度に
働くだけであるから、基板電圧発生回路は必ずし
も常時動作させておく必要はないものである。 FIG. 1 shows a conventional example of the substrate voltage generating circuit. This substrate voltage generation circuit includes an oscillation circuit 1, an amplifier circuit 2, and a charge pump circuit 3. The amplifier circuit 2 has a D type (depression type) transistor Q 1 and an E type (enhancement type) transistor Q 2 connected in series between the power supplies V CC and V SS , and a D type transistor Q 3 and an E type transistor connected between the power supplies. Q 4 are connected in series, and the output of oscillation circuit 1 is connected to the gates of transistors Q 2 and Q 4 .
The gate of Q 1 is connected to its own source, and this source is connected to the gate of transistor Q 3 to increase the driving ability of transistor Q 3 . The charge pump circuit 3 includes a capacitor 5 that generates positive and negative charges near the circuit point 4 in response to a signal (pulse) given from the amplifier circuit 2, and a capacitor 5 that generates positive and negative charges near the circuit point 4, and a power supply V SS (ground) to transfer, for example, the positive charge generated near the circuit point 4. E to discharge to the side
This substrate voltage generation circuit has an E-type rectifying transistor Q 5 and an E-type rectifying transistor Q 6 that directs, for example, negative charges generated near circuit point 4 to the substrate side. , as the oscillation circuit 1 begins to oscillate, it begins to be negatively biased through the transistor Q 6 and the parasitic diode D 1 , and after reaching a steady state, the transistor Q 6 and the diode D 1 become
Only enough current flows to compensate for the substrate voltage becoming higher due to leakage voltage. Therefore, once the substrate voltage generation path has reached a stable state, it only works to compensate for the slight leakage current of the substrate, so the substrate voltage generation circuit does not necessarily need to be operated all the time. be.
本発明は上記の点に着目してなされたもので、
基板電圧が或る設定電圧に達したことを検出して
基板電圧発生回路の全てまたは一部を停止させ、
また基板電圧がリーク電流により時間と共に変化
するのを検出して基板電圧発生回路を再び動作さ
せるようにすることにより、基板電圧発生回路の
平均的な消費電力を低減できる半導体装置を提供
しようとするものである。 The present invention has been made focusing on the above points,
Detecting that the substrate voltage has reached a certain set voltage and stopping all or part of the substrate voltage generation circuit,
The present invention also attempts to provide a semiconductor device that can reduce the average power consumption of the substrate voltage generation circuit by detecting that the substrate voltage changes over time due to leakage current and causing the substrate voltage generation circuit to operate again. It is something.
以下図面を参照して本発明の一実施例を説明す
る。第２図は同実施例を示す回路図であるが、こ
れは第１図のものと対応させた場合の例であるか
ら、対応個所には同一符号を付して説明を省略
し、特徴とする点のみを説明する。発振回路１
は、Ｄ型トランジスタQ7、Ｅ型トランジスタQ8、
……Ｄ型トランジスタQ11、Ｅ型トランジスタ
Q12の奇数段インバータをリング状に配置したも
ので、この発振回路１の奇数段インバータの一端
側は共通接続され、その共通接続端はＥ型トラン
ジスタQ13を介してグランドVSSに接続され、トラ
ンジスタQ13のゲートには基板電圧検出回路１１
から制御信号Ａが与えられる。基板電圧検出回路
１１は、基板電圧を検出し、その絶対値が設定電
圧の絶対値以上になつたら、制御信号Ａでトラン
ジスタQ13を遮断する。発振回路１の出力Ｂと増
幅回路２のトランジスタQ2のゲートとの間に設
けられたＤ型トランジスタQ14、Ｅ型トランジス
タQ15よりなるインバータ１２は、基板電圧発生
回路の動作停止時、必ず増幅回路２のトランジス
タQ2，Q4をオフ状態にするためのものである。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing the same embodiment, but since this is an example in which it corresponds to that in FIG. I will explain only the points. Oscillation circuit 1
are D-type transistor Q 7 , E-type transistor Q 8 ,
...D-type transistor Q 11 , E-type transistor
Q12 odd-numbered stage inverters are arranged in a ring shape, and one end of the odd-numbered stage inverters of this oscillation circuit 1 is connected in common, and the common connection end is connected to the ground V SS via an E-type transistor Q13 . , a substrate voltage detection circuit 11 is connected to the gate of the transistor Q13 .
A control signal A is given from. The substrate voltage detection circuit 11 detects the substrate voltage, and when the absolute value thereof becomes equal to or greater than the absolute value of the set voltage, the transistor Q13 is cut off using the control signal A. An inverter 12 consisting of a D-type transistor Q 14 and an E-type transistor Q 15 provided between the output B of the oscillation circuit 1 and the gate of the transistor Q 2 of the amplifier circuit 2 is always turned off when the substrate voltage generation circuit stops operating. This is for turning off the transistors Q 2 and Q 4 of the amplifier circuit 2.
第３図は第２図の回路動作を示すタイミング波
形図であり、以下この図をも適宜参照して第２図
の動作を説明する。まず電源VCCが立ち上がり、
発振回路１が発振を開始し、このため基板電圧が
或る設定電圧に達する。すると検出回路１１がそ
のことを検出し、出力Ａを高レベルから低レベル
に変化させ、従つて発振回路の出力Ｂは高レベル
となる。インバータ１２は、高レベルにある出力
Ｂを反転してトランジスタQ2，Q4をオフ状態と
し、電源VCC，VSS間に貫通電流が流れるのを防
止する。この状態では、インバータ１２が若干電
力を消費するのみである。基板電圧発生回路が動
作を停止した状態が続くと、基板電圧はリーク電
流により次第に高くなる。そして基板電圧が設定
電圧よりある程度以上高くなると、このことを基
板電圧検出回路１１が検出し、制御信号Ａを低レ
ベルから高レベルに変化させ、基板電圧発生回路
を再び動作させて基板電圧がリーク電流により高
くなろうとするのを防止するものである。 FIG. 3 is a timing waveform diagram showing the circuit operation of FIG. 2, and the operation of FIG. 2 will be explained below with reference to this diagram as appropriate. First, the power supply V CC starts up,
The oscillator circuit 1 starts oscillating, so that the substrate voltage reaches a certain set voltage. Then, the detection circuit 11 detects this and changes the output A from high level to low level, so that the output B of the oscillation circuit becomes high level. The inverter 12 inverts the high level output B to turn off the transistors Q 2 and Q 4 to prevent a through current from flowing between the power supplies V CC and V SS . In this state, the inverter 12 consumes only a small amount of power. If the substrate voltage generation circuit remains inactive, the substrate voltage gradually increases due to leakage current. When the substrate voltage becomes higher than the set voltage to a certain extent, the substrate voltage detection circuit 11 detects this, changes the control signal A from a low level to a high level, and operates the substrate voltage generation circuit again, causing the substrate voltage to leak. This prevents the current from becoming too high.
一般に、基板電圧がリーク電流により高くなつ
ていくときの時定数は、基板電圧発生回路の動作
速度に比べ充分大きなものであるから、上記のよ
うに基板電圧発生回路を常に動作させるのではな
く、一時的に動作させるようにすれば、基板電圧
発生回路における平均的消費電力を、ほとんど無
視できる程度に小さくすることができる。特に増
幅回路２では、発振回路１より大電力をを消費す
るので、増幅回路２の動作を極力停止させること
は好ましい。 Generally, the time constant when the substrate voltage increases due to leakage current is sufficiently large compared to the operating speed of the substrate voltage generation circuit, so instead of constantly operating the substrate voltage generation circuit as described above, If the substrate voltage generation circuit is operated temporarily, the average power consumption in the substrate voltage generation circuit can be reduced to an almost negligible level. In particular, since the amplifier circuit 2 consumes more power than the oscillation circuit 1, it is preferable to stop the operation of the amplifier circuit 2 as much as possible.
第４図に基板電圧検出回路１１の具体例を示
す。これは、通常の差動増幅回路と同様のもので
あるが、入力段トランジスタQ21，Q22がデプレ
ツシヨン型であり、このトランジスタQ21，Q22
のＷ／Ｌ（Ｗはチヤネル幅、Ｌはチヤネル長）の
比が異なることが特徴である。トランジスタ
Q21，Q22の一端は共通にＤ型トランジスタQ23を
介してVSSに接続され、トランジスタQ21，Q22の
他端はＤ型トランジスタQ24，Q25を介して電源
VCCに接続され、トランジスタQ24のゲートとソ
ースは増幅部２１に接続され、トランジスタQ25
のゲートとソースも増幅部２１に接続されてい
る。この第４図の回路は、基板電圧と或る基板電
圧（ここではVSS）を入力とする検出部でトラン
ジスタQ21，Q22を流れる電流の差を検出し、増
幅部２１においてこれを増幅し、制御信号Ａを出
力する。本実施例においては、トランジスタQ21
とQ23のＷ／Ｌの比を適当に選ぶことにより、設
定電圧を比較的自由に決めることができる。ここ
で、前述のような動作を行なわせるためには、こ
の設定電圧は、検出回路を用いない場合に発生す
る基板電圧よりわずかに高く設定しておかない
と、良好な基板電圧検出動作が期待できない。本
例においては、基板電圧検出回路１１の消費電力
は充分に小さくできるから、該回路１１を付加し
たことによる消費電力の増加は、充分に無視でき
る。また差動増幅回路構成であるため、Ｄ型トラ
ンジスタの閾値電圧のばらつきが設定電圧に及ぼ
す影響は、ある程度緩和される。 FIG. 4 shows a specific example of the substrate voltage detection circuit 11. This is similar to a normal differential amplifier circuit, but the input stage transistors Q 21 and Q 22 are depletion type ;
They are characterized by different ratios of W/L (W is channel width, L is channel length). transistor
One end of Q 21 and Q 22 is commonly connected to V SS through a D-type transistor Q 23 , and the other end of the transistor Q 21 and Q 22 is connected to the power supply through a D-type transistor Q 24 and Q 25 .
V CC , the gate and source of the transistor Q 24 are connected to the amplifier section 21 , and the transistor Q 25
The gate and source of are also connected to the amplifier section 21. The circuit shown in FIG. 4 detects the difference between the currents flowing through the transistors Q 21 and Q 22 in the detection section which inputs the substrate voltage and a certain substrate voltage (in this case, V SS ), and amplifies this in the amplifier section 21. and outputs control signal A. In this example, the transistor Q 21
By appropriately selecting the W/L ratio of Q23 and Q23, the set voltage can be determined relatively freely. In order to perform the operation described above, this set voltage must be set slightly higher than the substrate voltage that would occur when no detection circuit is used, otherwise good substrate voltage detection operation can be expected. Can not. In this example, since the power consumption of the substrate voltage detection circuit 11 can be made sufficiently small, the increase in power consumption due to the addition of the circuit 11 can be sufficiently ignored. Furthermore, because of the differential amplifier circuit configuration, the influence of variations in the threshold voltage of the D-type transistors on the set voltage is alleviated to some extent.
なお本発明は実施例のみに限定されるものでは
なく、種々の応用が可能である。例えば実施例で
はＮチヤネル型トランジスタを用いたが、Ｐチヤ
ネル型トランジスタを用いた回路構成等としても
よい。また実施例では、基板電圧発生回路に増幅
回路２を用いたが、これを省略した構成にするこ
ともできる。 Note that the present invention is not limited to the embodiments only, and various applications are possible. For example, although N-channel transistors are used in the embodiment, a circuit configuration using P-channel transistors may also be used. Further, in the embodiment, the amplifier circuit 2 is used as the substrate voltage generation circuit, but a configuration in which this is omitted may also be used.
以上説明した如く本発明によれば、基板電圧が
充分な電圧となつたならば、基板電圧発生回路の
動作を停止させるようにしたので、低消費電力化
された半導体装置が提供できるものである。特に
本発明は待機時（スタンドバイ時）における消費
電力を極めて小さくすることが要求されるダイナ
ミツクメモリー等において特に有効である。また
本発明の差動増幅回路は、接地電圧と基板電圧と
を比較しているため、電源電圧依存性がないもの
である。 As explained above, according to the present invention, the operation of the substrate voltage generation circuit is stopped when the substrate voltage reaches a sufficient voltage, so that a semiconductor device with low power consumption can be provided. . In particular, the present invention is particularly effective in dynamic memories, etc., which require extremely low power consumption during standby. Furthermore, since the differential amplifier circuit of the present invention compares the ground voltage and the substrate voltage, there is no dependence on the power supply voltage.
第１図は従来の基板電圧発生回路図、第２図は
本発明の一実施例の回路図、第３図は同回路の動
作を示すタイミング波形図、第４図は同回路の一
部を詳細化した回路図である。
１……発振回路、２……増幅回路、３……チヤ
ージ・パンプ回路、１１……基板電圧検出回路、
Q2，Q4，Q13……電流遮断用トランジスタ。
Fig. 1 is a conventional substrate voltage generation circuit diagram, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a timing waveform diagram showing the operation of the circuit, and Fig. 4 is a part of the circuit. It is a detailed circuit diagram. 1...Oscillation circuit, 2...Amplification circuit, 3...Charge pump circuit, 11...Substrate voltage detection circuit,
Q 2 , Q 4 , Q 13 ... Current interrupting transistors.
Claims (1)
回路と、前記基板の電圧を検出する基板電圧検出
回路と、前期基板電圧の絶対値が設定電圧の絶対
値以上になつたら前記基板電圧発生回路の動作を
停止させる停止手段とを具備し、前記基板電圧発
生回路は、発振回路、増幅回路、チヤージパンプ
回路よりなり、前記停止手段は、前記発振回路及
び増幅回路の電源間貫通電流を遮断するものであ
ることを特徴とする半導体装置。 ２ 前記基板電圧検出回路は、接地電圧と基板電
圧とを比較する差動増幅回路構成を有したことを
特徴とする特許請求の範囲第１項に記載の半導体
装置。[Scope of Claims] 1. A substrate voltage generation circuit that applies a substrate voltage to a semiconductor substrate, a substrate voltage detection circuit that detects the voltage of the substrate, and a substrate voltage detection circuit that detects the substrate voltage when the absolute value of the substrate voltage exceeds the absolute value of the set voltage. stopping means for stopping the operation of the substrate voltage generation circuit, the substrate voltage generation circuit comprising an oscillation circuit, an amplifier circuit, and a charge pump circuit, and the stopping means stopping the operation of the oscillation circuit and the amplifier circuit. A semiconductor device characterized in that it blocks. 2. The semiconductor device according to claim 1, wherein the substrate voltage detection circuit has a differential amplifier circuit configuration that compares a ground voltage and a substrate voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161683A JPS5785253A (en) | 1980-11-17 | 1980-11-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161683A JPS5785253A (en) | 1980-11-17 | 1980-11-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5785253A JPS5785253A (en) | 1982-05-27 |
| JPS6331942B2 true JPS6331942B2 (en) | 1988-06-27 |
Family
ID=15739855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55161683A Granted JPS5785253A (en) | 1980-11-17 | 1980-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5785253A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381160A (en) * | 1989-08-24 | 1991-04-05 | Juki Corp | Abnormality detecting device of magnetic coil for driving movable body |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4585954A (en) * | 1983-07-08 | 1986-04-29 | Texas Instruments Incorporated | Substrate bias generator for dynamic RAM having variable pump current level |
| JPH0750552B2 (en) * | 1985-12-20 | 1995-05-31 | 三菱電機株式会社 | Internal potential generation circuit |
| NL8701278A (en) * | 1987-05-29 | 1988-12-16 | Philips Nv | INTEGRATED CMOS CIRCUIT WITH A SUBSTRATE PRESSURE GENERATOR. |
| JPH0817033B2 (en) * | 1988-12-08 | 1996-02-21 | 三菱電機株式会社 | Substrate bias potential generation circuit |
| JPH04263194A (en) * | 1991-05-29 | 1992-09-18 | Hitachi Ltd | Semiconductor device |
| KR950002015B1 (en) * | 1991-12-23 | 1995-03-08 | 삼성전자주식회사 | Electrostatic source generation circuit operated by one oscillator |
| US5347172A (en) * | 1992-10-22 | 1994-09-13 | United Memories, Inc. | Oscillatorless substrate bias generator |
| JP5121587B2 (en) * | 2008-06-06 | 2013-01-16 | 旭化成エレクトロニクス株式会社 | Reference voltage circuit |
-
1980
- 1980-11-17 JP JP55161683A patent/JPS5785253A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0381160A (en) * | 1989-08-24 | 1991-04-05 | Juki Corp | Abnormality detecting device of magnetic coil for driving movable body |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5785253A (en) | 1982-05-27 |
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