JPS6331980B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a time division multiplex concentrator that accommodates both voice lines and data lines, and in particular to a time division multiplex concentrator system that improves the efficiency of highway usage. Regarding.

(b) Technical background FIG. 1 is a diagram showing an example of a time division multiplex concentrator to which the present invention is applied. In FIG. 1, a voice signal sent by a telephone 1 is transmitted to a subscriber circuit 3 via a voice line 2, converted into a digital signal at 64 kilobits per second, and transmitted to a time division multiplex concentrator 1.
0. On the other hand, a data signal of, for example, 32 kilobits per second sent from the data terminal device 4 is
Time division multiplex concentrator 1 transmits digital signals via data line 5 and digital subscriber circuit 6
A data signal of, for example, 8 kilobits per second transmitted to the data terminal 7 and sent out from the data terminal equipment 7 is transferred to the time division multiplex concentrator 10 via the data line 8 and the digital subscriber circuit 9.
transmitted to. The time division multiplex concentrator 10 concentrates and time division multiplexes digital signals of various information transfer rates transmitted from the subscriber circuit 3 and the digital subscriber circuits 6 and 9 through a time division multiplex concentrator channel (not shown). It is transmitted to a distribution device 12 via a highway 11 having a time slot with an information transfer rate of 64 kilobits per second.

(c) Prior art and problems In conventional time division multiplex concentrators, the time division multiplex concentrator communication path transmits all data signals of various information transfer rates from the accommodated data lines 5 and 8. The data was converted to an information transfer rate of 64 kilobits per second and transmitted to the distribution device 12 via one time slot on the highway 11. Therefore, the data signal of 32 kilobits per second transmitted from the data line 5 is repeatedly transmitted on the highway 11 twice,
Further, the data signal of 8 kilobits per second transmitted from the data line 8 is repeatedly transmitted on the highway 11 eight times, which has the disadvantage of reducing the usage efficiency of the highway 11 and the capacity of the distribution device 12.

(d) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional time-division multiplex concentrator communication path system as described above, and to realize a means for improving the utilization efficiency of highways and the capacity of distribution equipment as much as possible. exist.

(e) Structure of the Invention This object is to provide a time division multiplex concentrator that accommodates lines having various information transfer speeds, concentrates and time division multiplexes the signals of the lines, and connects the signals to a highway. It has a call memory that stores information digitized at a constant bit rate in a memory location for each line, and memory locations that are grouped according to the bits of the memory location for each line in the call memory. A holding memory that holds position information is provided, and bits at bit positions determined by the grouping of the holding memory are extracted from the information read from the call memory using the line position information sequentially read from the holding memory as an address. This is achieved by configuring a time slot for transmitting to the highway.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a time division multiplex concentrator communication path system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of input/output information of the read-only memory in FIG. 2, and FIG. 2 is a diagram showing an example of the operation process in FIG. 2. FIG. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, data signals 11 having various information transfer rates of 64 kilobits per second, 32 kilobits, 16 kilobits and 8 kilobits per second are transmitted from a digital subscriber circuit.
0 is converted to an information transfer rate of 64 kilobits per second by a rate conversion circuit 300, and then sent to a multiplexing circuit 31 together with a digitally encoded voice signal 100 of 64 kilobits per second transmitted from the subscriber circuit.
It is input to 0. The multiplex circuit 310 receives the audio signal 1
The data signal 110 whose speed has been converted to 00 and 64 kilobits per second is time-division multiplexed, serial-parallel converted into a parallel highway signal 780, and sent to the communication memory 450.
to communicate. The communication memory 450 uses the counting output 600 transmitted from the counting circuit 320 incremented by the clock signal 120 via the selection circuit 360 as address information, and the decoder 350 to which the counting output 600 is input is gated. 4
Write enable signal 6 transmitted via 00
90, the parallel highway signal 780 transmitted from the multiplex circuit 310 is sequentially written during the period in which the count output 610 indicates a logical value of 0. On the other hand, during the same period, a control unit (not shown) sends information to the call memory 4.
In order to generate address information when reading 50 at random, the line accommodation position information 140 where the audio signal 100 and data signal 110 arrive, which has been transmitted conventionally, and the audio signal 100 and data signal 110 are transmitted. Highway accommodation position information 130 specifying a time slot on the highway
In addition, division information 150 is transmitted. Division information 1
50 is an audio signal 100 and a data signal 110
Information transfer rate information (64 to 8 kilobits per second)
and insertion position information that specifies which of the 8 bits b0 to b7 in the time slot should be inserted. As shown in Figure 3, the insertion position information specifies all bits b0 to b7 in the time slot when the information transfer rate is 64 kilobits per second, and specifies bits b0 to b7 when the information transfer rate is 32 kilobits per second.
Specify b3 and any one set of bits b4 to b7,
Bits b0 and b1 for 16 kilobits per second,
One set of bits b2 and b3, bits b4 and b5, and bits b6 and b7 is specified, and in the case of 8 kilobits per second, one of bits b0 to b7 is specified. The highway accommodation location information 130, the line accommodation location information 140, and the division information 150 are held by the flip-flop group 330 in synchronization with the synchronization information 160, and are stored as the highway accommodation location information 130', the line accommodation location information 140', and the division information 150'. Output. The division information 150' is input to the read-only memory 390, and the enable signal 6 input from the synchronization circuit 340 is input to the read-only memory 390.
50, the chip select signals 680 to 687 as shown in FIG. Chip select signals 680 to 687 are connected to gates 410 to 4.
17 to the holding memories 460 to 467, and also receives the write enable signal 660 output from the synchronization circuit 340.
20 to 427 are controlled. For example, when the division information 150' specifying 64 kilobits per second and bits b0 to b7 is transmitted, the read-only memory 390 outputs chip select signals 680 to 687 with a logic value of 1, and all gates 420 to 427 are in a conductive state, all holding memories 460 to 467 store line accommodation location information 140' using highway accommodation location information 130' as address information. For example, when division information 150' specifying 8 kilobits per second and bit b0 is transmitted, chip select signals 680 to 686 with logic value 0 and chip select signal 687 with logic value 1 are transmitted from read-only memory 390. Since only the gate 427 becomes conductive, only the holding memory 467 uses the highway accommodation position information 130' as address information.
The line accommodation location information 140' is stored, but the other holding memories 460 to 466 do not store the line accommodation location information 140'. As a result, another divided information 1 whose insertion position information is bits b1 to b7
By inputting 50', other holding memory 4
60 to 466, different line accommodation location information 140' can be stored using the same highway accommodation location information 130' as address information. Next, when the count output 610 becomes a logical value 1, the selection circuit 360
and 370 are switched, and the decoder 380 also outputs a chip select signal 67 based on the count output 600.
0 to 677 are output sequentially, and gates 410 to 4 are output.
17 to the holding memories 460 to 467 in sequence. As a result, holding memories 460 to 46
7, the line accommodation position information 140' stored as address information is the output information 770, which is stored using the count output 600 transmitted via the selection circuit 370.
777 are sequentially extracted, and the selection circuit 360
The information is transmitted to the call memory 450 via the . As a result, the call memory 450 stores the transmitted output information 7
Bit information 790 to 797 stored as address information 70 to 777 is sequentially extracted,
It is transmitted to flip-flops 490-479.
On the other hand, the decoder 480 receives the input count output 60
0, the decoder output signals 800 to 807 are output sequentially based on the flip-flops 490 to 497.
to communicate. Bit information 790 extracted from the call memory 450 based on the resulting output information 770
797, only the bit information 790 is held in the flip-flop 490, and the bit information 79 extracted in the same way based on the output information 777 is stored in the flip-flop 490.
Of the bit information 0 to 797, only bit information 797 is held in flip-flop 497. Therefore, if the same line accommodation location information 140' is stored at the same address (highway accommodation location information 130') in the holding memories 460 to 467, the same address (output information 770 to 777) in the call memory 450 is stored.
=Bit information 790 to 797 stored in the line accommodation position information 140') are repeatedly extracted eight times within one time slot, and are extracted from the flip-flop 49.
All bit information from 0 to 497 790 to 79
7 is retained. In addition, the holding memories 460 to 46
7 same address (highway accommodation location information 13
0'), the bit information 79 stored in each address (output information 770 to 777 = each line accommodation position information 140') of the call memory 450
0 to 797 are sequentially extracted once within one time slot, and flip-flops 490 to 497 hold bit information 790 to 797 in units of one bit. All flip-flops 490-497
When the flip-flop 820 holds the bit information 790 to 797, the flip-flop 820 holds the output information of the flip-flops 490 to 497 at the rising edge of the inverter output signal 830 output from the inverter 810 to which the count output 610 is input, and outputs it as the highway signal 170. do.

As is clear from the above description, according to this embodiment, the audio signal 100 and data signal 110 corresponding to the line accommodation location information 140 are sent to any time slot specified by the highway accommodation location information 130 and the division information 150. any bit
For example, eight sets of 8 kilobits per second data signals 110 can be inserted into one time slot of the highway.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the information transfer rate of the data signal 110 is not limited to that shown in the figures, and many other modifications may be considered. However, the effects of the present invention do not change in either case. Furthermore, the configuration of the time-division multiplex concentrator channel system, the configuration of input/output information of the read-only memory 390, and the operation process are not limited to those shown in the drawings, and many other modifications may be considered. In this case, the effects of the present invention remain the same.

(g) Effects of the Invention As described above, according to the present invention, in the time-division multiplex concentrator, it is possible to significantly improve the highway usage efficiency and the capacity of the distribution device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a time division multiplex concentrator to which the present invention is applied, FIG. 2 is a diagram showing a time division multiplex concentrator communication path system according to an embodiment of the present invention, and FIG. FIG. 4 is a diagram showing an example of the input/output information of the read-only memory in FIG. 2, and FIG. 4 is a diagram showing an example of the operation process in FIG. In the figure, 1 is a telephone, 2 is a voice line, 3 is a subscriber circuit, 4 and 7 are data terminal equipment, 5 and 8 are data lines, 6 and 9 are digital subscriber circuits, 10 is a time division multiplex concentrator, 11 is a highway, 12 is a distribution device, 100 is an audio signal,
110 is a data signal, 120 is a clock signal, 1
30 is highway accommodation position information, 130' is retained highway accommodation position information, 140 is line accommodation position information, 140' is retained line accommodation position information, 150 is division information, 150' is retained division information, 160 is synchronization information, 170 is a highway signal, 300 is a speed conversion circuit, 310 is a multiplex circuit, 320 is a counting circuit, 330 is a flip-flop group, 340 is a synchronization circuit, 350, 380 and 480 are decoders, 360 and 370 are selections. circuit, 390 read-only memory, 400, 410
417 to 420 and 420 to 427 are gates;
50 is a call memory, 460 to 467 are holding memories, 490 to 497 and 820 are flip-flops, 600 and 610 are count outputs, 650
is an enable signal, 660 and 690 are write enable signals, 670 to 677 and 680
687 are chip select signals, 770 to 7
77 is output information of the holding memory, 790 to 797
800 to 807 are decoder output signals, 810 is an inverter, and 830 is an inverter output signal.

Claims (1)

[Scope of Claims] 1. In a time-division multiplex concentrator that accommodates lines with various information transfer speeds and connects the signals of the lines to a highway by concentrating and time-division multiplexing the signals of each circuit at a constant bit rate. a telephone memory 450 for holding information digitized in a memory location for each line; and a memory location grouped into groups corresponding to the bits of the memory location for each line in the telephone memory 450;
Holding memories 460 to 46 that hold line position information
7 is provided, and the line position information sequentially read from the holding memories 460 to 467 is used as an address to write to the call memory 4.
320, 360, 370, 380, 48 that extracts bits at bit positions determined by the grouping of the holding memory from the information read out from the information read from the bits 50, and configures time slots to be sent to the highway.
0,490 to 497.