JPS6332158B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital electronic timepiece equipped with a novel time adjustment device.

Conventionally, most digital electronic watches have displayed time information including hours, minutes, and seconds, or even the month, day, and day of the week on a single large display surface. However, in recent years, there has been a trend to incorporate digital watches into pendants and rings and use them as accessories.

However, when used as a pendant or ring, the display surface must be extremely small.
If all of the above information about hours, minutes, and seconds is displayed on that small display screen at once, the individual fonts become small and difficult to read. However, as a system for solving the above-mentioned drawbacks, the present inventor has already proposed a digital clock system in which only the unit digit of time information is displayed on a small display surface, and the time information is displayed in sequence.

An object of the present invention is to provide a time adjustment device most suitable for the digital clock proposed above.

The gist of the present invention for achieving the above object is to provide a reference oscillation circuit, a frequency dividing circuit that generates a clock signal, a clock circuit that counts the clock signal to generate time information, and a clock circuit that counts only the unit digit of the time information. In an electronic watch equipped with a displayable digital display device and a display drive circuit that sequentially displays time information on the digital display device, an externally operated correction switch and a display that stores display information when the correction switch is operated. A mode storage circuit, a correction information display means for setting the display information stored in the display mode storage circuit in a fixed display state, and a correction signal selectively supplied to the unit digit counter of the time measurement circuit designated by the correction information display means. It is characterized by having a correction selection gate for

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a digital watch according to an embodiment of the present invention. FIG. 4 is a detailed diagram of the display section expressing each display state. In FIG. 1, reference numeral 1 denotes a display device composed of a matrix liquid crystal cell. 1a allows one and a half digits of time information to be displayed in the normal flow display state. It is a dot matrix display section with 8 vertical rows and 9 columns horizontally, and 1b is an identification mark display section for displaying the unit of time information displayed on the dot matrix display section 1a.

Therefore, when hour digit information is displayed on the dot matrix display section 1a, the hour mark H representing the hour digit information is displayed on the identification mark display section 1b.
However, similarly, when the minute digit information is displayed, the minute mark M representing the minute digit information lights up.

However, Fig. 1a shows a state in which 22 o'clock information is about to be displayed in a normal time display, and the dot matrix display section 1a shows a 10 o'clock unit "2". The whole number and half of the number "2" representing one hour are displayed in sequence, and the hour mark "H" is lit on the identification mark display section 1b. It should be noted that when the hour digit information flows from the dot matrix display section 1a to the left side, the minute digit information flows in from the right side and is displayed, and correspondingly, the minute mark M is displayed on the identification mark display section 1b. Is displayed.

Also, Fig. 1b shows that by turning on an externally operable correction switch in the state of Fig. 1a,
In this state, as shown in the figure, the two digits representing the hour digit information are displayed on the dot matrix display section 1a when in the normal display state shown in Figure 1a. By changing to a smaller font, the two numbers are completely displayed within the display range and are fixedly displayed. At the same time, the hour mark "H" flashes on the identification mark display section 1b, indicating that the mode is in the hour digit correction mode.

FIG. 1c shows that the hour digits have been corrected from 22:00 to 14:00 in the hour correction mode of FIG. 1b. That is, as will be described later, by turning on the correction switch used to set the above-mentioned correction mode again in the correction mode, the display information on the dot matrix display section 1a is fast-forwarded from "22" to "14". It has just been corrected.

FIG. 1d shows the state where the display has returned to the normal display of one and a half digits. In other words, when the correction switch is operated in the correction mode and the setting is completed at the desired time, that is, 14:00, and the correction switch is turned off, the display will automatically return to the normal display after a predetermined period of time has elapsed due to the operation of the timer described later. Then, the hour mark "H" on the identification mark display section 1b returns from the blinking state to the lighting state.

Similarly, when the minute digit information is displayed on the dot matrix display section 1a and the minute digit mark "M" is lit on the identification mark display section 1b, if the correction switch is operated, the minute correction mode is entered.

The configuration of the digital electronic timepiece shown in FIG. 1 will be explained in more detail below.

FIG. 2 is a system block diagram of a digital electronic timepiece having the display shown in FIG. In Fig. 2, 2 is a reference oscillation circuit, 3 is a clock signal (φ _s )
The frequency dividing circuit 3 generates, in addition to the clock signal (φ _s ), an early correction signal (φ ₂ ) for time correction, and a timing reference signal (φ ₁ ) for correction operation.
is generated. 4 is a clock circuit that counts the clock signal (φ _s ) of the frequency divider circuit 3;

This timekeeping circuit 4 includes a second counter 4a, a minute counter 4b, and an hour counter 4c.
a and minute counter 4b, and minute counter 4b.
Correction switching gates 4d and 4e for switching between a signal for timing and a signal for correction are connected between the clock and the hour counter 4c, respectively.

1 is the display device described in FIG. 5 is
This is a display drive circuit that drives the display device 1. The display drive circuit 5 receives time information (φ _t ) from the clock circuit 4.
is input, and using the timing signal (φ _cl ) from the frequency dividing circuit 3, the hours and minutes are sequentially displayed on the dot matrix display section 1a of the display device 1 as explained in FIG. The digit of the time information in the display state is selectively displayed on the identification mark display section 1b.

Furthermore, the display drive circuit 5 has output terminals OH and OM that generate output signals according to the display contents, and these output terminals OH and OM are used when the display contents are hour digits, that is, the identification mark display section 1b. When the hour mark "H" is lit, the output terminal "OH" becomes "1", and when the display contents are minute digits,
That is, when the minute mark "M" is lit, an output is generated such that the output terminal "OM" becomes "1".

In addition, the input terminal SH provided in the display drive circuit 5,
SM is a correction display control terminal, and when "1" is input to the correction display control terminal SH, the hour digit correction state is entered, and as shown in Figure 1b, the display font is made smaller and the hour digit information is The two digits are displayed in a fixed manner, and the hour mark "H" on the identification mark display section 1b is displayed blinking. Similarly, when "1" is input to the correction display control terminal SM, the minute digit correction state is entered, the display font is made smaller, the minute digit information is fixedly displayed, and "M" in the identification mark display section is displayed blinking. .

6 is a display mode storage circuit for storing display information when the correction switch SW is operated. The display mode storage circuit 6 has two data types for storing display modes for hour digits and minute digits, respectively.
Flip-flop (hereinafter abbreviated as D-FF) 6a,
6b, which detects and stores the information of the output terminals OH and OM of the display drive circuit 5 by the ON pulse _P1 generated when the correction switch SW is operated, and when the output OH is "1" sets the D-FF6a of the display mode storage circuit 6 to set the hour digit designation signal PH to "1", and similarly, when the output OM of the display drive circuit 5 is "1", the display mode storage circuit 6 D-FF6b is set to set the minute digit designation signal PM to "1".

Reference numeral 7 denotes a switch circuit for outputting a predetermined correction operation signal by operating the correction switch SW. 7a is a chattering prevention circuit to accurately transmit the ON/OFF operation of the correction switch SW, and 7b is a circuit for preventing correction switch SW from OFF to ON.
Generates ON pulse P ₁ for operation switching to
ON differential circuit, 7c is also OFF which generates OFF pulse P ₂ for switching operation from ON to OFF.
It is a differential circuit.

7d, 7e, and 7f are RS flip-flops (hereinafter abbreviated as RS-FF), and RS-FF7e is
It is reset by the output of the ON differentiation circuit 7b, and the RS-FF 7f is reset by the output P ₂ of the OFF differentiation circuit 7c.
It has been reset by.

7g, 7h, and 7i count the timing reference signal (φ ₁ ) output from the frequency dividing circuit 3, and
These are timer circuits that generate output signals S ₁ , S ₂ , and S ₃ after a predetermined time, respectively.

Note that the output signal S ₁ is a correction mode signal for setting each component to a time correction state, and the output signal S ₂
is a correction mode release signal that releases each component from the time correction state and returns to the normal state, and the output signal S ₃ is an early correction signal (φ ₂ ) in the time correction state.
This is an early correction timing signal that specifies the timing at which .

7j and 7l are AND gates, 7k is an OR-gate, 7m is an inverter, and the output signal _S4 of the OR gate 7k is a modified input signal.

8 is a modification information display means, which displays two AND-
Consisting of gates 8a and 8b, correction mode signal S ₁
and hour digit designation signal PH or minute digit designation signal PM
Accordingly, the display drive circuit 5 is set to a corrected display state for the hour digit or minute digit.

Reference numeral 9 denotes a modified selection gate, which is composed of two AND gates 9a and 9b, and receives a modified input signal S ₄
is transmitted to the designated digit by the correction information display means 8.

Next, before explaining the operation of the digital electronic timepiece having the above configuration, the operation of the switch circuit 7 will first be described in detail with reference to the signal waveform diagram shown in FIG.

First, FIG. 3 shows the output signal of the ON differentiation circuit 7b generated in response to the operation of the correction switch SW. The timing of the ON pulse _P1 and the OFF pulse _P2 , which is the output signal of the OFF differentiation circuit 7c, will be explained.

W ₁ shown in Figure 3 A is the correction switch SW.
ON, OFF operation signal is chattering prevention circuit 7a
This is a switch signal generated as a result of passing through the . By turning on the correction switch SW, the switch signal W ₁ changes from "0" to "1", and each time, ON pulses P ₁ a and P ₁ b are generated as shown in Figure 3 (b). , conversely, by turning off the correction switch SW, the switch signal _W1 changes from “1” to “0”.
and each time it changes to OFF as shown in Figure 3 C.
Pulses P ₂ a and P ₂ b are generated.

In other words, to explain using Fig. 2, when the correction switch SW is turned on, the chattering prevention circuit 7
The switch signal _W1 , which is the output of the switch a, changes from "0" to "1", and the ON differentiation circuit 7b outputs the ON pulse _P1.
occurs. When the correction switch SW is turned OFF, the switch signal _W1 changes from "1" to "0", and after that signal is inverted by the inverter 7m, an OFF pulse _P2 is generated by the OFF differentiation circuit 7c. That's what I do.

Next, by turning on the correction switch SW, the correction mode signal _S1 is output, and the correction switch is also turned on.
By turning off the SW, the correction mode signal _S1
We will explain the operation to release the .

First, by turning on the correction switch SW, the ON differentiation circuit 7b generates the ON pulse P ₁ a and sets the RS-FF 7d as described above. As a result, the output of RS-FF7d is inverted from "1" to "0". At the same time, ON pulse P ₁ a is RS
-Reset FF7e.

As a result, the timer circuit 7g is released from reset by the output signal of the RS-FF 7d, and starts counting the timing reference signal (φ ₁ ).
After a predetermined time _t1, a correction mode signal _S1 is output as shown in FIG. 3D.

Next, when the correction switch SW is turned OFF, the OFF differential circuit 7c generates the OFF pulse P ₂ a as described above, and sets the RS-FF 7e. As a result, the output of RS-FF7e changes from “1” to “0”.
to be reversed. As a result, the timer circuit 7h outputs RS-
The reset is canceled by the output signal of FF7e, and counting of the timing reference signal (φ ₁ ) is started. Then turn off the correction switch SW.
If left in this state, a correction mode release signal _S2 is output after a predetermined time _t2 , and this correction mode release signal _S2
By resetting RS-FF7d, its output is inverted from "0" to "1". As a result, the timer circuit 7g is reset again and the correction signal _S1 is returned to "0".

As described above, when the correction switch SW is turned ON, the correction mode signal _S1 is generated after the predetermined time _t1 of the timer circuit 7g, and by turning the correction switch SW OFF, the correction mode signal S1 is generated after the predetermined time t1 of the timer circuit 7g. t ₂
Later, a modification mode release signal _S2 is generated, which releases the modification mode signal _S1 .

Next, turn on the correction switch SW at short intervals,
The operation of generating a single correction signal, which is generated by repeating the OFF operation, will be explained.

First of all, by turning on the correction switch SW, the ON differentiation circuit 7b is activated as described above.
ON pulse P ₁ a is generated, and after a predetermined time t ₁ of timer circuit 7g, correction mode signal S ₁ is generated. After that, by turning off the correction switch SW,
An OFF pulse P ₂ a is generated from the OFF differentiation circuit 7c.

As a result, the timer circuit 7h starts counting as described above, and generates the correction mode release signal _S2 after a predetermined time _{t2 .}
Turn on the correction switch SW again before
Then, the ON differentiation circuit 7b is turned on again.
Generates ON pulse P ₁ b.

The ON pulse _P1b is again supplied to the set terminal of RS-FF7d, but since RS-FF7d has already been set, the correction signal _S1 continues to be output.

At the same time, the ON pulse _P1b resets the RS-FF7e. As a result, the output of RS-FF7e is inverted from "0" to "1", and by forcibly resetting the timer circuit 7h which is in the counting operation, generation of the correction release signal _S2 is prevented and the correction state is maintained. let Since the correction mode signal S ₁ is "1", the ON pulse P ₁ b that has passed through the AND gate 7l, which is in an open state, further passes through the OR gate 7k and is single-shot corrected as shown in FIG. The signal P ₁ b is output as the corrected input signal S ₄ .

Thereafter, when the correction switch SW is turned OFF, the OFF differentiation circuit 7c generates the OFF pulse P ₂ b, and the timer circuit 7h starts counting, in the same manner as described above. However, the counting time t ₂ of the timer circuit 7h again
By turning on the correction switch SW within
As described above, the ON pulse _P1 is output as the correction input signal _S4 for single-shot correction.

As described above, by first keeping the correction switch SW ON for a predetermined time t ₁ , the correction mode signal S ₁ is output, and after turning the correction switch SW once OFF, the correction mode signal S 1 is output within a predetermined time t ₂ . Turn on the correction switch SW again, then turn it on and off for a short time
By repeating the operation, the ON pulse _P1 generated each time becomes a single correction signal according to the number of operations and is output as a correction input signal _S4 . After that, if the correction switch SW is left OFF, the timer circuit 7h starts counting by the last generated OFF pulse _P2 , and after a predetermined time _t2 , a correction mode release signal _S2 is generated. , modification mode signal
Cancel S ₁ .

Next, the operation of generating the fast forward correction signal (φ ₂ ) will be explained.

First, in accordance with the single-shot correction signal generation operation as described above, by first turning on the correction switch SW, the correction mode signal S ₁ is generated after a predetermined time t ₁ .
After that, the correction switch SW is turned OFF once, and before the predetermined time t ₂ elapses, the correction switch SW is turned ON again and a single correction signal P ₁ b is output as shown in Fig. 3 (E). .

If the correction switch SW is kept in the ON state, the RS-FF 7f will not be reset, so the operation of the timer circuit 7i will continue for a predetermined period of time.
After t ₃ , a quick correction timing signal S ₃ is generated. This early correction timing signal S ₃ opens the AND gate 7j to allow the early correction signal (φ ₂ ) to pass, and the early correction signal (φ ₂ ) further passes through the OR gate 7k. It is output as a correction input signal _S4 for quick correction shown in FIG. 3E. Thereafter, when the correction switch SW is turned OFF, the OFF pulse P ₂ b is generated from the OFF differentiation circuit 7c, as described above, and the RS-FF 7f is reset, and as a result, the output is inverted from "0" to "1".

As a result, the timer circuit 7i is reset and the early correction timing signal _S3 is released. The AND gate 7i is thereby closed and prevents the passage of the early correction signal (φ ₂ ).

One OFF pulse P ₂ b causes the timer circuit 7h to start counting as described above, and the timer circuit 7h starts counting.
h generates a modification mode release signal S ₂ after a predetermined time t ₂ and releases the modification mode signal S ₁ . As described above, by operating the correction switch SW, the correction mode signal S ₁ is output, and then by continuing to turn on the correction switch SW again, the correction input signal by the ON pulse P ₁ b is first output. S ₄ and then, after a predetermined time t ₃ , a modified input signal S ₄ based on the early modification signal (φ ₂ ) can be output.

Then, by turning off the correction switch SW, the output of the quick correction signal ( _φ2 ) is stopped, and by leaving the correction switch SW in the OFF state, the correction mode is switched on after a predetermined time _t2 . Stop outputting signal _S1 .

Shown here. The predetermined times t ₁ , t ₂ , and t ₃ are in the range of 1 to 5 seconds in a normal clock system, and in this embodiment, t ₁ =t ₂ =t ₃ =2 seconds.

Similarly, the early correction signal (φ ₂ ) was set at about 8 Hz.

Next, the operation of the digital electronic timepiece equipped with the above-mentioned switch circuit 7 will be explained.

First, the operation in the normal time display state shown in FIG. 1a will be explained.

The reference signal of the reference oscillation circuit 2 is supplied to a frequency dividing circuit 3.
and generates a clock signal (φ _s ).
In addition, in the normal time display state, the correction initial conversion gates 4d and 4e of the timekeeping circuit 4 are set so that only signals for timekeeping pass through, so that the timekeeping signal (φ _s ) is transmitted to the seconds counter 4a and the minute. counter 4b,
It is sequentially counted by the hour counter 4c and outputs minute digit information and hour digit information as a time information signal (φ _t ). This time information signal (φ _t ) is sent to the display drive circuit 5
The display driving circuit 5 causes the dot matrix display section 1a of the display device 1 to display the hours and minutes sequentially from right to left in accordance with the time information signal (φ _t ).

Furthermore, the display drive circuit 5 displays a dot matrix display section 1a on the identification mark display section 1b of the display device 1.
When the time information displayed at that time is hour digit information, the hour mark H is lit up, and when the time information displayed at that time is minute digit information, the minute mark M is lit up.

In the state shown in FIG. 1a, the display drive circuit 5, which has been outputted with hour digit information indicating that the content of the hour counter 4c of the timekeeping circuit 4 is 22 o'clock, displays the dots on the display device 1 according to the hour digit information. Matrix display section 1
22 o'clock is displayed in sequence at 22 o'clock a, and an hour mark "H" is lit on the identification mark display section 1b to indicate that it is hour digit information.

Note that, as described above, when the hour mark "H" is lit on the identification mark display section 1b, the display drive circuit 5 outputs "1" to its output OH.

Next, change the correction switch from the display state as shown in Figure 1a.
We will explain the operation of operating the SW to call up the hour digit correction mode.

First, by turning on the correction switch SW, the switch circuit 7 outputs the ON pulse P ₁ a from the ON differentiation circuit 7b as described above, and is supplied to the display mode storage circuit 6. At this time, since the output terminal OH of the display drive circuit 5 is "1" as described above, the D-FF 6a of the display mode storage circuit 6 is
As mentioned above, it is set by the ON pulse _P1a supplied to the clock terminal CL, and the hour digit designation signal PH
AND gate 8 of correction information display means 8
Open a.

The correction switch SW is kept ON, and when a predetermined time t ₁ has elapsed, a correction mode signal S ₁ is output, and this correction mode signal S ₁ causes the correction switching gates 4 d and 4 e of the clock circuit 4 to pass through the correction signal. At the same time as switching to , it passes through the open AND gate 8a of the correction information display means 8.

Modification mode signal S ₁ passed through AND gate 8a
By setting the correction display control terminal SH of the display drive circuit 5 to "1", the hour digit correction mode shown in FIG. This makes it possible to supply a modified input signal _S4 to the hour counter 4c.

Next, the operation of correcting the hour digits from 22:00 to 14:00, as shown in FIGS. 1b and 1c, after calling up the hour digit correction display state will be described.

This correction operation will be explained for the case where the time is first corrected from 10:00 to 12:00 by fast-forward correction, and then the time is corrected from 14:00 by single-shot correction.

First, as described above, by turning on the correction switch SW for a predetermined time _t1 or more, the mode is set to the hour digit correction mode. Next, when the correction switch SW is turned OFF, the timer circuit 7h operates and the correction mode is canceled when a predetermined time _t2 has elapsed, but before the correction mode is canceled. ,
When the correction switch SW is turned ON again, ON pulse P ₁ b is generated as described above, and that ON pulse
P ₁ b becomes the correction input signal S ₄ for single correction,
It passes through the open AND gate 9b of the correction selection gate 9 and inputs it to the hour digit counter 4c via the correction switching gate 4e, setting the hour digit counter 4c to 22
One step forward from 11:00 to 23:00. Then, the correction switch SW continues to be turned on, and when the predetermined time t ₃ of the timer circuit 7i has elapsed, the early correction signal (φ ₂ ) becomes the correction input signal S ₄ for early correction, and the AND gate of the correction selection gate 9 9b, and is input to the hour digit counter 4c via the correction switching gate 4e.

As a result, the hour digit counter 4c changes from 23:00 to 8
Quickly corrected by Hz signal. Then, when the correction switch SW is turned off at 12 o'clock, the correction input signal _S4 for quick correction stops.

Next, by repeating the ON/OFF operation of the correction switch SW at a time interval during which the correction mode is not released, the correction input signal _S4 for single correction generated each time the correction switch SW is turned on is used. , increments the hour digit counter 4c one by one.

In other words, by repeating the ON/OFF operation of the correction switch SW twice, the hour digit counter 4c is
It will be revised from 12:00 to 14:00. Through the above series of operations, it is possible to correct the hour digit to the desired 14 o'clock state as shown in FIG. 1c.

Next, the operation of returning to the normal time display state will be explained.

As mentioned above, when the correction switch SW is turned OFF after completing the necessary corrections, the correction mode release signal S ₂ is activated after a predetermined time t ₂ by the operation of the timer circuit 7h.
As a result of this occurrence, the correction mode signal _S1 is canceled, and the correction switching gates 4d and 4e return to the state in which they pass the clock signal.

Furthermore, when the modification information display means 8 is closed, the modification selection gate 9 is also closed, and the modification display control terminal SH connected to the output of the modification information display means 8 becomes "0". Then, the display drive circuit 5 returns to the normal time display state, and the display device 1
restarts the time flow display as shown in FIG. 1d. The correction operation of the hour digits has been explained above, but the same applies to the minute digits. “1”
At this time, by operating the correction switch SW, the minute digit correction mode can be called up and corrected.

As described above, the present invention provides a small digital display device capable of displaying only unit digits of time information and one correction button, so that during normal watch operation, the digital display device can display time information. In addition to displaying unique time information by displaying a sequence of digits and identification marks, when correcting time information, this sequence display can be used as a function to select the correction digit, and select the desired time information from the sequentially displayed time information. The unit digit to be displayed is fixedly displayed using the correction button, and the fixedly displayed unit digit is then corrected using the correction button.
In addition to making it possible to adjust the time with ease of operation using only one operation button, the display device is smaller and the number of operation members is reduced, increasing the degree of freedom in design selection for electronic watches and further reducing costs. Many effects can be obtained, such as making it possible to

[Brief explanation of the drawing]

Each of the drawings shows a digital watch according to an embodiment of the present invention, and FIG. 1 is a detailed view of the display section expressing each display state. FIG. 2 is a system block diagram, and FIG. 3 is a signal waveform diagram of the switch circuit shown in FIG. 2. DESCRIPTION OF SYMBOLS 1... Display device, 2... Reference oscillation circuit, 3... Frequency divider circuit, 4... Timing circuit, 5... Display drive circuit, 6... Display mode storage circuit, 7... Switch circuit, 8... Correction information display means, 9... Correction selection gate.

Claims (1)

[Claims] 1. A reference oscillation circuit, a frequency dividing circuit that generates a clock signal, a clock circuit that counts the clock signal and generates time information, a digital display device that can display only unit digits of time information, and a digital display device that displays time information. In a digital electronic watch equipped with a display drive circuit that sequentially displays the following information, a correction switch that is operated from the outside, a display mode storage circuit that stores display information when the correction switch is operated, and a display mode storage circuit that stores information stored in the display mode storage circuit. The present invention is characterized by comprising a correction information display means for setting display information in a fixed display state, and a correction selection gate for selectively supplying a correction signal to a unit digit counter of a time measuring circuit designated by the correction information display means. A digital electronic clock.