JPS6332295B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In diversity reception where there is a difference in antenna gain between diversity antennas, the present invention is aimed at increasing the received electric field level in a time-division manner using one receiver in order to achieve the best diversity reception. The present invention relates to a diversity receiving device suitable for use in a vehicle and configured to select one antenna from the other.

Normally, when receiving an in-vehicle FM radio, multipath and skip noise occur due to mutual interference between directly arriving radio waves and radio waves that arrive after being reflected from buildings, mountains, etc. Therefore, the electric field is generally low at points where interference such as multipath or skip noise exists.

In a diversity receiving device that selects the antenna with the stronger reception level for reception, if the diversity antenna gains are the same, it is possible to select the antenna with the stronger electric field and receive better reception with less interference. When there is a gain difference between the diversity antennas, if the antenna with lower antenna gain receives good radio waves with a strong electric field, and the antenna with higher antenna gain receives radio waves with weak electric field and many interferences. If you think about it, the lower the antenna gain, the lower the reception level, and as a result, you often receive radio waves with a lot of interference. This is a malfunction, and to solve this problem, an amplifier is generally installed in the low-gain antenna to compensate for the gain difference. There are problems with distortion and high cost.

The present invention eliminates the above-mentioned drawbacks of the prior art by performing gain differentiation of diversity receiving antennas within a diversity control circuit.

Embodiments of the diversity receiving apparatus of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 and 2 are antennas for diversity reception, and 3 is the antenna 1 and 2.
29 is a control terminal for switching, 4 is a tuner circuit of receiver 28, 5 is an intermediate frequency amplification circuit, 6 is an FM detection circuit, 7 is an impulse noise limiting circuit for removing noise generated in the ignition system of an automobile, 8 is a stereo demodulation circuit, 9 is a power amplifier circuit, and 10 is a speaker.
Reference numeral 11 denotes a reception level detection terminal for extracting an output according to the reception level from the intermediate frequency amplification circuit 5; 27 an antenna gain correction circuit connected to the terminal 11 and correcting the antenna gain difference between the antennas 1 and 2;
12 is connected to the antenna gain correction circuit 27, and in order to obtain reception level detection outputs corresponding to the antennas 1 and 2, the antennas are controlled in a time-division manner by clock pulses from a clock pulse circuit 20 of the control circuit 19, which will be described later. A first sample switch 13 detects the reception level of the antennas 1 and 2 by switching the antennas 1 and 2, and detects the reception level corresponding to the reception electric field level in the state immediately before the switching. Similarly, the second
a sample switch 14, a first sample and hold circuit for accumulating (memorizing) a reception level corresponding to the reception electric field level of the antenna immediately before switching obtained by the first sample switch 12;
15 is a second sample and hold circuit for storing (memorizing) the reception level corresponding to the reception electric field level of the antenna immediately after switching obtained by the second sample switch 13, and 16 is the reception level obtained immediately before switching the antenna. To compare the level of the first sample-and-hold circuit 14 that stores the reception level corresponding to the electric field level with the level of the second sample-and-hold circuit 15 that stores the reception level that corresponds to the reception electric field level immediately after antenna switching. 17 is a pulse circuit that generates a pulse only when the level of the first sample and hold circuit 14 is higher than the level of the second sample and hold circuit 15 based on the result of the comparison circuit 16, and 18 is a pulse circuit that will be described later. This is a drive circuit consisting of a flip-flop circuit that receives pulse signals from the circuit 23 and the pulse circuit 17 to switch or return the antenna, and its output is sent to the antenna gain correction circuit 2.
7 and the control terminal 29 of the changeover switch section 3 as a switching drive signal.

Reference numeral 19 denotes a control circuit for adjusting timing in order to operate the circuits of the above-mentioned parts normally. In this control circuit 19, in response to the clock pulse from the clock pulse circuit 20, the pulse circuit 2
1, a reset pulse is given to the first sample and hold circuit 14. At the same time, at the same timing as the reset pulse, a pulse having a slightly longer duration than the reset pulse is applied to the control terminal 30 via the pulse circuit 22 in order to turn on the first sample and hold circuit 12.

The pulse circuit 23 is connected to the pulse circuit 22, and provides a pulse for antenna switching to the drive circuit 18 when the pulse of the pulse circuit 22 ends.
Further, the delay circuit 24 is connected to the pulse circuit 21, and the drive circuit 18 switches the antenna 1 or 2 to adjust the antenna gain via the tuner circuit 4, the intermediate frequency amplification circuit 5, and the reception level detection terminal 11. The time until the reception level corresponding to the reception electric field level after antenna switching appears in the output of the correction circuit 27 is delayed. Pulse circuit 2
5 is connected to the delay circuit 24 and provides a reset pulse to the second sample and hold circuit 15. At the same time, at the same timing as the reset pulse, a pulse with a slightly longer duration than the reset pulse is sent to the control terminal 31 via the pulse circuit 26 in order to turn on the second sample switch 13.
give to

The above components 12 to 19 and 27 constitute a control section of the diversity receiving apparatus.

Next, the operation of the diversity receiver configured as described above will be explained using the signal waveform diagrams of FIGS. 1 and 2. Note that the signals a to i shown in FIG. 1 correspond to the waveforms a to i in FIG. 2. Now, assuming that there is a gain difference between antenna 1 and antenna 2, and that antenna 1 has a higher gain, and assuming that switch section 3 is connected to antenna 1 and reception is performed using antenna 1, then The output of the antenna is sent to FM via tuner circuit 4 and intermediate frequency amplification circuit 5.
Sound is generated from a speaker 10 through a detection circuit 6, an impulse noise limiting circuit 7, a stereo demodulation circuit 8, and a power amplification circuit 9.

On the other hand, a signal corresponding to the reception level is output to the terminal 11. Further, the control circuit 19 is controlled by the clock pulse circuit 20 every 5 to 30 msec as shown in Fig. 2a.
A clock pulse a is generated, which causes the pulse circuits 21, 22, 23, 25, and 26 to operate in conjunction with each other. That is, in response to the clock pulse a from the clock pulse circuit 20, the pulse circuit 21 operates as shown in FIG.
Generate a pulse b with a width of about 2 μsec as shown in
The first sample and hold circuit 14 is reset. At the same time, the pulse circuit 22 generates a pulse c as shown in FIG.

By doing this, the first sample switch 12 is turned on, and the reception level of the antenna 1 is transferred to the first sample and hold circuit 14, which has been reset in advance, to the switching section 3, the tuner circuit 4, and the intermediate frequency signal. an amplifier circuit 5, a reception level detection terminal 11, an antenna gain correction circuit 27,
Antenna 1 via first sample switch 12
A reception level corresponding to the reception electric field level of is stored. At this time, the antenna gain correction circuit 27 has a gain corresponding to the antenna 1. When this is completed, the pulse circuit 23 connected to the pulse circuit 22 generates a pulse d having a width of about 1.5 μsec as shown in FIG.
As a result, the drive circuit 18 operates to apply a control signal to the control terminal 29 of the changeover switch section 3, and the changeover switch section 3 operates to provide the control signal to the control terminal 29 of the changeover switch section 3.
and switch to antenna 2. Therefore, receiver 2
8 starts receiving with antenna 2. At this time, of course
The reception level of the antenna 2 also begins to appear at the terminal 11 for reception level detection. However, it takes about 5 μsec to switch to antenna 2 and the reception level of antenna 2 appears on terminal 11 for reception level detection.
There is a time delay of 20μsec. A pulse circuit 21 to a delay circuit 24 are provided to match this time delay. Approximately from the pulse circuit 25 connected to this
A pulse e having a width of 1 μsec is generated to reset the second sample and hold circuit 15. At the same time, the pulse circuit 26 generates a pulse g with a width of approximately 5 μsec, which is slightly longer than the pulse circuit 25, and the second
Control terminal 31 of sample switch 13
Add to. Then, the second sample switch 13 is turned on, and the level received by the antenna 2 is transferred to the changeover switch section 3, the tuner circuit 4, and the intermediate frequency in the same way as the first sample hold circuit 14 and the first sample switch 12. A reception level corresponding to the reception electric field level of the antenna 2 is stored in the second sample and hold circuit 15 via the amplifier circuit 5, the reception level detection terminal 11, and the antenna gain correction circuit 27. At this time, the antenna gain correction circuit 27 has a gain corresponding to the gain of the antenna 2, that is, the gain of the circuit is increased by the gain difference between the antennas 1 and 2. FIG. 2f shows the state of the output voltage of the antenna gain correction circuit 27 via the reception level detection terminal 11 when switching from the antenna 1 to the antenna 2 described above. In operation, as shown in FIG. 2i, antenna 1 has a higher received electric field level.

The comparison circuit 16 compares the reception level corresponding to the reception electric field level of the antenna 1 stored in the first sample and hold circuit 14 with the reception level corresponding to the reception electric field level of the antenna 2 stored in the second sample and hold circuit 15. Add to input A and input B respectively. This comparison circuit 16 compares the levels of input A and input B. As a result, if the level of input A is higher than the level of input B, pulse h is generated from pulse circuit 17 and applied to drive circuit 18 . As a result, the drive circuit 18 determines that the received electric field level of the antenna 1 immediately before switching is higher than the received electric field level of the antenna 2 immediately after switching, and gives a control signal to the control terminal 29 of the changeover switch section 3 to switch back to the antenna 1. . Here, if the level of input B of the comparison circuit 16 is higher than the level of input A (in the case of operation)
Since the pulse circuit 17 does not generate pulses and the drive circuit 18 does not operate, the antenna is not switched and the antenna 2 remains the same. This antenna selection processing time is approximately 20 μsec. Then, the clock pulse circuit 20 waits until the next clock pulse a arrives (5 to 30 msec).
The selected antenna is connected to the receiver 28 to receive the signal, and at the next clock pulse a, by repeating the antenna selection operation described above, the antenna with the high received electric field level is selected and received. In other words, this device temporarily switches the antenna, and if the receiving electric field level of the antenna before switching is high, it immediately returns to the original state, and also if the receiving electric field level of the antenna that was temporarily switched is high. is a method of receiving the data as is. Therefore, in the explanation, the reception level of antenna 1 is determined by the first sample and hold circuit 1, using antenna 1 as a reference.
4, but this indicates that antenna 1 was used before the antenna was temporarily switched.If antenna 2 was used before the antenna was temporarily switched, then the first sample and hold circuit 1
4 stores a reception level corresponding to the reception electric field level of antenna 2. That is, the first sample and hold circuit 14 temporarily stores the reception level corresponding to the reception electric field level immediately before the antenna switching, and the second sample and hold circuit 15 temporarily stores the reception level corresponding to the reception electric field level immediately after the antenna switching. Store levels.

Furthermore, although the explanation has been given for the case where the antenna 1 has a higher gain than the antenna 2, even in the reverse case, the operation is exactly the same except that the gain of the antenna gain correction circuit is reversed.

In addition, in this device, the antenna is switched periodically using the clock pulse a, so switching noise occurs due to the switching, but this is caused by the receiver 2.
The impulse noise limiting circuit 7 in 8 can treat and remove the ignition noise in the same way as the ignition noise of a car, thus making it possible to receive good reception.

FIG. 3 shows a specific embodiment of the main part of the present invention. This is the part of the control section 32 shown by the dotted line in FIG.
corresponds to the clock pulse circuit 20 in FIG.
The inverter 34, the NAND gate 35, the inverter 36, and the reset transistor 37 are the first
This corresponds to the pulse circuit 21 in the figure. Oneshot・
The multivibrator 38 is the pulse circuit 2 in FIG.
Corresponds to 2. Inverter 39, NAND gate 40, and NAND gate 41 correspond to pulse circuit 23 in FIG. One-shot multivibrator 42 corresponds to delay circuit 24 in FIG.

The NAND gate 43, inverter 44, and reset transistor 45 are connected to the pulse circuit 25 in FIG.
corresponds to NAND gate 46 and inverter 47 correspond to pulse circuit 26 in FIG. Analog switch 48 corresponds to first sample switch 12 in FIG. The operational amplifier circuit 49, the peak hold diode 50, and the operational amplifier circuit 51 are the same as the first sample hold circuit 14 in FIG.
corresponds to Analog switch 52 corresponds to second sample switch 13 in FIG. The operational amplifier circuit 53, the peak hold diode 54, and the operational amplifier circuit 55 correspond to the second sample hold circuit 15 in FIG. Inverter 56, analog switches 57, 58, and operational amplifier circuit 5
9 corresponds to the comparison circuit 16 in FIG. Inverters 60, 62 and NAND gates 61, 63 are the first
This corresponds to the pulse circuit 21 in the figure. Flip-flop circuit 64 corresponds to drive circuit 18 in FIG.
In addition, the operational amplifier circuit 65 and the analog switch 66
is a buffer amplifier/antenna gain correction circuit 27 of FIG. 1 which connects the reception level detection terminal 11 of FIG. 1 and the control section 32 of FIG. 3 to derive the reception level. Moreover, in this case, since the potential relationship between the receiving level of the receiver and the terminal 11 for detecting the receiving level is of opposite polarity, that is, when the receiving level increases, the electrons at the terminal 11 decrease. 49 has reverse polarity to return it to positive polarity. Further, even if the input polarity of the operational amplifier circuit 59 corresponding to the comparator circuit is reversed by operating with the opposite polarity, exactly the same effect will be obtained.

Also, the connection points of the parts corresponding to the control circuit 19 in FIG. 1 are slightly different in FIG. 3, but this is because the timing is exactly the same as the control circuit 19 in FIG. 1. It goes without saying that these connection relationships can be changed in any way as long as the timing relationship shown in FIG. 2 is maintained.

As is clear from the above explanation, the present invention enables reception by selecting an antenna with a high receiving electric field level even when there is a periodic antenna gain difference due to clock pulses in one receiver, which is economical. The present invention is also advantageous, and it is possible to realize a diversity receiving device that is particularly effective against skip noise, picket fencing, and multipath in car-mounted FM radio receivers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment of the present invention.
FIG. 2 a, b, c, d, e, f, g, h, and i are timing diagrams of signal waveforms of each part in FIG. be. 1, 2... Antenna for diversity reception,
3... Selector switch section, 11... Terminal for detecting reception level, 12... First sample switch, 1
3... Second sample switch, 14... First sample hold circuit, 15... Second sample hold circuit, 16... Comparison circuit, 17... Pulse circuit, 18... Drive circuit, 19... control circuit,
27...Antenna gain correction circuit, 32...Control unit.

Claims (1)

[Claims] 1. A plurality of antennas for diversity reception with different gains, a changeover switch section that selects the antennas, a receiver to which the antenna output from the changeover switch section is given, and a reception level provided in the front receiver. a diversity reception control section that controls the changeover switch section in response to an output from a detection terminal via an antenna gain correction circuit; an antenna gain correction circuit that corrects the gain in synchronization with the state of the changeover switch; a drive circuit that drives the changeover switch section; a sample switch for inputting the output of the reception level detection terminal before and after switching the antenna to either one of the first and second sample and hold circuits, respectively; and a comparator for comparing the output levels of the second sample and hold circuit, and the output thereof is applied to the drive circuit to drive the changeover switch and the antenna gain correction circuit,
The sample switch, the first and second sample hold circuits, and the drive circuit include clock pulses and reset pulses that operate the sample switch, and a pulse generation circuit that generates control pulses for the sample switch. A diversity receiving device characterized by being configured to automatically switch to an antenna.