JPS6333176B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly, to an integrated circuit device in which an output signal from a built-in circuit under test (ROM or similar circuit) is extracted for test checking.

In recent years, integrated circuit devices, especially logic integrated circuit devices, have a remarkable tendency to include a programmed ROM (read-only memory) in the device to perform each function in order to cope with the complexity of the functions. On the other hand, manufactured integrated circuit devices are tested to see if they function normally before being shipped, and non-defective products are sorted out. Testing has also become more complex, and the testing time per device has become enormous, increasing the cost of the devices.

In order to deal with this situation, various measures have been taken to shorten the test time, and in particular, for integrated circuit devices that have a built-in ROM programmed as described above, it is necessary to check the output signal of the ROM. It is known that the idea is to promote labor savings in functional testing. That is, this is
This method attempts to test most of the functionality by checking whether the output of all bits of the ROM is normal across all addresses being decoded within the device, reducing test time considerably. can be expected.

By the way, when implementing such a ROM check method, since it is a built-in ROM, the output signal of the ROM is usually not output to the output terminal of the device, so it is necessary to check the ROM in some way.
The output of all bits must be taken out of the device. Therefore, either provide a dedicated test output terminal, or
Or use the normal output terminal to output ROM
The problem here is that the output signals of all bits of the ROM must be extracted. Therefore,
Due to limitations on device chip size and number of input/output terminals.
Of course, it is not possible to provide the same number of test terminals as the number of bits in the ROM, and the normal output terminals are
There is no guarantee that there are more bits than the number of bits in ROM. This means that it is difficult to output all bits in parallel. Furthermore, when attempting to take out the output of all bits of the ROM in parallel, a disadvantage arises in that signal wiring is required to transmit the bit-number of signals from the ROM section to the output terminal section.

For convenience of explanation below, the integrated circuit device is
Limited to CMOS-LSI (complementary metal oxide semiconductor large-scale integrated circuit), such logic LSI
Let me describe the general configuration of the built-in ROM. The ROM built into this CMOS-LSI is a so-called dynamic synchronous ROM, which divides time into precharge time and logic time to take advantage of its chip size, and performs logic using only a single channel. It is often a composition. In such a configuration, the output of each bit of the ROM must be taken out as an output latched by an appropriate timing pulse.

When implementing a circuit that converts each bit output of the ROM into a serial signal for ROM check in a CMOS-LSI that has a built-in dynamic synchronous ROM as described above, it is simply an extension of the conventional technology. If we consider a circuit as follows, the configuration will be as shown in the circuit example shown in FIG. The circuit shown in FIG. 1 will be briefly explained with reference to the time chart shown in FIG. Incidentally, FIG. 2 is a timing chart at the time of ROM check, and the logic is written in negative logic with the ground level being logic "0" and the -V _DD (V _DD >0) level being logic "1". Now, as shown in Figure 2, when the precharge pulse φ _ROM is at logic "0", the N channel transistor for precharge is
N ₁ , N _{2 .} . . Precharge node R ₁ ^* of each bit of the ROM charged to logic “1” level by N _o ,
R ₂ ^* ,...R _o ^* operate according to the respective logic of each bit of the ROM at the same time that the precharge pulse φ _ROM becomes logic "1" level and each N channel transistor N ₁ to _No is turned off. The logic level is determined to be "1" or "0" until the latch pulse φ _L shown in FIG. 2 is output. after that,
The potential of each precharge node R ₁ ^* to R _o ^* is latched to the latch circuit L ₁ to _{L o} by the latch pulse φ _L , and the output from the latch circuit L ₁ to L _o is
Each bit of the ROM is output as R ₁ to _{R o} . At the same time, a logic "1" write control pulse φ _W is applied to the shift registers S ₁ to _{S o} prepared for each bit in order to convert the ROM output from parallel to serial at the timing shown in Figure 2. At the same time, immediately after that, the shift pulse φ _{S1 shown} in _{FIG .}
~ Stored within S _o . After that, the write control pulse φ _W becomes logic “0”, and each shift register S ₁ to
Since it is prohibited to write the output data R ₁ to R _o of the ROM to S _o , the data stored in the shift registers S ₁ to _{S o} are processed by the shift pulses φ _S1 and φ _S2 shown in FIG.
Move sequentially through shift registers S _o ~ _{S 1} by
As shown in FIG. 2, the data is taken out as serial data in the order of R ₁ , R ₂ . . . _Ro data from the output end of the final stage shift register S ₁ .

As explained above, when a commonly used parallel-to-serial conversion circuit is applied to ROM check, the output signal of each bit of ROM
A switching control circuit and a shift register using shift pulses φ _S1 and φ _S2 are required for each bit of the ROM when writing R ₁ to Ro and when shifting data in shift registers S ₁ to _{S o .} The required circuitry occupies a considerable amount of area on the chip.

The present invention was made in view of the above circumstances, and
By using a circuit configuration in which the latch circuit for each bit output of the circuit under test is shared as a write circuit for the shift register for parallel/serial conversion,
It is an object of the present invention to provide an integrated circuit device capable of efficiently converting the output of a circuit under test from parallel to serial while suppressing an increase in chip area.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows an example of a circuit built into the integrated circuit device of the present invention, in which LS ₁ to _{LS o} are provided corresponding to each bit 1 to n of the ROM, and latches the output of each of these bits. This is a latch shift circuit that performs a shifting operation and serves as a parallel-to-serial conversion shift register. The latch shift circuits LS ₁ to _{LS o} have their sources connected to the power supply -V _DD and their drains connected to each bit output terminal of the ROM, and each bit output terminal is controlled by a precharge pulse φ _ROM applied to the gate. An N-channel transistor N ₁ for precharging whose precharge potential is the precharge node R ₁ ^* ~ R _o ^* .
-N _o and a first latch circuit L 1 -L _o which is connected to the precharge node R ₁ ^* - R _o ^* and latches each bit output ₁ -n of the ROM by means of a latch pulse φ _L.
The shift pulse φ S is connected to the output terminals of the first latch circuits L ₁ to L _o , respectively, and only when the logic “1” write control pulse φ _W is applied, the shift pulse φ _S (this pulse is connected to the above latch pulse φ _L phase is different from that)
The second latch circuit L ₁ ', L _o ' takes in the outputs from the first latch circuits L _{1 -L o} . The outputs of the first latch circuits L ₁ to L _o are as follows:
When the write pulse φ _W is logic "0", each bit 1 to n of the ROM is taken out as output data R ₁ to R _o . Furthermore, by using the pulses φ _L and _{φ S} applied to the first and second latch circuits L ₁ to _{L o ,} L ₁ ' to L _o ' of the latch shift circuits LS 1 to _{L o} as shift pulses, these The first and second latch circuits L ₁ to _{L o} , L _{1 ′} to _{L o ′} are operated as shift registers. Serial data of each bit of the ROM can be obtained from the output terminal of the corresponding circuit _LS1 . Furthermore, among the first latch circuits L ₁ to _{L o} , the circuit L _o corresponding to the last of the latch shift circuit array is a ROM.
is connected to the n-bit output terminal of the latch pulse φ _L
a clocked inverter CI ₁ driven by
It is equipped with two stages of inverters I ₁ and I ₂ connected in series to this clocked inverter CI ₁ , and a clocked inverter CI ₂ connected in parallel with this inverter I ₁ and driven by an inverted latch pulse _L. .
The first latch circuits L ₁ to _{L o-1} other than the above latch circuit L _o are latch shift circuits corresponding to the bit output of the corresponding ROM and the adjacent bit, respectively.
A NAND circuit NA 1 which receives the outputs of LS ₂ to _{LS o} (corresponding to the outputs of the second latch circuits L ₂ ′ to L _o ′) and is driven by a latch pulse φ _L and the same inverters I ₁ and I as described _above . ₂ and a clocked inverter CI ₂ . Further, the second latch circuits L ₁ ′ to L _o ′
are the corresponding first latch circuits L ₁ to L _o
output (corresponds to the output of inverter I ₂ , also ROM
A NAND circuit NA ₂ is driven at the timing of the shift pulse φ _S in response to the bit output data R ₁ to _{R o} ) and the reverse phase signal _W of the write control pulse φ _W.
It consists of

Next, the operation of the apparatus configured as described above will be explained with reference to the time charts of FIGS. 4 and 5. Note that FIG. 4 is a time chart during normal operation, and FIG. 5 is a timing chart during ROM check. First, during normal operation, the write control pulse φ _W is always at logic “1”.
Shift pulse φ _S in latch shift circuit LS ₁ ~ _{LS o}
The outputs of the second latch circuits L ₁ ′ to L _o ′ (corresponding to the output of the NAND circuit NA ₂ ) driven by are always “1”.
It is becoming. Therefore, the first latch circuits L ₁ to _{L o-1 are not affected by the above output, and the fourth latch circuits L 1 to L o-1} are not affected.
As shown in the figure, the potentials of nodes R ₁ ^* to R _o ^* precharged by the precharge pulse φ _ROM are latched by the first latch circuits L ₁ to L _o by the latch pulse φ _L , and the ROM bit output data R ₁ is generated. ~ As R _o
Outputs normal ROM data. In this case, the drive timing pulse φ _S of the second latch pulses L ₁ ' to _{L o} ' may be always at logic "1" or may be a pulse having a waveform as shown in FIG.

Next, the operation during ROM check will be explained. In this case, the timing pulses φ _L and φ _S have waveforms with mutually different phases as shown in FIG. 5, and act as shift pulses corresponding to the conventional pulses φ _S1 and φ _S2 . Furthermore, this pulse φ _L also plays the role of a latch pulse that latches each bit output of the ROM. The details will be explained below.

(1) When the precharge pulse _φROM shown in FIG. 5 is at logic “0”, the N-channel transistor N ₁ ~
The negative charges at ^the nodes R ₁ ^* to R _{o *} of each bit of the ROM charged by turning on the transistor N ₁ to N _o at the timing when the pulse φ _ROM changes to logic “1” At the same time, depending on the logic of each bit in the ROM, the battery may be discharged or remain undischarged. Depending on whether or not this negative charge remains at each node R ₁ ^* to R _o ^* , the nodes R ₁ ^* to _{R o} ^* for each bit change when the pulse _φROM is logic “1”. Outputs a logical value according to the logical content.

(2) The time it takes for the logic value of each bit of the ROM to be determined is determined by the latch shift circuit _LS1 , which operates as a parallel/serial conversion register for the ROM output.
The write control pulse φ _W to ~LS _o is at logic " _{1 "} as shown in FIG.
The output of L _o ' (NAND circuit NA ₂ ) shows logic "1". At this time, the shift pulse φ _S that drives this NAND circuit NA ₂ becomes a logic “1” for a certain appropriate time from the time when the write control pulse φ _W becomes a logic “1” as shown in FIG. There is.

(3) The write control pulse φ _W is logic “1” and the drive pulse φ _L of the first latch circuit L ₁ to _Lo
When becomes logic "1", one input of NAND circuit NA ₁ all indicates logic "1" as mentioned in section (2), and the other input R ₁ ^* ~ R _o-1 ^* teeth
As mentioned in section (1) above, each bit output data R1 to R0-1 indicates a logical value according to the logical content of each ROM bit, so each bit output data _R1 to _R0-1 is a ROM value according to the logical content of each ROM bit. As the output signal, the fifth
The data is latched by the latch pulse φ _L shown in the figure in the first latch circuits L ₁ to _{L o-1} and simultaneously written to the latch shift circuits LS ₁ to L _o which operate as parallel-to-serial conversion registers. At this time, the ROM output R _o is also latched by the first latch circuit L _o . That is, in this case, the first latch circuits L ₁ to _Lo operate as ROM output latch circuits and also serve as write circuits for the parallel-to-serial conversion register.

(4) In the above item (3), when the writing operation of the potential of the nodes R ₁ ^* to R _o ^* is completed, the write control pulse φ _W becomes logic “0” as shown in FIG. The second latch circuits L ₁ -L _o ' having the signal _W as one input operate as storage circuits that latch the other input data R ₁ -R _o as they are at the timing of the shift pulse φ _S. Furthermore, at this time, the precharge pulse φ _ROM
also becomes logic “0” as shown in Figure 5,
Nodes R ₁ ^* to R _o ^* of each bit of the ROM are set to logic "1" by N channel transistors N ₁ to _{N o} . Therefore, the NAND circuit NA ₁ which has nodes R ₁ ^* to R _o-1 ^* as one input inputs only the output data of the NAND circuit NA ₂ in the previous stage directly to the fifth
It operates as a memory circuit that latches at the timing of latch pulse _φ1 shown in the figure.

(5) Next, when the state described in item (4) above is reached, two pulses φ _L and φ _S are generated with different phases as shown in Figure 5. If you make it work as a shift pulse,
Circuit that operates as the shift register described above
The output data R ₁ to _Ro of each bit of the ROM written to LS ₁ to _{LS o} is sequentially shifted by the shift pulses φ _L and φ _S and sent to the latch shift circuit as serial data as shown in FIG. Taken out from the output end of LS ₁ .

(6) In item (5) above, while the output data of the ROM is being shifted sequentially, both pulses φ _W and φ _ROM are at logic “0” as shown in FIG.
Nodes R ₁ ^* to R _o ^* of each bit of ROM are logic “1”
After all the data has been shifted, that is, after the bit data R _o has been taken out as serial data, the nodes R ₁ ^* to R _o ^* in the above-mentioned (1) are set to a predetermined logical value. The process returns to the operation described above, and the same cycle as the series of operations described above is repeated. Here, these data R ₁ ~ _{R o}
As shown in Figure 5, while is being shifted
When the ROM address is changed, in the next cycle, the ROM output data corresponding to a different address from the previous cycle can be serially retrieved.

(7) The cycle described in items (1) to (6) above is
If we decide to repeat the same number of times as the ROM address,
Data covering all addresses of all bits in ROM can be extracted as serial data.

According to the above device, the latch circuit required to operate the ROM is shared as the write circuit of the parallel/serial conversion shift register, so ROM output data can be easily written by adding only the data read circuit. Parallel/serial conversion becomes possible. Therefore, the area occupied by the conversion circuit on the chip is not as large as in the conventional case, but can be made compact.

In the above embodiment, a CMOS type dynamic ROM was explained, but other circuits similar to ROM, that is, outputs of multiple bits are latched by first latch circuits each using the first pulse φ _L as the latch pulse. The present invention can also be applied to the case of checking the output of a circuit that is taken out.

As explained above, according to the present invention, the circuit configuration is such that the latch circuit that latches multiple bits output from the circuit under test is shared as the write circuit of the parallel/serial conversion register, so the circuit configuration is simple and the chip area is reduced. It is possible to provide an integrated circuit device that can be made compact by suppressing an increase in output, and can efficiently and easily perform parallel-to-serial conversion of the output.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a conventional integrated circuit device, FIG. 2 is a time chart for explaining the operation of the device in FIG. 1, and FIG. 3 is a circuit diagram of an integrated circuit device according to an embodiment of the present invention. The configuration diagram, FIGS. 4 and 5 are time charts for explaining the operation of the apparatus shown in FIG. 3. LS ₁ ~ _{LS o} ...Latch shift circuit (parallel/
(shift register for serial conversion), L ₁ to _{L o} .... first latch circuit, L ₁ ' to _{L o} ' ... second latch circuit,
N ₁ ~ _{N o} ...N channel transistor, NA ₁ ~
NA ₂ ... NAND circuit, R ₁ ^* ~ _{R o} ^* ... each bit node, R ₁ ~ R _o ... ROM bit output data, φ _W ...
...Write control pulse, φ _L ...Latch pulse,
_φS ...Shift pulse.

Claims (1)

[Scope of Claims] 1. In an integrated circuit device incorporating a circuit under test having an output of a plurality of bits, a first circuit is provided corresponding to the output bits of the circuit under test and latches each of the output bits with a first pulse. A latch circuit and an output of this latch circuit are respectively introduced, and the input is controlled by a predetermined control pulse to generate a second pulse having a phase different from that of the first pulse.
a second latch circuit that latches by the pulse of;
The first latch circuit and the second latch circuit for each of these bits
a circuit that connects two latch circuits in series, and when the control pulse is not applied, the output of the first latch circuit is derived in parallel, and when the control pulse is applied, the output of the first latch circuit and the first latch circuit are derived in parallel. An integrated circuit device characterized in that the plurality of bit outputs are derived in series by a shift operation using two pulses. 2. The integrated circuit device according to claim 1, wherein the circuit under test is a dynamic ROM.