JPS633331B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a function value generation device for determining the value of a function for an encoded variable.

Numerical calculations regarding specific functions, such as trigonometric functions or hyperbolic functions, are one of the basic functions essential for arithmetic operations by electronic computers and the like. In addition, calculations involving the above-mentioned functions are often performed in numerical control devices or graphic display devices controlled by minicomputers, microcomputers, etc. when handling geometric coordinates.

Therefore, it is important to simplify and speed up the procedure and processing mechanism for generating a function value, that is, finding the value of a function for a given numerical value.

Among the conventional methods of generating function values, one that is relatively widely adopted because it is well suited to software methods is to expand the function into a polynomial regarding input variables and perform numerical calculations. be. Although this method has the advantage of requiring only a small amount of data to be memorized in advance, since it is an approximate calculation, it is necessary to repeatedly calculate even high-order terms in order to obtain a highly accurate solution. However, it takes a long processing time and lacks high speed. Also, according to the CORDIC algorithm, which is a well-known method for finding elementary functions,
Although it is well suited to firmware and hardware implementation, it also has problems with solution convergence and requires a long processing time, making it unsuitable for use in devices that require high speed.

On the other hand, advances in LSI technology have made it possible to provide large-capacity and inexpensive storage devices such as ROM, so when the number of inputs is relatively small, all required function values can be stored in advance. It may also be stored in a ROM or the like. However, if the number of inputs is large, for example if the input variables are represented with 16-bit binary precision, this method requires approximately 65K words of memory to store all the required function values. It requires ROM, etc., and is economically difficult to put into practical use.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a function value generating device that can quickly generate highly accurate function values for highly accurate input variables and reduce the required storage capacity.

According to the present invention, there is provided a means for outputting an integer part of a quotient obtained by dividing a binary encoded input variable by a predetermined constant and a partial remainder smaller than the constant, and the integer part a function value storage device in which function values corresponding to all possible numerical values of are stored in advance, and the stored function values can be read out by addressing with the integer part; and inputting the partial multiplication remainder. a first arithmetic unit that calculates a function value for the partial product by polynomial approximation up to a predetermined degree of the function; and a function value read from the function value storage device and the first arithmetic operation. There is obtained a function value generating device characterized in that it comprises a second arithmetic device which inputs a function value calculated from the device and calculates a function value for the input variable.

The present invention obtains a function value to be determined from a small amount of stored function values and a function value calculated by approximating a function polynomial of a lower order, thereby obtaining highly accurate function values at high speed with a simple device configuration. It is characterized by the fact that it can occur.

In order to more specifically explain the principles and effects of the present invention, a sine function of trigonometric functions will be considered as an example.

The input variable Θ (unit: radian) is expressed as Θ=αN+β β<α ……(1). Here, α is a constant, N is an integer, and β is a partial multiplication remainder of the part smaller than α. According to the addition theorem of trigonometric functions, the following relationship holds true: SinΘ=Sin(αN+β)=SinαNcosβ+cosαNsinβ...(2) Moreover, if the trigonometric function is expanded into a polynomial, it can be expressed as sinβ=β− ^β3 /6+…… cosβ=1− ^β3 /2+……(3), and if β is sufficiently small, a sufficiently good approximation can be obtained up to a low order. Give the formula.

That is, equation (2) shows that the value of the sine function for the input variable Θ is determined from the sine and cosine function values for the variable N and the variable β, respectively.
Furthermore, by appropriately selecting the constant α, the maximum value of the variable N can be made small, and the variable β can be made a sufficiently small value. small capacity
It can be obtained by storing it in advance in a storage device such as a ROM, and the function value regarding the variable β can be obtained by an approximation of equation (3) up to a low order, that is, by a simple arithmetic means.

The principles explained above are also applicable to other trigonometric functions, hyperbolic functions, exponential functions, etc., i.e., a family of functions in which the function value for the sum of multiple variables is expressed by calculating the function value for each change. It is something.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a trigonometric sine function value generator for explaining a first embodiment of the present invention.

1 is a means for extracting an integer N and a partial multiplier β from an input Θ according to equation (1), that is, a division device; 2 is a polynomial approximation of the sine/cosine function value for the partial multiplier β according to equation (3) 3 is the sine/cosine function corresponding to the integer N.
A function value storage device that stores sinαN and cosαN in advance, and 4 a second arithmetic unit that calculates the sine function value regarding the input Θ from the function value for the integer N and the partial product β using equation (2). It is. Reference numeral 101 is an output signal line that supplies input Θ, which is input to division device 1 . 102 and 103 are output signal lines of the division device 1. The partial product remainder β is outputted to the output signal line 102 and supplied to the first arithmetic unit 2 .
An integer N is output to the output signal line 103 and supplied to the function value storage device 3. Reference numerals 201 and 202 are output signal lines of the first arithmetic unit, which transmit the calculated values of sin β and cos β, respectively, and supply them to the second arithmetic unit 4. 301 and 302 are output signal lines of the function value storage device 3, and transmit the values of sinαN cosαN read to each of them to be sent to the second arithmetic device 4.
supply to Reference numeral 401 is an output signal line of the second arithmetic unit 4, and is also an output signal line of the present sine function value generation device.

Now, assume that a sine function value is generated for an input Θ in the range OΘ<π. As an example, input Θ
is m-bit fixed-point format data, and if we set the constant α=π/2 ⁿ (n<m) in equation (1), then N
is an n-bit integer, and β is a value smaller than π/2 ⁿ .

FIG. 2 is a block diagram showing a specific embodiment of the division device 1. As shown in FIG. 11 is a selector, 12 is a shift register, 13 is a fixed register, 14 is a determination circuit including a subtraction circuit, and 15 is a shift register, which constitute a division circuit. Since this configuration is well known, details such as control signals are omitted in the figure. The shift register has m bits, and a multiple divisor, ie, an input Θ which is first supplied to the input signal line 101, is set via the selector 11. A divisor, that is, a constant α (=
π/2 ⁿ ) is set in fixed point format with appropriate significant digits. The determination circuit 14 subtracts the contents of the fixed register 13 from the shift register 12, including the most significant digit, and if the value is positive, sets it in the shift register 12 via the selector 11, and also writes "1" to the shift register 15. Shift in a value. If the value is negative, only a value of "0" is shifted into the shift register 15. Next, the shift register 12 is shifted 1 bit upwards and the above operation is repeated. After repeating n times, the n-bit quotient, ie, the integer N, is delivered to the shift register 15, and its partial product, ie, β, is obtained to the shift register 12, and these are outputted through output signal lines 103 and 102, respectively.

FIG. 3 is a circuit diagram showing a specific embodiment of the first arithmetic unit 2. In FIG. As an example, let us obtain an approximate value using the quadratic term of equation (3). 21 is a multiplication circuit, 22 is a fixed register, 23 is a subtraction circuit, 24
and 25 is a normalization circuit. The fixed-point format partial product remainder β supplied to the signal line 102 is converted into a floating-point format via the normal circuit 24 and output. That is, the value obtained on the output signal line 201 is sinβ=β. The other partial multiplier β is calculated as β ² by the multiplier circuit 21, and is extracted by shifting the output signal line by one bit in the lower direction, so that a value of β ² /2 is obtained. Further, the value 1 is set in the fixed register 22, and the subtraction circuit 23 calculates 1-β ² /2 from the above two values, which is further converted into floating point format via the normalization circuit 25 and output. be done. In other words, cos β to the output signal line 202
A value of =1-β ² /2 is obtained. Again in Figure 1,
The function value storage device 3 is a ROM of 2 ⁿ words addressed by an integer N, and for example, sin αN is stored in the upper half of each word, and cos αN is stored in the lower half of each word. The values of sinαN and cosαN are obtained in advance by other calculation means, and are expressed in floating point format as an example. The content of the upper half of each word, ie, the value of sinαN, is read out to the output signal line 301 of the function value storage device 3, and the content of the lower half of each word, ie, the value of cosαN, is read out to the output signal line 302, respectively.

FIG. 4 is a circuit diagram showing a specific embodiment of the second arithmetic unit 4. In FIG. 41 and 42 are multiplication circuits, and 43 is an addition circuit, each of which performs floating point operations. The multiplication circuit 41 calculates the value of sinαN on the signal line 301 and the value of sinαN on the signal line 202.
The multiplier circuit 42 receives the value of cosβ and calculates the value of sinαNcosβ, the multiplier circuit 42 receives the value of cosαN on the signal line 302 and the value of sinβ on the signal line 201 and calculates the value of cosαN sinβ, and the adder circuit 43 calculates the value of cosαN sinβ. The re-output value is received, added, and output. That is, the second calculation device 4 performs calculation according to the right side of equation (2),
The value of sinΘ is obtained on the output signal line 401.

In the above description, it is assumed that the sine/cosine function values stored in the function value storage device 3 are in fixed-point format, and therefore the second arithmetic unit 4 is constituted by a multiplication and addition circuit that performs fixed-point arithmetic. For example, the normalization circuits 24 and 25 of the first arithmetic unit 2 are unnecessary.

FIG. 5 is a circuit diagram showing a second embodiment of the division device 1. 16 is an m-bit register that stores the input Θ, 103 is the output signal line of the upper n bits of register 16, and 102 is the lower m-n bits of register 16.
This is a bit output signal line. In this embodiment, the constant α=2 ^2-n is determined in equation (1), and the input Θ is in m-bit fixed-point format including a 2-bit integer part.
, the n-bit integer N and m−n bits
2 This is to extract the partial power β smaller than ^2-n .
That is, the integer N is output to the output signal line 103, and the partial product remainder β is output to the output signal line 102. At this time, the other components in FIG. 1 are configured in exactly the same way as in the first embodiment, but the sine/cosine function values stored in the function value storage device 3 are such that N is 0 to π/4.
×2 It corresponds to the range of integers not exceeding ⁿ .

According to this embodiment, the division device 1 based on equation (1) can be implemented without requiring a complicated division circuit.

FIG. 6 is a block diagram showing the configuration of a sine function value generator for explaining a third embodiment of the present invention.

In this embodiment, the polynomial approximation according to equation (3) is limited to first-order terms, and therefore equation (2) is expressed as sinΘ=sinαN+βcosαN . . . (2)′. At this time, the first arithmetic unit 2 that performs polynomial approximation calculations is not particularly required, and the output signal line 102 that conveys the partial product β of the division device 1 is directly input to the second arithmetic unit 4. The second arithmetic unit 4 that implements equation (2)' is constructed as shown in FIG. The other components are exactly the same as in the first or second embodiment.

According to this embodiment, the present invention can be implemented with a further simplified circuit configuration.

By analogy with the above explanation, the present invention can be implemented in the same way with other trigonometric functions, hyperbolic functions, exponential functions, etc.

To specifically explain the effects of the present invention using numerical values, when input Θ is expressed with 16-bit precision,
If we were to store all the values of sinΘ, a ROM of 65536 words would be required, but in this invention, as an example,
= 8, the capacity of the function value storage device will be greatly reduced to 512 words even if the sine and cosine function values are stored in separate ROMs, and the partial product β will also be smaller than 0.016, making polynomial approximation linear. Alternatively, a sufficiently well approximated function value can be obtained up to the quadratic term, which simplifies the arithmetic circuit.

In summary, the effect of the present invention is that highly accurate function values can be generated quickly for highly accurate input variables using a simple device configuration and a small capacity storage device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a trigonometric sine function value generator for explaining the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the specific configuration of the division device 1, and FIG. 3 is a circuit diagram showing the specific configuration of the first arithmetic device 2, and FIG. 4 is a circuit diagram showing the specific configuration of the first arithmetic device 2.
5 is a circuit diagram showing a second embodiment of the division device 1, and FIG. 6 is a sine function of a trigonometric function for explaining a third embodiment of the present invention. FIG. 7 is a block diagram showing the structure of the value generating device. FIG. 7 is a circuit diagram showing the structure of the second arithmetic device 4 according to the third embodiment. In the figure, 1...means for extracting an integer N and a partial multiplier β from an input Θ, that is, a division device, 2...a first arithmetic device,
3...Function value storage device, 4...Second arithmetic device,
11...Selector, 12...Shift register, 1
3... Fixed memory, 14... Judgment circuit, 15...
Shift register, 16...Register, 21...Multiplication circuit, 22...Fixed register, 23...Subtraction circuit, 24, 25...Normalization circuit, 41, 42...
A multiplication circuit, 43...an addition circuit.

Claims (1)

[Claims] 1. A device for calculating a function value for a binary-encoded input variable, and extracting an integer part of a quotient obtained by dividing the input variable by a predetermined constant and a partial remainder smaller than the constant. means, a function value storage device in which function values corresponding to all possible numerical values of the integer part are stored in advance and the stored function values can be read out by addressing with the integer part; a first arithmetic device that inputs the partial remainder and calculates a function value for the partial remainder by polynomial approximation of a function up to a predetermined degree;
A second arithmetic device that calculates a function value for the input variable by inputting the function value read from the function value storage device and the function value calculated from the first arithmetic device. Function value generator.