JPS6333735B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for driving large capacitive loads.
Regarding MOSFET buffer circuit. In more detail, it consumes almost no power in standby mode.
This article relates to MOSFET buffer circuits for driving large capacitive loads.

As a MOSFET buffer circuit for driving a large capacitive load, two enhancement type MOSFETs, the first and second ones with large gain constants, are used.
The drain electrode of the first MOSFET is connected to the first power supply, the source electrode is connected to the output point, and the second
An output stage configured by connecting the drain electrode of a MOSFET to an output point and connecting a source electrode to a second power supply, and the second power supply provided between the first and second power supplies to drive the output stage; first and second
Depletion type connected to MOSFET
A circuit consisting of a drive stage made up of two sets of push-pull inverters using MOSFETs as pull-up transistors is often used.

The conventional circuit that has been modified from this circuit so that it consumes almost no power in the standby state is a depletion type circuit in the drive stage.
An enhancement type MOSFET is connected between the drain electrode of the MOSFET and the first power source to which it is connected, with the drain electrode connected to the first power source and the source electrode connected to the depletion type MOSFET.
It is inserted so that it is connected to the drain electrode of the MOSFET, and its gate electrode is connected to the MOSFET in the operating state.
A control voltage is applied to turn on the MOSFET, and a control voltage is applied to turn it off in the standby state to interrupt the conductive path between the first power source and the second power source in the drive stage, and Said first MOSFET
By providing means for applying a voltage level that turns off the MOSFET in the standby state to the gate electrode of one or both of the second MOSFETs, the conductive path of the output stage is also cut off, and leakage current is prevented in the standby state. Other than that, it is a circuit that consumes no power.

However, according to this conventional circuit, in the operating state, the gate electrode of the first MOSFET in the output stage has a threshold voltage of the MOSFET of the switch that is lower than the control signal voltage as the voltage level that turns on the MOSFET. You can only get the value by subtracting . Therefore, compared to a circuit without a switch MOSFET that can obtain up to the voltage value of the first power supply, the voltage value from the first power supply to the first power supply is
It had the disadvantage of low ability to charge the load capacitance through MOSFET.

The present invention eliminates the drawbacks of the conventional circuit, and does not consume power other than through leakage current in the standby state, while at the same time, in the operating state, the load charging capacity is improved compared to a circuit that does not include the transistor of the switch. The purpose is to provide a comparable MOSFET buffer circuit.

According to the present invention, an enhancement-type first electrode whose drain electrode is connected to a first power source is provided.
The MOSFET and the drain electrode are connected to the first
A second enhancement-type MOSFET is connected to the source electrode of the MOSFET to form an output point, and the source electrode is connected to the second power supply, and a third depletion-type MOSFET is connected to the first power supply, and the drain electrode is connected to the first power supply. a fourth enhancement-type MOSFET whose drain electrode is connected to the source electrode of the third MOSFET and whose source electrode is connected to the gate electrode of the first MOSFET;
an enhancement-type fifth MOSFET whose drain electrode is connected to the source electrode of the fourth MOSFET, whose gate electrode is connected to the input terminal, and whose source electrode is connected to the second power supply;
A capacitor whose first terminal is connected to the gate electrode of the MOSFET and whose second terminal is connected to the source electrode, whose drain electrode is connected to the first power supply, and whose source electrode is connected to the gate electrode of the fourth MOSFET. a sixth enhancement type MOSFET which is connected to the fourth MOSFET; a seventh MOSFET whose drain electrode is connected to the gate electrode of the fourth MOSFET and whose source electrode is connected to the second power supply; means for applying a signal in phase with the signal applied on the terminal to the gate electrode of the second MOSFET; and means for applying a signal in phase opposite to the signal applied on the input terminal to the gate electrode of the third MOSFET. and a means for applying the voltage, and in the standby state the seventh
The MOSFET conducts and cuts off the fourth MOSFET, and the first MOSFET and the second MOSFET
A MOSFET buffer circuit is obtained in which at least one of the MOSFETs is cut off.

The present invention will be described below with reference to drawings showing embodiments. However, the MOSFET is assumed to be an N-channel device as an example, and the enhancement type device will be described as being turned on by a positive voltage level representing a truth value state.

FIG. 1 is an example of a conventional MOSFET buffer circuit for driving a large capacitive load, which consumes no power other than leakage current in a standby state. 1 and 2 are enhancement type MOSFETs with large gain constants that discharge and charge the load capacitance connected to the output point 15, respectively. Enhancement type MOSFETs 5 and 8 and depletion type MOSFETs 4 and 7 form two sets of push-pull inverters for driving MOSFETs 1 and 2, and enhancement type MOSFETs 3 and 6 are switches for cutting off the conductive path in the standby state. . In the standby state, the control signal CE applied to the terminal 10 has a negative value and the MOSFETs 3 and 6 are turned off. Regarding MOSFET1 and 2,
When at least one of the inputs applied to points 11 and 12 is set to the truth level, points 13 and 14
a negative value level is obtained for at least one of the
At least one of MOSFETs 1 and 2 is turned off. Alternatively, connect a device between point 13 and ground, or between point 14 and ground, or both, which acts as a switch that conducts in a standby state;
Turn off one or both of MOSFETs 1 and 2. Therefore, all conductive paths from the power supply to ground are cut off, and no power is consumed other than by leakage current.

In the operating state, CE becomes the truth value, and MOSFET3
and 6 are conductive. Voltages having opposite phases to each other are input to input points 11 and 12, voltages having opposite phases to each other are generated at points 13 and 14, and a truth value or a negative value is obtained at output point 15. Now, when a truth value level is input to input point 11 and a negation value level is input to input point 12, a truth value level is obtained at point 14, a negation value level is obtained at point 13, and a truth value level is obtained at point 15.
Here, the voltage of the control signal CE is set to VCE, MOSFET1,
Let VT1 and VT3 be the threshold voltages of 3, respectively, the voltage V14 obtained at point 14 is V14=VCE-VT3. When there is no MOSFET 3 in the switch, if the power supply voltage is VDD, V14 = VDD, and generally VCE≦VDD, so the circuit in Figure 1 is for the switch.
Compared to the case without MOSFET 3, the voltage applied to the gate electrode of MOSFET 1 is lower, and therefore the ability to charge the output load capacitance from the power supply through MOSFET 1 is lower. Also, the output voltage obtained at point 15
In the circuit shown in Figure 1, VOUT is VOUT = VCE - VT3 - VT1, which is lower than the voltage VOUT = VDD - VT1 without MOSFET 3, which is also not desirable.

FIG. 2 shows an embodiment of the invention. MOSFET2
The operations of MOSFETs 1, 22, 26, 27, and 28 are respectively the same as those of MOSFETs 1, 2, 6, 7, and
The operation is the same as No.8. Enhancement type
MOSFET24 is in the circuit of Figure 1.
Acts as a switch equivalent to MOSFET3
MOSFETs 29 and 30 each have a control signal CE and its opposite phase signal input to their gate electrodes, charge and discharge a capacitor 31,
Controls MOSFET24.

In the operating state, CE is the truth level, so
When CE is at negative level, MOSFET29 is on.
MOSFET30 is turned off. Yotsute MOSFET
24 is turned on because a truth level is applied to the gate electrode, and the gate consisting of MOSFETs 23, 24, and 25 drives MOSFET 21 by inputting voltages having mutually opposite phases to points 11 and 12. MOSFETs 23 and 25 are push-pull circuits, and since a depletion type element is used for pull-up transistor 23, the voltage at point 34 is higher than the input voltage applied to point 11, which would occur if an enhancement type element was used. There is no problem of the threshold voltage being lowered, and the large gate capacitance of the MOSFET 21 with a large gain constant can be driven at high speed. At this time, MOSFET24,
A capacitor 31 connected between the gate electrodes 29 and 24 and the source electrode constitutes a bootstrap circuit. That is, when a negative value is input to point 11, a truth value is input to point 12, and a negative value level is generated at point 34, capacitor 31 is charged from the power supply through MOSFET 29, and the voltage between the terminals of capacitor 31 at this time is:
Even when the input at point 11 becomes a truth value, the input at point 12 becomes a negative value, and the point 34 becomes a truth value level, it is also saved, so MOSFET 24 is turned off even if the voltage at point 34 rises to the power supply voltage VDD. Must not be. Therefore, point 34 has the power supply voltage as the truth level.
VDD can be obtained, and the drawbacks of the conventional circuit shown in FIG. 1 are not present.

In the standby state, CE is a negative value, and therefore a truth value, MOSFET 29 is turned off, MOSFET 30 is turned on, and capacitor 31 is discharged through MOSFET 30, so MOSFET 24 is turned off, and MOSFET 23,
The conductive path from the power supply to the ground of the gate circuit consisting of 24 and 25 is cut off. Since the MOSFET 26 is off, the conductive path from the power supply to the ground of the gate circuit composed of the MOSFETs 26, 27, and 28 is also cut off. By setting at least one of the inputs applied to points 11 and 12 to the truth level, point 3
At least one of points 3 and 34 becomes a negative level, at least one of MOSFETs 21 and 22 is turned off, and the conductive path from the power supply to ground is also cut off in the gate circuit consisting of MOSFETs 21 and 22. Instead of bringing at least one of the inputs applied to points 11 and 12 to a truth level, point 3
At least one of points 33 and 34 is set to a negative value level by other obvious means such as providing a MOSFET that conducts in a standby state between point 33 and ground or between point 34 and ground. You can also turn one off.

As explained above, according to the present invention, there is no power consumption other than leakage current in the standby state, and the charging capacity of the output load capacitance in the operating state includes the MOSFET of the switch for cutting off power consumption. A MOSFET buffer circuit that is as good as a circuit without it can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional embodiment, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. In the figure, 1, 2, 3, 5, 6, 8, 21,
22, 24, 25, 26, 28, 29, 30...
Enhancement type MOSFET, 4, 7, 23,
27...Depression type MOSFET, 11,1
2...Input terminal, 15, 35...Output terminal, 9...
...Power supply terminal, 10...Control signal input terminal, 20...
...Input terminal for a reverse phase signal of the control signal, 31...Capacitance, 13, 14, 33, 34... Connection point.

Claims (1)

[Claims] 1. A first enhancement type MOSFET whose drain electrode is connected to a first power source, a drain electrode connected to the source electrode of the first MOSFET to form an output point, and a source electrode connected to a second power source. Second enhancement type MOSFET
a depletion-type third MOSFET, the drain electrode of which is connected to the first power source, the drain electrode of which is connected to the source electrode of the third MOSFET, and the source electrode of which is connected to the gate electrode of the first MOSFET; The fourth enhancement type
MOSFET, and the drain electrode is connected to the fourth
A fifth enhancement type transistor connected to the source electrode of the MOSFET, whose gate electrode is connected to the input terminal, and whose source electrode is connected to the second power supply.
a MOSFET, a capacitor whose first terminal is connected to the gate electrode of the fourth MOSFET, whose second terminal is connected to the source electrode, whose drain electrode is connected to the first power source, and whose source electrode is connected to the fourth MOSFET. The sixth enhancement type MOSFET is connected to the gate electrode of the MOSFET, and the drain electrode is connected to the fourth MOSFET.
a seventh MOSFET connected to the gate electrode of the MOSFET and whose source electrode is connected to the second power supply;
and means for applying a signal in phase with the signal applied to the input terminal to the gate electrode of the second MOSFET in an operating state; Said third MOSFET
means for applying a voltage to the gate electrode of the seventh MOSFET, and in a standby state, the seventh MOSFET conducts and cuts off the fourth MOSFET, and the first MOSFET
A buffer circuit characterized in that at least one of the MOSFET and the second MOSFET is cut off.