JPS6333858B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an abnormal cell detection device that can measure cancer cells non-invasively and non-invasively, for example in mass breast cancer screenings.

BACKGROUND ART Conventionally, as a method for examining abnormal cells in a living body, such as breast cancer cells, in addition to palpation, diagnostic devices using X-ray mammography, ultrasound scanners, and thermography have been considered. However, although X-ray mammography is unsurpassed in terms of resolution, it tends to be regulated, especially in the United States, because of the problems of radiation damage such as birth of abnormal babies and secondary cancer damage. . Furthermore, although the demand for diagnostic ultrasound scanners has been rapidly increasing recently, their poor resolution makes them somewhat unsatisfactory from the perspective of early detection of breast cancer. Moreover, thermography has not yet reached the practical stage.

Recently, as shown in FIG.
b are placed in close contact with each other, each electrode is an assembly of independent electrode cells, and the capacitance value existing in the path from each electrode cell to the other opposing electrode is measured. A device called Mammoth Scanner has been announced to determine the presence or absence of however,
In such a mammoth scanner, one electrode 2a
Since the electrode 2b is placed on the breast and the other electrode 2b is placed on the back, there is a problem that the measured value contains many error components due to the influence of various organs (i.e. cells) intervening between them and their fluctuations. can be,
Also, the lengths of the paths connecting each of the above electrode pairs l ₁ , l ₂ ......
Since the number of cells in the path will vary depending on the undulation of the breast, etc., the number of cells in the path will also differ accordingly, and there is a risk that the measurement may be performed as if there were abnormal cells even though there are no abnormal cells. In order to prevent such inconvenience from occurring, post-processing such as correction according to the body shape is required, which poses a major problem in that the entire device becomes large-scale.

The present invention has been made in view of the above circumstances, and can eliminate the drawbacks of the mammoth scanner to perform accurate measurements, ensure safety, and improve reliability without increasing the size of the device. It is an object of the present invention to provide an abnormal cell detection device that can improve the performance.

The present invention will be specifically explained below with reference to the basic principle and examples.

2 to 4 are diagrams for explaining the basic principle of the present invention. Of these, Figure 2 is a simulated depiction of living body A and cell B inside it.
FIG. 3 is an electrical equivalent circuit on a straight line in the X-Y direction in FIG. 2. However, in FIG. 3, the epidermis and nucleus of living body A in FIG. 2 are completely abstracted away. This is because the epidermis and nucleus have negligible electrical properties. In the diagram
C ₁ to _{C 4} are the intracellular fluid and capacitance, R ₁ to _{R 4} are the resistance of the intracellular fluid and external fluid, and C ₅ to _{C 8} are the capacitance of the plasma membrane of the cell. Here, each of the above constants differs depending on each tissue, but since the number of cells in the measurement site is extremely large and their arrangement is random, here, for convenience of explanation, it is assumed that they all have the same value. . In particular, this assumption is justified since each tissue can be considered to be almost uniform only in the breast region. When this is displayed, it becomes as shown in the following equations (1) to (3).

C ₁ = C ₂ = C ₃ = C ₄ = C _l ...(1) R ₁ = R ₂ = R ₃ = R ₄ = R _l ...(2) C ₅ = C ₆ = C ₇ = C ₈ = C _n ...(3) On the other hand, FIG. 4 is a diagram showing the frequency characteristics of the dielectric constant εS of biological tissues, and although the details of the characteristic curve differ depending on each tissue, they show almost the same tendency. That is,
The relative dielectric constant εS decreases around a certain frequency. Dispersion phenomenon is observed in three parts (α, β, γ), and β dispersion in particular is also called structural dispersion and occurs because the electrical constant differs in each part at the cellular level. It is a phenomenon. That is,
In the frequency range lower than the frequency o that causes β dispersion, the externally applied voltage is applied mostly to the plasma membrane, and in the frequency range higher than o, it is applied to the capacitance of the intracellular fluid and external fluid and the plasma membrane. In this case, the capacitance of the intracellular and external fluids and the capacitance of the plasma membrane are connected in series as shown in Figure 3, and the former has a smaller value than the latter, so they are separated by the frequency o. The capacitance measured externally will be significantly reduced.

Let's consider the equivalent circuit in Figure 3 again assuming the above facts. Here, _{let L} be a frequency lower than the frequency o, _H be a higher frequency, and n be the number of cells in the current path between the Xo and Yo electrodes.

The impedance between Xo and Yo at frequency _L (i.e. capacitance C _L ) is expressed by the following equation (4) from the relationship of the previous equations (1) to (3).
It is expressed as follows.

C _L =C _n /n (4) Then, the capacitance C _H with respect to the frequency _H is expressed as in the following equation (5) in the same way as above.

C _H = 1/n (C _l・C _n /C _l +C _n )...(5) Therefore, the ratio of both capacitances is as shown in the following equation (6), which is independent of the number of cells n. .

C _L /C _H =1+C _n /C _l (6) Next, assume that, for example, cancer cells exist within the measurement site, and the number of cells decreases from n to m (n>m). At this time, the number of plasma membranes decreases according to the number of cells, but the capacitance (same resistance) of the intracellular and external fluids does not change the length of the measurement site, so there are equivalently n cells. can be considered to be similar to the state. Therefore, the capacitance C′ _L for frequency _L
is expressed by the following equation (7).

C' _L = C _n /m ...(7) On the other hand, the capacitance C' _H with respect to frequency _H is expressed by the following formula (8)
It is represented by.

C′ _H = C _l . Cm/mC _l +nCm ……(8) And the ratio of each capacitance (C′ _L /C′ _H ) is calculated using the following formula (9)
It is represented by.

C′ _L /C′ _H =1+(n/m)・C _n /C _l ...(9) Here, since the relationship n>m, the previous equations (6) and (9)
The following equation (10) holds true between .

(C _L /C _H )<(C _L ′/C _H ′) ...(10) Based on these results, calculate the capacitance values at frequencies _L and _H in the current path from each electrode cell,
If the ratio is calculated and the calculation result is displayed as a gray signal corresponding to the measurement area, the above-mentioned
From the relationship of equation (10), the presence or absence of cancer cells and their location can be detected.

An embodiment embodying the above principle will be described.

FIG. 5 is a block diagram showing one embodiment of the apparatus of the present invention. Reference numeral 1 in the figure is a subject, and electrodes 2a and 2b are brought into close contact with the upper and lower surfaces of the breast for breast cancer screening. Although not clearly shown in the figure, it is assumed that the electrode 2a is internally divided into electrode cells. The signal S1a from each electrode cell constituting the electrode 2a is sent to analog switches AS1a, AS1b,
They are connected to one end of AS1n, respectively, and are input to the capacitance measuring device 3 together with the signal S1b from the other electrode 2b via the other ends of these analog switches AS1a to AS1n. The capacitance measuring device 3 receives the output signal S12 of the reference voltage generating device 6 that separately generates two types of voltages having the two frequencies _L and _H (equal amplitude), and also Voltage signals S2 corresponding to capacitance values at respective frequencies _L and _H are sequentially and selectively output in the current path of the electrode cell. The voltage signal S2 from this capacitance measuring device 3 is sent to two analog switches.
The signals are transferred to two corresponding peak value detection and holding devices 4a and 4b via AS2a and AS2b, respectively. The output signals S3a and S3b of the two peak value detection and holding devices 4a and 4b are inputted to a dividing device 7, which outputs a signal S4 which is the ratio of both signals S3a and S3b. This signal S4 is input to an analog-digital converter (ADC) 8, and the output digital signal S5 of this ADC 8 is sequentially stored in the storage device 9. Reference numeral 10 denotes a display device that receives an output signal S6 based on information in the storage device 9, performs appropriate signal processing, and then displays a desired display. Reference numeral 5 denotes a timing control circuit for controlling the various devices, including the capacitance measuring device 3 and the peak value detection and holding device 4.
Reset signal S for resetting a and 4b
7.Sequentially turn analog switches AS1a to AS1n
Analog switch gate signal S to turn ON and OFF
8. The reference voltage generator 6 and analog switches AS2a, AS2b are set to the two types of frequencies _L and
Gate signal S9 that selectively switches according to _H , address selection signal S that selects the address of the storage device
10, each outputs a memory latch signal S11.

An example circuit showing details of the capacitance measuring device 3 will be described with reference to FIG. 6. This capacitance measuring device consists of an operational amplifier IC ₁ with resistors R ₅ to _{R 7}
and has resistors R ₈ to R ₁₀ and diodes D ₁ and D ₂ ,
an operational amplifier IC ₂ that receives the output of the operational amplifier IC ₁ as an input; and resistors R ₁₁ to R ₁₃ ;
It is equipped with an operational amplifier IC ₃ whose input is the output of IC ₂ ,
The electrostatic capacitance C of the human body existing on the current path connecting the electrodes 2a and 2b is connected between the input and output of the operational amplifier _IC1 , and a switching transistor driven by the reset signal S7 is connected to the feedback path. Q ₁ is connected to constitute an integrating circuit 3A, and the two subsequent operational amplifiers IC ₂ and IC ₃ constitute an absolute value circuit 3B.

A detailed circuit of one embodiment of the peak value detection and holding devices 4a and 4b will be described with reference to FIG. This device includes _a detection and holding circuit 4a 1 consisting of an input resistor R ₁₄ , an operational amplifier IC ₄ having a feedback capacitor C ₉ , a diode D ₃ and a capacitor C ₁₀ , and the detection and holding circuit 4a ₁
A source follower circuit (consisting of a field effect transistor _Q4 and a resistor _R15 connected in series between the power supplies +V and _-V ) _4a2 provided on the output side of the A field effect transistor Q ₃ is connected in series between the power supply +V and -V terminals via resistors R ₁₇ and R ₁₈ , respectively, and is driven by the collector side output of the transistor _{Q 2} . is constituted by a reset circuit _4a3 connected between the cathode of the diode _D3 and the ground terminal.

A detailed embodiment of the timing control circuit 5 will be described with reference to FIG. This circuit is a resistor
It is reset by a power reset circuit 5A consisting of R ₁₉ and a capacitor C ₁₁ and the output of this power reset circuit 5A, and is also reset by a push button switch.
A flip-flop FF constituted by gate circuits IC ₅ and IC ₆ whose setting and reset are performed by PB ₁ and PB ₂ , and this flip-flop FF.
Gate circuits IC ₇ , IC ₈ , resistors R ₂₂ , R ₂₃ , capacitor C ₁₂ , controlled by one output signal S ₁₃ of
An oscillator OSC consisting of a crystal oscillator XTL, and a first
A second JK flip-flop IC11 that inputs the output of this flip-flop IC10 to the clock terminal, a shift register IC12 and a counter IC13 that commonly input the output of this flip-flop IC11 to the clock terminal, and four NAND gates. Circuit IC14
~ IC17, JK flip-flop IC10, IC11 and shift register IC12,
Both the counter IC 13 and the flip-flop FF
is cleared by the other output signal. Here, the first stage NAND gate circuit IC
14 outputs a reset signal S7 in relation to the output of the oscillator OSC and the outputs of the first and second JK flip-flops IC10 and IC11, and the next stage NAND gate circuit C15 outputs the inverted signal of the oscillator OSC (by inverter IC9). inversion), first, second
A memory latch signal S11 is output in relation to the JK flip-flop IC10, IC11, and the third and fourth stage NAND gate circuits IC16, IC17 output the first and second JK flip-flop IC10,
Analog switch gate signals S9a, S9b, and S9 are output for switching the analog switches AS2a and AS2b, respectively, in relation to IC11, and n
The shift register IC12, which has four output terminals, outputs an analog switch gate signal S8 for switching the analog switches AS1a to AS1n, and the counter IC13 outputs an address signal S10 in the form of a binary signal. One of the pushbutton switches, _PB1 , is for starting, and when closed, activates each circuit.The other switch, _PB2 , is for stopping, and is closed at the end of the measurement. This is to inactivate all the output signals of the timing control circuit 5.

Next, a detailed circuit of an embodiment of the reference voltage generating device will be described with reference to FIG. This device includes analog switches AS3a and AS3b which are respectively controlled by analog switch gate signals S9a and S9b for selectively switching the analog switch S2a for selecting the low frequency _L and the analog switch S2b for selecting the high frequency _H. A first resonant circuit (consisting of resistor R ₂₄ and capacitor C ₁₃ ) connected to 6A ₁ and a second resonant circuit (consisting of resistor R 24 and capacitor C 13) connected to
R ₂₅ , configured by capacitor C ₁₄ ) 6A ₂
and an operational amplifier IC18 having a capacitor C ₁₅ , resistors R ₂₆ , R ₂₇ , and a volume resistor VR ₁ , and the output of this Wien Bridge oscillator 6A is connected to a diode.
Input via D ₄ , D ₅ and resistors R ₂₈ , R ₂₉
and operational amplifier IC1 with volume resistor VR ₂
9, and is configured to generate two types of reference voltages corresponding to each frequency as the output signal S12.

Next, the operation of the component device will be explained with reference to the time chart of FIG. 10.

First, after turning on the power, electrodes 2a and 2b are attached to desired positions, for example, on the upper and lower surfaces of the breast as shown in FIG. Then, by turning on the start push button switch _PB1 , the oscillator OSC in the timing control circuit 5 is activated, and a pulse-like signal S14 as shown in FIG. 10 is generated from the output terminal of the inverter IC8. Next, the first JK flip-flop IC 1 in the timing control circuit 5
0 is activated, NAND gate circuit IC1
6 is also activated and the analog switch gate signal S9a for low frequency _L selection is output.
The low frequency _L selection analog switch AS3a of the reference voltage generator 6 is turned on, and a sine wave voltage E of frequency _L is generated from the Wien Bridge oscillator 6A. Therefore, the voltage follower 6B at this time
The output signal _S12L from is a voltage calculated by the following equation (11).

S12 _L = E sin (2π _L ) t ...(11) Such a signal S12 _L is detected by the capacitance measuring device 3.
At the same time, the least significant bit (hereinafter abbreviated as LSB) of the parallel output signal S8 of the shift register IC12 in the timing control circuit 5 is in the active state, so the analog switch AS1a is turned on by the signal S8a. Therefore, the capacitance measuring device 3 obtains an output signal _S2L expressed by the following equation (12) (actually, the signal is absolutely amplified by the absolute value circuit 3B).

S2 _L = |-1/R ₅・C _L ∫ _p ^t S12dt|=E/2π _L・
R ₅ · C _L · cos (2π _L ) t...(12) Furthermore, since the analog switch AS2a is also in the ON state due to the analog switch gate signal S9a, the signal S2 _L is detected by the peak value detection and holding device 4a.
is input. Therefore, the peak value detection and holding device 4a
If the peak amplification degree of is 1, the output signal S3
a becomes a value expressed by the following equation (13) and is held.

S3a=max(S2 _L )=E/2π・_L・_R5・_CL ...(13) (The above is time _T1 in FIG. 10) Next, from the NAND gate circuit IC17 at the bottom stage in the timing control circuit 5 The _H selection analog switch gate signal S9b is activated and the analog switch AS3b in the reference voltage generator 6 is turned on, thereby generating an output signal _S12H having a value as shown in the following equation (14).

S12 _H =E sin(2π _H )t (14) Therefore, an output signal S2 _H having a value as shown in the following equation (15) is obtained from the integrating device 3.

S2 _H = E/2π _H・R ₅・C _H | cos (2π _H ) t | ...(15) Furthermore, this signal S2 _H is the analog switch AS2
input to the peak value detection and holding device 4b via b,
The output signal S3b indicates a value expressed by the following equation (16).

S3b=E/2π _H・R ₅・C _H ...(16) (The above is time T ₂ in Fig. 10) Signals S3a, S3b obtained as above
is input to the division device 7, which calculates the ratio between the two and outputs a signal S4 having a value as shown in the following equation (17).

S4=S3b/S3a=( _L / _H )・( _CL /CH ₎ ...(17) Here, since ( _L / _H ) is a known constant,
The ratio of capacitance values can be equivalently determined based on the signal S4 using the above equations (6) to (9). Subsequently, the output signal S4 is digitized by the ADC 8, and this digitized signal S5 is stored in the storage device 9. This storage is performed by the counter IC 13 and the NAND gate circuit in the timing control circuit 5.
This is done through activation of IC15. That is, the parallel output address signal S10 is obtained by activating the counter IC13, and the NAND gate circuit IC1
5, a memory latch signal S11 is obtained, and the combination of these causes the digitized signal S5 to be stored at a predetermined address. in this case,
For example, the storage device 9 is configured to have an area corresponding to the array or matrix electrodes 2a, and when storing, in synchronization with an analog switch gate signal S8 that switches each cell of the electrodes 2a, It is assumed that the data can be stored at the corresponding address.

(The above is time T ₄ in FIG. 10.) Thereafter, the uppermost NAND gate circuit IC14 in the timing control circuit 5 is activated to output a reset signal S7, and this reset signal S7 resets the capacitance measuring device 3 and the peak value. detection holding device 4a,
4b.

(The above is time T ₅ in FIG. 10) Thereafter, the same operation is repeated for the number of electrode cells, and the digital signal S5 is generated based on the value S4 obtained by the above formula (17) corresponding to each electrode cell. are sequentially stored at predetermined addresses in the storage device 9. Then, the data in the storage device 9 is read out sequentially for each address at any time and displayed on the screen of the display device 10 through signal processing such as digital/analog conversion. At this time, the magnitude of the data at each address in the storage device 9 is converted into multiple gradation signals such that, for example, large values are dark, small values are light, and intermediate values are gray. The brightness will be modulated and displayed on a CRT, etc. Therefore, the tissue in the area of the breast sandwiched between the two electrodes 2a and 2b will be displayed in shading, and in particular, the points on the screen corresponding to the areas where cancer cells are present will be displayed in a darker shade. , its discovery becomes extremely easy. Incidentally, if the display device 10 is provided with a function of displaying specific numerical values or a graph such as a histogram in addition to a function of displaying gradation, so that each image can be displayed simultaneously, the measurement accuracy can be further improved. This will lead to improvements.

Note that if the measurement range surface of the living body exceeds the area of the electrode 2a, it is necessary to reinstall the electrodes 2a and 2b at different positions. Pressing the stop button PB2 will stop all functions. The same applies after the measurement is finished.
With such an embodiment device, abnormal cells can be reliably detected even if the distance between the electrodes is uneven, and since the distance between the electrodes is narrow, the current flowing through the living tissue can be detected. Since the structure is also minute, safety can be ensured, and since the structure is extremely simple, the device can be made smaller, lighter, and less expensive.

The present invention is not limited to the embodiments described above, and various modifications can be made.

FIG. 11 is a block diagram showing another embodiment of the present invention. This circuit consists of resistances Ra, Rb, capacitance C,
It has a Wheatstone bridge circuit (hereinafter simply referred to as a bridge circuit) WBC consisting of C′. The capacitance obtained by sequentially driving each electrode cell of the electrodes 2a and 2b attached to the living body in the first embodiment is connected between the terminals to which one capacitor C of this bridge circuit WBC is connected. and the capacity of the other
A variable capacitor selected by an analog switch circuit ASC, the details of which will be described later, is connected to the portion to which C' is connected. The power supply terminal of this bridge circuit WBC has the same function as the reference voltage generator shown in the first embodiment, that is, a reference voltage V H based on the high frequency _H and a reference voltage V _H based on the low frequency _L based on the selection signal. A reference voltage generator RVC that generates a reference voltage V _L is connected to this bridge circuit.
A zero state detection circuit (also referred to as a zero detection circuit) ZDT is connected to the output terminal of the WBC. Therefore,
The impedance of each element constituting the bridge circuit WBC is Ra=Z〓 ₁ , Rb=Z〓 ₂ , C=
If Z〓 ₃ , C′=Z〓 ₄ , and Z〓 ₁ = Z〓 ₂ , then Z〓 ₁・Z〓
₃ = Z〓 ₃・
When Z = ₄ , the zero detection circuit ZDT operates,
A predetermined output can be obtained. That is, when the biological capacitance C and the variable capacitance C' match (Z〓 ₃ =Z〓 ₄ ), a predetermined output is obtained.

The analog switch circuit ASC is of an address type, and has a plurality of capacitors (eight in the figure) arranged in parallel, and internally includes a plurality of analog switches and a decoder that selects and controls them. ing. This decoder is controlled based on the output of the counter CT. That is,
This counter CT performs a count-up operation using the output of the oscillator OSCo and sequentially generates count outputs from multiple output terminals (8 bits in the figure), and this count output selects the address of the analog switch circuit. As a result, the decoder outputs an 8-bit combination signal (255 signals), turns on the corresponding analog switch, and selects the capacitance value. Therefore, each capacitance value of each capacitance Ca to Ch is set to, for example, 1, 2,
In the case of 4, 8, 16, 32, 64, 128pF, the signal based on the above 8-bit combination will be 1 to 255pF.
This makes it possible to select a capacitance value within the range of .
The 8-bit output signal of the counter CT is applied to the input terminals of two latch circuits LTA and LTB, and is further applied to the input terminal of a NAND gate circuit NGo. This NAND gate circuit NGo generates a "0" level output every time the counter CT counts the maximum count value ("255") and the outputs of all bits match, and this "0" level output Therefore, the reference voltage switching flip-flop FFo is activated. This flip-flop FFo is a clock type flip-flop whose output is inverted every time the NAND gate circuit NGo outputs a "0" level, and each output switches the reference voltage of the reference voltage generator RVC to the _VH or _L side, respectively. It is something.

On the other hand, a mono multi vibrator (hereinafter referred to as mono multi) is installed on the output side of the zero detection circuit ZDT.
A MM is provided and is configured to generate an inverted output for a predetermined period of time when triggered by the output of the zero detection circuit ZDT. The Q and output of this mono multi MM are each two NAND gate circuits.
The voltage is applied to one input terminal of NG ₁ and NG ₂ , and these NAND gate circuits NG ₁
The Q and output of the clock type flip-flop FFo are applied to the other input terminals of NG2 and _NG2 , respectively. The output of one NAND gate circuit NG ₁ is connected to the strobe terminal of the one latch circuit LTA, and the output of the other NAND gate circuit NG ₂ is connected to the other latch circuit LTA.
It is designed to be applied to each strobe terminal of the LTB. The clear terminal of the counter CT is applied with the output of the NAND gate circuit _NG3 , which has two inputs: the inverted signal of the NAND gate circuit NGo (inverted by the inverter INo) and the output of the monomulti MM. It's getting old,
Normally, it is cleared when the counting operation of the counter CT is finished, but if the zero detection circuit outputs at this time and the mono multi MM is triggered, the clearing operation is temporarily stopped so that it does not interfere with the measurement operation. It's like this. Also, two latch circuits
LTA and LTB outputs are digital divider circuits
It is designed to be input to the input terminals IN-A and IN-B of the DMC, and this digital divider circuit
The output data of the DMC can be stored in a storage device similar to that shown in the first embodiment.

Next, the operation of the circuit will be explained with reference to the time chart of FIG. In this circuit example, each electrode cell is switched using the analog switch used in the first embodiment. RVC is the first reference voltage
The switching timing of each cycle and the switching timing of the electrode cell are synchronized when one cycle is defined as the case where V _H and the second reference voltage V _L are generated and completed once each. , the electrode cells are switched at the falling timing of the output signal of the flip-flop FFo.

First, at time t ₁ in Fig. 12, the counter CT
Suppose that counts the maximum value (“255”) and each bit output matches, then the NAND gate circuit
The outputs of NGo and NG ₃ sequentially become "0" level,
At this timing, the counter CT is cleared, and at the same time, the Q output of the flip-flop FFo becomes "1" level, so the reference voltage generator RVC
produces a V _L output, which causes the bridge circuit to
Power supply voltage is applied to WBC. Since the output of the NAND gate circuit NGo immediately returns to the "1" level, the output of the NAND gate circuit _NG3 also becomes "1".
The level is restored and the counter CT starts counting. At a timing synchronized with this, the first electrode cell of the electrode is selected, and the capacitance C of the living body becomes connected to one capacitance terminal of the bridge circuit WBC. Also, based on the operation of the counter CT, the addresses of the analog switch circuit ASC are sequentially selected and the analog switch is switched, and the value of the capacitor C' connected to the other capacitor terminal of the bridge circuit WBC increases sequentially. It will change to. Then, when both capacitance values (impedances) match, an output is generated from the zero detection circuit ZDT, and the monomulti MM is triggered. Therefore, the Q output of the monomulti MM is "1"
level, and opens the gate of NAND gate circuit _NG1 to which the Q output of flip-flop FFo is input. Therefore, a strobe signal is applied to the first latch circuit LTA, and the current count output of the counter CT is latched. Latch circuit at this time
The digital value latched in LTA is the reference voltage V _L
This corresponds to the capacitance value of the capacitance C of the living body at the time of application (time t ₂ ).

Next, when the counter CT goes through one cycle, the outputs of each bit all match, so the NAND gate circuit NGo
The output of the NAND gate circuit NG3 becomes "0" level again, and accordingly, the output of the NAND gate circuit _NG3 also becomes "0" level and the counter CT is cleared. At this time, the output of the flip-flop FFo is also inverted and becomes the "1" level, so it is switched to the reference voltage _VH of the reference voltage generator RVC, and the bridge circuit WBC
The power supply voltage V _H is applied to (time t ₃ ).
Thereafter, in the same manner as above, the capacitance C of the living body directly under the electrode cell selected first is compared with the variable capacitance C', and when the two match, the zero detection circuit ZDT
Output is generated from. For this reason, monomulti MM
is triggered again and the Q output goes to the "1" level, this time the gate of the second NAND gate circuit _NG2 to which the output of the flip-flop FFo is input is opened, and a strobe signal is given to the second latch circuit LTB. As a result, the current count value of the counter CT is latched in the latch circuit LTB. The digital value latched in this way is the reference voltage.
This corresponds to the capacitance value of the capacitance C of the living body when V _H is applied (time t ₄ ).

As mentioned above, the two latch circuits LTA and LTB
When the digital data corresponding to the capacitance value obtained when the reference voltages V _L and V _H are supplied to is latched, at this timing the digital divider circuit DMC
operates and outputs data corresponding to the ratio of the two. This output data is stored at a predetermined address in the same storage device as in the first embodiment.

This operation is performed sequentially each time each electrode cell is switched, and after the data has been stored in the storage device, it is displayed on the display device and used for various measurements.

By the way, if an output is generated from the zero detection circuit ZDT immediately before the counter CT finishes counting, there is a possibility that this operation will be performed in relation to the counter CT clearing operation, but in this example circuit, the inverter INo and the NAND gate By combining it with circuit NG ₃ , malfunctions are reliably prevented. That is, at time _t5 immediately before the coincidence signal of each bit of the counter CT in FIG. 12 is generated, the capacitance C of the living body
If the maximum capacitance value (255th selected value) of the variable capacitance C′ matches, the output of the monomulti MM becomes the “0” level at this stage, so within that period (time t ₅ ~ _t6 ), the gate of the NAND gate circuit _NG3 does not open, and the counter CT is cleared only when the Q output of the monomulti MM returns to the "1" level (time _t6 ). Therefore, there is no possibility that the digital data latched in the latch circuit LTA will be incorrect data.

According to the device of this embodiment, in addition to the effects of the device of the first embodiment, the signal processing circuit can be completely digitalized, so that the device can be further reduced in size, weight, and cost. The unique effects of improved reliability of circuit operation and excellent operability can be obtained.

Furthermore, in the above embodiment, the pair of electrodes 2
As shown in FIG. 13a, electrodes a and 2b have a structure in which one electrode 2a is a collection of n divided cells, and the other electrode 2b is a single plate electrode.
In this case, for example, the current path between the electrodes 2a and 2b selected by the analog switch AS1a does not necessarily pass through the shortest path _i1 between the electrodes 2a and 2b. That is, in this case, the current path between both electrodes 2a and 2b is the path with the lowest impedance, so the path is longer than the shortest path _l1.
There is a possibility that i ₁ ′, i ₁ ′. Therefore, it is difficult to make the positional correspondence of the current paths by the matrix of the divided cells of the electrode 2a. Therefore, as shown in FIG. 13b, the other electrode 2b is made into n divided cells like the one electrode 2a, and an analog switch AS1a with the same configuration and control drive as the analog switches AS1a to AS1n is formed. ′～
AS1n' is configured to define the current path for each predetermined electrode cell pair by selecting the electrode cells, as shown in the diagram i ₁ , i ₂ , i _{3 .} . . in in FIG. . This clarifies the positional correspondence of the current paths and improves the diagnostic value of the displayed image.

Note that the display method on the display device 10 shown in each of the above embodiments is not limited to the case where the data stored in the storage device 9 is displayed as an image as it is. For example, a data processing device 11 indicated by a dashed line block may be inserted and connected between the storage device 9 and the display device 10 in FIG. 5 to adopt various display modes. For example, as shown in FIG. 14, this data processing device 11 includes an arithmetic circuit (for example, a digital arithmetic circuit) 11A that combines a plurality of data stored in the storage device 9 and calculates and outputs an average value thereof, and a corresponding one that corresponds to the arithmetic output. a display image storage device 11C that combines the data stored in the average value storage device 11B and the data stored in the storage device 9 and stores it as data of an image to be displayed; The control circuit 11D controls the operation of each of these devices.

Next, the operation of this data processing device 11 will be explained in the 15th section.
This will be explained with reference to FIGS. 17 to 17. First, in the memory device 9, as shown in FIG. 15, rows S ₁₁ to S _1o ×columns S ₁₁ to _{S o1} in the divided cells of the electrodes are stored.
It has a matrix corresponding to the matrix of (-1), and data P ₁₁ to _{P 1o} , P ₁₁ are stored in each divided cell.
It is assumed that ~P _o1 , ...... are stored in correspondence (i.e., the data stored in each divided cell section
P ₁₁ , P ₁₂ , . . . can be regarded as indicating the brightness of the central portion of the cell portion). With such a storage device 9 as a reference, the calculation circuit performs calculations as shown in FIGS. 16a to 16e by the operation of the control circuit 11D based on a predetermined calculation program, and sequentially stores them in the average value storage device.

That is, first, two adjacent pieces of data P ₁₁ in a horizontal row,
Average value of P ₁₂ , P ₁₂ , P ₁₃ (P ₁₁ + P ₁₂ /2, P ₁₂ +
P ₁₃ /2), and this calculated data is stored in the average value storage device 11B at a position corresponding to the center of cells S _{100 and} S ₁₀₁ including the tangents of each divided cell S ₁₁ , S ₁₂ , S 12 , and S ₁₃ . (a, b in the same figure). The average value of two horizontally adjacent pieces of data is sequentially shifted one by one and stored in the corresponding position. Next, _the average value _{( P 11 + P 21} /
2, P ₂₁ +P ₃₁ /2), and this calculated data is stored in a position corresponding to the center of the cells S ₁₀₀ and S ₁₁₁ of the average value storage device 11B (c and d in the figure). In this way, the average value of the two pieces of data in the vertical direction is obtained by sequentially shifting one piece at a time and storing it in the corresponding position. Finally, the average value (P ₁₁ +P ₁₂ +P 21 +P ₂₂ /4) of the four adjacent data P ₁₁ , P ₁₂ , P ₂₁ , P ₂₂ is calculated, and the center value of the four cells of the average value storage device 11B is calculated _. The data is stored in the cell S ₂₀₀ located at (e in the same figure), and the same process is performed by sequentially shifting the data one by one. In this way, average value data is stored in the average value storage device 11B at the center of the tangent to each divided cell of the storage device 9 as shown in FIG. 15. The data in the average value storage device 11B obtained in this way and the data in the storage device 9 are sequentially read out by the operation of the control circuit 11D, and the display image storage device 1
It is written to the corresponding address of 1C. As a result, the data arrangement of the display image storage device 11C obtained is as shown in FIG. Display image data is also stored in the .

If an image is displayed on the display device 10 based on the data stored in the display image storage device 11C, the density of shading becomes finer and the detection accuracy can be improved. Note that the arithmetic processing in the data processing device 11 may be performed based on various methods using a microcomputer.

According to the apparatus of the present invention described in detail above, compared to conventional diagnostic apparatuses, it is possible to exhibit optimal diagnostic functions in terms of ability to detect abnormal cells, safety, etc.
Furthermore, since the overall configuration of the device is simple, the device can be made smaller and less expensive. In particular, compared to mammoth scanners for breast cancer screening, the measurement area range can be set narrower, and even if there is variation in the distance between opposing electrodes, there is no risk of false detection, which improves diagnostic accuracy. It is also extremely safe in terms of safety against in-vivo currents. By the way, in the mammoth scanner, a current of about 100 μA is passed between the breast and the back, so there is a risk of direct damage to the heart, etc., whereas with the device of the present invention, the electrodes are placed between a narrow distance between the upper and lower surfaces of the breast. It is extremely safe to use because the current applied is very small and there is no risk of direct damage to the heart. Furthermore, since it is easy to operate, it is particularly effective when used as a device for mass medical examinations.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the principle of the conventional mammoth scanner.
Fig. 2 is a schematic diagram showing the state of living tissue, Fig. 3 is an electrical equivalent circuit diagram of living tissue, Fig. 4 is a diagram explaining the principle of the device of the present invention, and Fig. 5 is a block diagram of an embodiment of the device of the present invention. 6 is a circuit diagram of an embodiment of an integrating device used therein, FIG. 7 is a circuit diagram of an embodiment of a peak value detection and holding device similarly used therefor, and FIG.
9 is a circuit diagram of an embodiment of a timing control circuit used therein, FIG. 9 is a circuit diagram of an embodiment of a reference voltage generator similarly used therefor, and FIG.
11 is a block diagram showing another embodiment of the present invention. FIG. 12 is a time chart for explaining the operation. FIGS. 13 a and b 14 is a schematic diagram showing an example of the structure of an electrode used in the device of the present invention.
The figure is a block diagram of an embodiment of a data processing apparatus used in another embodiment of the apparatus of the present invention, and FIGS. 15 to 17 are matrix diagrams for explaining data processing aspects of the data processing apparatus. 2a, 2b...electrode, 3...integrator, 4a,
4b... Peak value detection and holding device, 5... Timing control circuit, 6... Reference voltage generator, 7... Division device, 8... Analog-to-digital converter, 9
... Storage device, 10 ... Display device, 11 ... Data processing device.

Claims (1)

[Scope of Claims] 1. At least a pair of electrodes disposed in close contact with a part to be measured in a living body, and voltage generating means for supplying first and second voltages of different frequencies between the electrodes;
a detection means for individually detecting first and second capacitance values obtained from the measurement site when first and second voltages are supplied between the electrodes; an abnormal cell characterized by comprising: a dividing means for calculating the ratio of the first and second capacitance values, and a display means for displaying the in-vivo tissue in shading based on the result of the dividing means. Detection device. 2. The abnormal cell detection device according to claim 1, wherein one of the pair of electrodes is an assembly of independent electrode cells. 3. The first and second frequencies are frequencies located before and after a frequency that causes structural dispersion in a frequency versus permittivity characteristic curve of cells existing in the measurement site. The abnormal cell detection device according to item 1 or 2.