JPS6334482B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a status monitoring device for plants such as power plants and chemical plants, and particularly to a monitoring device suitable for displaying data installed in an operation control panel.

Many monitoring instruments such as indicator needles and indicator lights are installed on the operation control panels of large-scale plants such as thermal power and nuclear power plants. In order to operate the plant safely and efficiently, operators judge whether or not an abnormality has occurred in the plant based on the readings of monitoring instruments, turning on and off lamps, etc., and take appropriate countermeasures. In large-scale plants such as thermal power and nuclear power plants, when an abnormality occurs that may impair the safety of the plant or its component equipment, an interlock is used to automatically shut down the plant or equipment that causes the abnormality, with safety first. I have to. Therefore, in order to increase plant operating efficiency, changes in plant data related to interlocks must be known in advance and appropriate precautions must be taken before interlock activation. Plant interlock circuits consist of complex logic circuits to avoid unnecessary plant shutdowns. In addition, monitoring instruments displaying plant data related to interlocks are widely distributed on the operation control panel. For this reason, the work of monitoring the plant operating state is a very burdensome work for operators.

An object of the present invention is to provide a plant status monitoring device that processes plant data related to interlocks, provides operators with margin until interlock activation, and allows operators to easily judge the operating status of the plant. It is to be.

In the present invention, the plant data input to the interlock circuit that stops the plant and equipment is grouped, and the margin until the interlock is activated is calculated based on the deviation from the steady value of each plant data in the group and the interlock conditions. The system is designed to be provided to operators who request it.

FIG. 1 is a diagram showing the overall configuration of the present invention, which includes a plant 1, an input device 2, an interlock circuit 3,
It consists of a calculation section 4 and a display section 5. A large amount of analog data (signals indicating various quantities) and digital data (binary signals indicating various opening/closing states, etc.) necessary for monitoring are input from the plant 1 into the input device 2 . The input device 2 takes in data from the plant 1 and sends the data to the interlock circuit 3 and the calculation section 4. The interlock circuit 3 performs calculations according to the internal logic circuit configuration based on the captured data, and sends an interlock condition signal, for example, a plant scram command 3A.

The arithmetic unit 4 groups the captured data for each part of the plant to be monitored, and calculates, for each group, the degree of margin of each piece of data constituting the group to the corresponding part Scrum. This margin calculation is performed by comparing a steady value (reference value) of data given for each data, a trip value, and actual input data. The next step is to perform a logical operation based on the calculated margin. The result of the logical operation between the margins is also calculated as the margin. This margin calculation is sequentially executed according to a model similar to the logic for forming the interlock condition, and finally, the margin for trip of the grouped corresponding parts is obtained.
The finally obtained margin is displayed on the display section 5. This makes it possible to visually check the margin for trips and scrums. In the above process, when a plurality of groups are formed, margin calculation is performed for other groups in the same way. Of course, the grouped items may be related to each other to perform more advanced trip and scrum margin calculations.

FIG. 2 is a diagram showing an embodiment in which the input device 2, the calculation section 4, and the display section 5 are further implemented. Input device 2
consists of an analog multiplexer _MPLI , an A/D converter _ADCi , and a digital scanner _DIi . The calculation unit 4 includes a margin determination device MCS _i and a display control unit.
Consists of DCS. This calculation section 4 is composed of, for example, a microcomputer. The display section 5 is a CRT
It consists of a display section DSP. The operation of this device will be described below using a nuclear power plant as an example. In Fig. 2, P ₁₁ , P ₁₂ , ..., P _1i are analog data such as pressure and flow rate related to the interlock circuit of the generator trip, and D ₁₁ , D ₁₂ , ..., D _1l are the analog data of the generator trip interlock circuit. This is digital data that indicates the opening/closing of valves, the status of operation switches, etc. related to the interlock circuit. P ₂₁ , P ₂₂ , ..., P _2j and D ₂₁ , D ₂₂ ,
... _D2n are analog and digital data related to the turbine trip interlock, P _N1 , P _N2 , ..., P _Nk and D _N1 , D _N2 , ...
..., D _No is plant data related to the water pump trip. Analog data of groups 1 to N, P ₁₁ to _{P 1i} , P ₂₁ to _{P 2j} , ..., P _N1 to _{P Nk} are multiplexers MPX ₁ to MPX _N and A/D (analog/digital) converters ADC ₁ to ADC _N The data are periodically taken into the margin determining devices MCS ₁ to MCS _N via the following. In addition, each group's digital data
D ₁₁ ~ D _1l , D ₂₁ ~ D _2n , ..., D _N1 ~ D _No are also connected to the margin determination device via digital scanners DI ₁ ~ DI _N
Periodically taken into MCS ₁ to MCS _N.

The margin determination devices MCS ₁ to MCS _N are the analog data of each group P ₁₁ to _{P 1i} , P ₂₁ to P _2j , ..., P _N1 to
Deviation from steady value of P _Nk and digital data D ₁₁
〜D ₁ , D ₂₁ 〜D _2n , ..., D _N1 〜 D _No. Calculate the margin until interlock operation from the interlock conditions described later, and calculate the margin signal I ₁ to I _N for each group. Send to display controller DCS. The display control device DCS outputs the margin signals I ₁ to I _N to a display device DSP using a CRT or the like in a format to be described later. In FIG. 2, in this embodiment, the margin determination devices MCS ₁ to MCS _N and the display control device DCS use microcomputers.

Below, the margin determination device which is the center of the present invention
The processing contents of MCS ₁ to MCS _N will be described in detail, but since the processing contents are the same for each group,
Here, we will describe the processing of the margin determination device MCS _M for determining the margin signal I _M until the reactor scram interlock operation, taking the Mth group as an example.

FIG. 3 shows a conceptual diagram of the reactor scram interlock circuit 3. In Figure 3, 11 to 14
indicates an AND gate, and 15 to 21 indicate an OR gate. As shown in FIG. 3, the interlock circuit is composed of an OR gate, an AND gate, and a time delay element (not shown in FIG. 3). Nuclear reactor scrams occur under various conditions as shown in FIG. Analog data for margin determination device MCS _M
From the values of P _M1 to P _M12 and digital data D _M1 to D _M6 and the same logic as the interlock conditions shown in FIG. 3, the margin up to the reactor scram is calculated by the method described below.

FIG. 4 shows the processing flow of the margin determination device MCS _M. In FIG. 4, in processing step _F1 , analog data P _M1 to _{P M12} and digital data D _M1
~ D _M6 is taken in periodically. In processing step _F2 , the analog data P _M1 captured in processing step F1 _is
~P Calculate how much margin there is until _M12 opens the AND and OR gates with reference to a table as shown in FIG. In Figure 5
The ADT table is an analog data table that stores the current values of periodically captured analog data P _M1 to _{P M12} , and PNT stores the steady values of each analog data P ^N _M1 to ^{P N} _M12 and trip values P ^T _M1 to P This is a constant table that stores ^T _M12 in advance. The trip values P ^T _M1 to ^{P T} _M12 are the logical products of the interlock circuits,
A value that opens the OR gate is set for each analog data. For example, analog data
In the case of the reactor water level of P _M4 , the steady value P ^N _M4 is set to 1150 mm, which is the data taken during normal operation, and the trip value P ^T _M4 is set to 273 mm ( (reactor water level low) is set. In addition to this, there is also an example in which the trip condition is set to rise. FIG. 6, which will be described later, shows an example of this. Furthermore, the margin calculation below also describes the opposite example. In processing step _F2 of FIG. 4, the margins I _M1 to I _M12 of each analog data are calculated by the following formula with reference to the analog data table ADT and constant table PNT shown in FIG. 5, and the margin table is calculated.
Store in IT.

When P ^N _Mi P _Mi I _Mi = 0 P ^N _Mi <P _Mi <P ^T _Mi When I _Mi = P _Mi −P ^N / _Mi /P ^T / _Mi −P ^N
/ _Mi P _Mi P ^T _Mi When I _Mi = 1 In this example, the plant data P _Mi is the trip value
The degree of margin I _Mi until reaching P ^T _Mi was calculated using a function as shown by the solid line in Figure 6. This function form is shown in the dotted line and dashed-dotted line in Figure 6, taking into account each analog data change state. It may be calculated using various functional forms such as Further, although the steady value P ^N _Mi of each plant data is set in advance as a constant in this embodiment, there is data that changes depending on the plant state. For example, among the analog data shown in FIG. 3, the steady-state values of the reactor pressure, power range neutron monitor, etc. change depending on the output level of the plant. For such analog data, a steady value may be obtained by calculation from the plant state, and the value of P ^N _Mi in the constant table PNT may be periodically updated.

Next, in processing step _F3 of FIG.
Interlock conditions are determined as follows by referring to the interlock table INTLOK shown in the figure. The interlock table INTLOK is a table that stores the input/output relationship of the interlock circuit in advance and is configured as follows. In FIG. 7, a indicates the type of logic element of the interlock circuit, and a=1 for logical sum, a=2 for logical product, and a=3 for delay element. b specifies the number of inputs to the logic element. However, in the case of a delay element, specify the delay time in seconds in b. c ₁
~c _o specifies the input data to the logic element. Here, for analog data, the number of the margin table IT shown in Figure 5 is used, and for digital data, the number of the digital data table that stores the data periodically fetched in processing step _F1 of Figure 4 is used. specify. d specifies the number of the margin table IT that stores the margin calculation results. As a specific example of a table, examples created for logic models corresponding to logic elements 16, 17, and 12 in FIG. 3 are shown at T ₆ , T ₇ , and T ₂ in FIG. 7.

In processing step _F3 the interlock table
Referring to INTOK, calculate the margin for each logic element as follows.

(1) In the case of logical sum.

The maximum value among the margins of each input data is set as the output. For example, for the table T ₆ , T ₇ , I _M20 = _Max {I _M7 , I _M8 ), I _M21 = _Max {I _M9 ,
D _M3 }. That is, in the case of a logical sum, a value having a margin as close as possible to "1" in the input data is selected as the output.

(2) In the case of logical product.

The minimum value among the margins of each input data is set as the output. For example, for a table of T ₂ I _M22 =
Let M _io {I _M20 , I _M21 }.

(3) For time delay elements.

The time delay element of the interlock circuit operates as follows. For example, when the delay time is Δt seconds, if the input data continues to be “1” for Δt seconds, the output becomes “1”. Therefore, in the case of a time delay element, the minimum value of the data Δt seconds before the current time is selected as the output.

As described above, the margin I _M until the reactor scram is calculated by referring to the INTLOK table.
The margin I _M up to reactor scram calculated in processing step _F3 in FIG. ₄ is sent to the information display control device DCS in processing step F4.

As described above, the margin determination device which is the center of the present invention
Although the processing contents of MCS _M have been described using the reactor scram as an example, other margin determination devices MCS ₁ to _{MCS M-1} ,
Regarding the processing of MCS _M+1 to MCS _N , the only difference is the input data, and the processing contents are the same. Further, in this embodiment, a distributed system is used in which one microcomputer is used for each group, but if a microcomputer with a large memory capacity is used, processing can be performed with one microcomputer.

The margin signals I ₁ to _IN sent from the margin determination devices MCS ₁ to MCS _N are displayed on the display device DSP in various formats by the information display control device DCS.

Display examples using a CRT as the display device DSP are shown in FIGS. 8 and 9. FIG. 8 is an example in which the current value of the margin is displayed in a bar graph. Further, FIG. 9 is an example of trend display of changes in margin over the past hour, where time 0 indicates the current margin. The display shown in FIG. 9 is an example of a display in which the past history can be monitored, and at the same time, future predictions can be made from changes in the margin.

The embodiments of the present invention have been described above. According to this embodiment, it is possible to easily provide a margin for interlock operation for plant shutdowns and equipment shutdowns such as reactor scrams, turbine trips, and water supply pump trips in nuclear power plants. It is possible to judge.

According to the present invention, the degree of margin until interlock activation for plant stoppage and start-up stoppage can be calculated from the changing state of plant data related to each interlock and the interlock conditions, and can be provided in an easy-to-understand format to operators. . Therefore, the plant condition monitoring device of the present invention allows the operator to intensively monitor the plant condition, which has been judged from a large number of instruments in the past, and the monitoring work of the operator can be reduced. In addition, since the margin until interlock activation can be easily monitored, countermeasures can be taken early before abnormalities occur in the plant, preventing abnormalities such as plant shutdowns and equipment shutdowns, and enabling efficient plant operation. becomes.

[Brief explanation of the drawing]

Figure 1 is an overall configuration diagram of the present invention, Figure 2 is a diagram of a specific embodiment of the present invention, Figure 3 is a conceptual diagram of the reactor scram interlock, and Figure 4 is the processing flow of the margin determination device. , Fig. 5 is a related diagram of the table for margin calculation, Fig. 6 is an explanatory diagram of the function form for margin calculation, Fig. 7 is a configuration diagram of the interlock table, and Figs. 8 and 9. is a diagram showing an example of displaying the degree of margin. DESCRIPTION OF SYMBOLS 1... Plant, 2... Input device, 3... Interlock circuit, 4... Arithmetic unit, 5... Display unit.

Claims (1)

[Claims] 1. In a system comprising an interlock circuit that interlocks a plant according to an interlock judgment condition consisting of a combination of logical product, logical sum, and delay elements, the devices are grouped to correspond to the interlock. monitoring means that takes in the plant data obtained and monitors the margin up to the interlock according to margin determination conditions that are the same as the interlock determination conditions of the interlock circuit; an input unit that receives the same plant data as the lock circuit; a means for comparing each data with a steady value and a trip value for each plant data to calculate a margin for each plant data; and a margin for each plant data. is used as the input data for the margin determination condition instead of the plant data, and the logical product element in the margin determination condition outputs the minimum value of the plurality of margins input to the element as the next stage margin, The OR element outputs the maximum value of multiple margins input to the element as the next stage's margin, and the delay element delays the input margin by the delay time and outputs it as the next stage's margin. A plant condition monitoring device comprising: a margin interlock determination unit that performs a margin interlock determination unit; and a display unit that displays the determination output.