JPS6334496B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a channel buffer control method in a data processing system that includes a channel buffer in a main memory control section.

(b) Background of the Technology As data processing systems have recently become larger and faster, input/output devices connected to the data processing systems have also become faster.

In order to cope with the trend toward faster speeds of input/output devices (i.e., to improve channel throughput and prevent overruns in input/output devices), channel buffers are installed in the main memory control section located between the main memory device and the channel. There is a known method for increasing the memory access speed seen from the channel.

However, mainly low speed input/output devices are connected to the channel. There are multiplexer channels, block multiplexer channels to which high-speed input/output devices are connected, and selector channels. For example, for multiplexer channels that transfer data only in 8-byte units, the channel buffer function described above is There is a problem in that the channels are not fully utilized, and it has been desired to study a channel buffer control system that is suitable for the three types of channels mentioned above.

(c) Prior art and problems In general, channels include a block multiplexer channel (hereinafter referred to as BMC), a selector channel (hereinafter referred to as SLC), and a multiplexer channel (hereinafter referred to as SLC).
There are three types of channels (hereinafter referred to as MXC).

From the perspective of the main memory control unit (hereinafter referred to as MCU), BMC and SLC have the characteristic that read data and write data are transferred in a unit during a read or write operation.
In the case of MXC, read and write operations are mixed,
It also has the characteristic that it is transferred in units of 8 bytes.

In a data processing system in which the above MCU has a built-in channel buffer (hereinafter referred to as CHB), due to the characteristics of CHB, it is difficult to process the transfer data from the three types of channels equally for the sake of "efficient use of CHB". There are the following problems. In other words: Decreased usage efficiency of CHB: In memory access from MXC, read and write are mixed, and addresses are not continuous, but are accessed in units of 8 bytes, so when CHB is used, In response to a memory access request, even if the relevant data does not exist in the CHB and one block of 64 bytes is prepared from the main storage unit (hereinafter referred to as MSU), the above 8
Only one byte will be used, and the remaining 56 bytes will most likely be discarded.

Decreased efficiency of memory access from the central processing unit: When accessing CHB from MXC and the relevant data block does not exist in CHB, when accessing MSU and transferring, what would normally be an 8-byte access is , are accessed in blocks of 64 bytes, so the interleaving unit of the MSU corresponding to the 64 bytes becomes busy and cannot be accessed during the access time of the MSU, so the memory from the central processing unit is There was a problem that made access less efficient.

(d) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention provides that, in a data processing system in which a channel buffer is built in the main memory control unit, when a channel processor performs memory access to the main memory control unit, the access request signal is Add a flag specifying the type of memory access in , perform memory access,
It is an object of the present invention to provide a method in which a main memory control unit identifies, using the flag, the type of channel that is accessing the memory, and controls the channel buffer.

(e) Structure of the Invention According to the present invention, a main storage device, a central processing unit and a channel processor that perform data transfer with the main storage device, and a main storage device, a central processing unit, and a channel processor that perform data transfer with the main storage device. A main memory control unit that controls data transfer between processors, and a channel buffer provided within the main memory control unit that temporarily stores data transferred between the channel processor and the main memory device. In a system that
The interface of the main memory control unit to the channel processor is provided with a storage means for setting a flag indicating the amount of data to be transferred and the priority of access to the main memory, and the channel processor sets a flag in the storage means. The main memory control unit recognizes the type of channel processor that accessed the main memory device from the amount of transferred data indicated by the flag, so that read and write to the main memory device are mixed and a small amount of data is transferred. A method of selecting a channel processor to perform a main storage, prohibiting writing of data to the channel buffer, and setting the priority of access to the main storage device lower than the priority of other channel processors based on the priority indicated by the flag. In the case of memory access from a multiplexer channel, the channel buffer is controlled not to be used, so there is an advantage that the channel buffer can be efficiently controlled.

(f) Embodiments of the Invention First, to summarize the gist of the present invention, in the present invention, in a data processing system that includes a channel buffer in the main memory control unit, memory access is performed from the channel processor to the main memory control unit. In this case, the memory access is performed by adding a flag specifying the type of channel for the memory access to the access request signal, and the main memory control unit uses the flag to identify the type of channel for the memory access. For example, if the flag indicates a memory access from a multiplexer channel (MXC), in the case of a fetch request, an 8-byte memory fetch is performed and it is not registered in the channel buffer. The fetch data is directly transferred to the channel processor, and even in the case of a store request, the 8-byte data is written directly to the main memory without writing to the channel buffer.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a diagram showing an example of the configuration of a data processing system to which the present invention is applied, FIG. 2 is a block diagram showing an example of the configuration of a channel buffer (CHB), and FIG. ) is a diagram showing an example of the configuration of a tag section.

In Figure 1, 1 is the main storage unit (MSU), 2
is a central processing unit (hereinafter referred to as CPU), and 3 is a channel processor (hereinafter referred to as CHP).
There are 16 channels connected to the CHP. 4
is the main memory control unit (MCU), which has a built-in channel buffer (CHB) 41. The CHB consists of 2 ways (64 bytes/way), and 2 ways are allocated to each channel.

First, before explaining the general operation of the CHB 41, the tag section of the CHB 41 will be explained with reference to FIG.

The tag section of the CHB 41 related to the present invention consists of a control section (CTRL) and an address section (ADDR).

Since the transfer unit for CHB41 is 64 bytes, the address part (ADDR) is for addresses 1 to 25.
It consists of bits and their parities P0 to P3.

The control unit (CTRL) is composed of the elements shown below. That is: V: Valid bit indicating the validity of the block.

F: FIRST IN indicating whether the block is new or old
It's bit. and: F=1: New (indicating recently registered).
F=0: Old, subject to move-out/replacement. Normally, at the point when it changes to 10, C=
If it is 1, put it in the move out queue.

C: Indicates that the block is stored from CHP3. Logically, BM0~BM described later
This is a logical sum signal of 7.

Pv: Parity bit for the above V, F, and C bits.

BM0 to BM7: Byte marks for each 8 bytes of a 64-byte block. When each bit is on, it indicates that all of the corresponding 8 bytes have been written.

PB: Parity bit for BM0 to BM7.

In this embodiment, the tag part is CHP0/
1 and 3, and 32 lines per way for each channel (i.e. 16 channels x 2 CHP)
It consists of two ways.

Therefore, the CHB 41 is accessed using the CHP number and channel number.

Based on Figures 1, 2, and 3 below, CHP
An outline of the memory access operation from 3 will be explained.

In FIG. 2, 5 is a CHP address register (CHPAR), 51 is a flag register (F) that identifies the type of channel necessary for implementing the present invention, 6 is a channel identification register (CHIDR), and 61 is a CHP
The number identification section 62 is a +1 circuit and is used to initialize the channel buffer tag section (CHB TAG) and the channel buffer data section (CHB, DATA). Reference numerals 70 and 71 are channel buffer tag sections (hereinafter referred to as CHB TAG), which indicate way 0 and way 1, respectively. 80 and 81 are comparison circuits (C) provided for each way;
The contents of CHP address register (CHPAR) 5 and
CHB TAG70, 71 address section (ADDR)
are compared bitwise, and if they match, a match signal is generated.
Output MCH0,1. 9 is a converter, which outputs logic “1” when the match signal is MCH0, and outputs a match output.
When it is MCH1, it outputs logic "0". 10 is
The CHB address register (CHBAR) 101 is a match way number register (CWNR) to which the output of the converter 9 is set. 11 is the data section of the channel buffer (hereinafter referred to as CHB DATA), 1
2 is CHB data register (CHBDR), 13 is
CHP store data register (CHPSTDR), 1
4, 15, CHP fetch data register (CHPFCHDR).

Now, when memory access is performed from CHP3 to MSU1, the memory address is set in the CHP address register (CHPAR)5,
The channel identification register (CHIDR) 6 has the channel number to which the memory was accessed, and the CHP number identification section 61 has the channel connected to it.
BHP number is set.

and channel identification register (CHIDR) 6
CHB TAGs 70 and 71 are accessed using the contents of the CHP number identification section 61 as an address, the address section (ADDR) is read out, and the comparison circuit (C) 80 and 81 reads the contents of the CHP address register (CHPAR) 5. The contents are compared.

According to the above comparison results, control is performed as follows. That is: In the case of fetch access from CHP: 1 If either the match output MCH0 or 1 is obtained, the output signal is converted to 1/0 by the converter 9, and the match way number register (CWNR) 1
01, and the contents of the channel identification register (CHIDR) 6 and CHP number identification section 61 are set to CHB address register (CHBAR).
10, CHB DATA11 of CHB41 is accessed using the contents of CHB address register (CHBAR) 10 and the contents of match way number register (CWNR) 101 as an address, and the read output data is stored in the CHP fetch data register (CHPFCHDR). )14,1
5, and the fetch data is sent to the CHP 3.

2 In case of mismatch: Since there is no data to be fetched in CHB41, it is necessary to move in from MSU1 to CHB41. However, CHB
The move-in operation differs depending on the contents of the TAG control section (CTRL). “V=1,1 and C=1,
1” In this case, both ways 0 and 1 are V=1,
In addition, since C=1, the data in the way on the F=0 (that is, old data) side is transferred to MSU1.
After moving out to MSU1 in the same way
The data block at the address is moved in from the CHP 3, and the move-in data is bypassed (however, only the first 8 bytes) and sent to the CHP 3. (Hereinafter, the meaning of bypass is the same.) "When V = 1, 1 and C ≠ 1, 1" In this case, the V bit is 1 in both ways 0 and 1, but the C bit is 1 in way 0. ，
Since one of the 1's is 0, the move-in data is moved in to the way on the C=0 side, and the move-in data is bypassed and sent to the CHP 3.

"When V≠1,1" In this case, the V bit of one of the ways is 0, so the move-in is performed to the way on the V=0 side, and the move-in data is bypassed.
It is sent to the relevant CHP3.

If the fetch data is not pure data such as command address word (CAW) or channel command word (CCW), fetch access is performed with the highest priority, and the fetch data (8-byte data) is bypassed and directly sent to CHP3. Sent out. That is, no move-in operation is performed for CHB 41.

In addition, F of the control part (CTRL) of CHB TAG70
Bits are updated upon move-in.

In the case of store access from CHP: 1 If a matching output is obtained: For the way with C=0, the channel identification register (CHIDR) 6 and the CHP number identification unit 61
CHB TAG70,
71 to set C=1, and store data previously set in the CHB data register (CHBDR) 12 with the CHB address register (CHBAR) 10 obtained by the method explained at the time of fetch access. Using the contents of the matching way number register (CWNR) 101 as an address, CHB DATA 11 of the CHB 41 is accessed and stored in the corresponding block.

For the way C=1, the store data is then stored in the corresponding block.

2 In case of mismatch: "When V = 1, 1 and C = 1, 1" Read the data of the way on the F = 0 side to the CHP store data register (CHPSTDR) 13,
After moving out to MSU1, write store data to the same way.

At this time, the F bit of the corresponding way is set to logic “1”.
The F bit of the other way is set to logic "0". That is, the F bit is updated.

“When V=1,1 and C≠1,1” Write store data to one of the ways where C=0, set the F bit of that way to logic “1”, and set the other way to logic “0”. shall be.

“When V≠1,1 and C=0” Write store data to the way on the V=0 side. The data on the C=1 side is registered in the moveout queue, and the F bit is updated.

"When V≠1,1 and C=0" Store data is written to the way on the V=0 side and the F bit is updated.

The operation of memory access from CHP3 has been explained above, but when the present invention is implemented,
For the interface from CHP3 to MCU4,
Two flag bits, DATA (hereinafter referred to as D) and PRIORITY (hereinafter referred to as P), are provided, and the MCU 4 reads the two flag bits D and P and determines the CHP.
3, the type of channel that is accessing the memory is identified, and the memory access operation corresponding to the type is controlled.

In the following, CHP when implementing the present invention
The operation for CHB 41 from 3 will be explained.

First, the basic meanings of the flag bits D and P will be explained.

D=1: Indicates continuous data transfer.

D=0: indicates data transfer in units of 8 bytes,
Command address word (hereinafter referred to as CAW), channel command word (hereinafter referred to as CCW), dynamic address translation (hereinafter referred to as DAT) table fetch, channel status word (hereinafter referred to as CSW)
This applies to stores and memory accesses (fetch, store) from MXC related to the present invention.

P=1: Indicates that an access request is issued to the main storage device 1 with the highest priority.

P=0: Indicates that an access request is issued to the main storage device 1 with normal priority.

In the present invention, the following states are defined by combining the above two bits D and P.

(1) "When D, P = 0, 0" Indicates that the data section memory access is from MXC. .

(2) "When D, P = 0, 1" CAW, CCW, DAT table fetch,
Memory access via CSW store (MXC,
BMC, SIC).

(3) "When D, P = 1, 0" Indicates that the data section memory access is from a source other than MXC (ie, BMC, SLC).

(4) “When D, P = 1, 1” Mark as an unused flag.

Hereinafter, the fetch access will be explained assuming that it is a fetch access from the data section.

Among the above cases, case (3) is the conventional
This is the same as the case of memory access to CHB 41, and control is performed to perform the aforementioned fetch and store operations for CHB 41.

In cases (1) and (2), the same control is performed except that case (2) issues a memory access request to MSU 1 with the highest priority.

Case 1 is the operation when the present invention is implemented, and its details will be explained below.

"For Fettu Access" CHP number, channel number, CHB TAG70
, and perform the following control based on the reference result.

Case of address mismatch: This case applies to most fetch accesses from MXC.

In this case, 8-byte fetch access is activated for MSU1. Do not register fetish data from MSU1 to CHB41,
Simply sending it directly to CHP3 ends this fetch access.

In the case of address match: Simply set the data read from CHB DATA 11 in CHB 41 to either CHP fetch data register (CHPFCHDR) 14 or 15, and then send it to CHP 3.
This process ends.

"For store access" CHP number, channel number, CHB TAG70,
71 and performs the following control based on the reference result.

Case of address mismatch: This case applies to most store accesses from MXC.

In this case, 8-byte store access is activated for MSU1. And CHB41
It is controlled not to write to.

If the address matches and C=0: Invalidate the corresponding block of CHB41 (V=0
After that, an 8-byte store access is made to MSU1, but no write is performed to CHB41.

When the address matches and C=1: After moving out the relevant block of CHB41 to MSU1 and invalidating that block (setting V=0), an 8-byte store access is performed to MSU1, but Writing to CHB41 is not performed.

The operation when implemented in the present invention has been explained above, but in the present invention, from CHP3 to MCU4
When accessing a memory, a flag (D, P) indicating the type of channel for accessing the memory is sent along with the memory address, and if the flag is
Indicating memory access from MXC, in the case of a fetch request, an 8-byte memory fetch is performed and the CHP is directly accessed without registering in CHB41.
3, and in the case of a store request, the key point is that it is controlled to write 8-byte data directly to the MSU 1 without writing to the CHB 41 even in the case of a store request.

(g) Effects of the Invention As explained in detail above, the channel buffer control method of the present invention provides a data processing system with a built-in channel buffer in the main memory control unit, in which an interface from a channel processor to the main memory control unit is controlled. A flag is provided in the ACE, and the main memory control unit recognizes the flag to identify the type of channel that accesses the memory, changes the control for the channel buffer according to the type of channel, and controls the access from the multiplexer channel. In the case of memory access, both fetch and store operations are controlled so that no registration or writing is performed in the channel buffer, resulting in efficient channel buffer control.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the configuration of a data processing system to which the present invention is applied, Figure 2 is a diagram showing an example of the configuration of a channel buffer (CHB), and Figure 3 is an example of the configuration of the tag section of the channel buffer (CHB). FIG. In the drawing, 1 is a main storage unit (MSU), 2 is a central processing unit (CPU), 3 is a channel processor (CHP), 4 is a main memory control unit (MCU), 41 is a channel buffer (CHB), and 5 is a CHP address register (CHPAR), 51 is flag register (F), 6 is channel identification register (CHIDR), 6
1 is a CHP number identification section, 70 and 71 are channel buffer tag sections (CHB TAG), 80 and 81 are comparison circuits (C), 10 is a CHB address register (CHBAR), 101 is a matching way number register (CWNR), 11 12 indicates a channel buffer data section (CHB DATA), 12 indicates a CHB data register (CHBDR), 13 indicates a CHP store data register (CHPSTDR), and 14 and 15 indicate a CHP fetch data register (CHPFCHDR), respectively.

Claims (1)

[Scope of Claims] 1 A main storage device 1, a central processing unit 2 and a channel processor 3 that perform data transfer with the main storage device 1, and a main storage device 1, a central processing unit 2 and a channel processor 3 that perform data transfer with the main storage device 1, a main memory control section 4 that controls data transfer between the channel processor 3 and the main memory device 1; and a channel buffer 41 provided within the main memory control section 4 that temporarily stores data transferred between the channel processor 3 and the main memory device 1. In the system, a storage means 51 is provided at the interface of the main memory control unit 4 to the channel processor 3 for setting a flag indicating the amount of data to be transferred and the priority of access to the main memory 1, The main memory control unit 4 recognizes the type of channel processor 3 that accessed the main memory device 1 from the amount of transferred data indicated by the flag set by the channel processor 3 in the storage means 51.
A channel processor that performs read and write operations on the main memory device 4 at the same time and transfers a small amount of data is selected, and is prohibited from writing data to the channel buffer 41, and is selected based on the priority indicated by the flag. A channel buffer control method characterized in that the priority of access to device 1 is set lower than the priority of other channel processors.