JPS633478B2 - - Google Patents
Info
- Publication number
- JPS633478B2 JPS633478B2 JP53074399A JP7439978A JPS633478B2 JP S633478 B2 JPS633478 B2 JP S633478B2 JP 53074399 A JP53074399 A JP 53074399A JP 7439978 A JP7439978 A JP 7439978A JP S633478 B2 JPS633478 B2 JP S633478B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply wiring
- circuit board
- signal lines
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 本発明は混成集積回路基板の改良に関する。[Detailed description of the invention] The present invention relates to improvements in hybrid integrated circuit boards.
従来、高集積化され、かつ大電力消費を伴なう
混成集積回路基板においてはパターンの形成方法
として、信号線と電源配線を同一面内に設ける方
法は、多層構造にして、信号線と電源配線を層別
に分離する方法の２種類が主に実施されている。
しかるに前者は、電源電圧変動を少なくするため
電源配線を信号線に比べ数倍以上太くする必要が
あるので、基板内の信号線の形成可能本数が減少
し、高集積化が難しいという欠点がある。後者は
通常、いわゆる厚膜ペーストを利用して実現され
る多層配線基板等に見られるものであり、第１図
にその断面図を示したように、絶縁基板１の上に
電源配線２を設け、その上に絶縁層３を設け、信
号線４と６を絶縁層５を介して二層に設けた構造
を有する。しかしこの構造では信号線の形成可能
本数を減少させずに電圧変動の少ない電源を供給
することが可能であるが、信号線４，６と電源配
線２との間の静電容量が大きくなり信号線の特性
インピーダンスは低くなり、高速動作回路基板と
しては不適当となる。これは、信号線４，６と電
源配線２の間に存在する絶縁層３，５によるもの
であり、通常使用されている厚膜絶縁層の場合、
その比誘電率は10〜20、膜厚は30μｍから60μｍ
程度なので静電容量は1.5PF／mm2から6PF／mm2程
度となるためである。 Conventionally, the pattern formation method for hybrid integrated circuit boards that are highly integrated and consume a large amount of power has been to provide signal lines and power supply wiring on the same plane by creating a multilayer structure, Two types of methods are mainly used: separating wiring into layers.
However, in the former case, the power supply wiring must be several times thicker than the signal line in order to reduce power supply voltage fluctuations, which reduces the number of signal lines that can be formed on the board, making it difficult to achieve high integration. . The latter is usually seen in multilayer wiring boards etc. that are realized using so-called thick film paste, and as shown in the cross-sectional view of FIG. It has a structure in which an insulating layer 3 is provided thereon, and signal lines 4 and 6 are provided in two layers with an insulating layer 5 interposed therebetween. However, with this structure, it is possible to supply a power supply with little voltage fluctuation without reducing the number of signal lines that can be formed, but the capacitance between the signal lines 4 and 6 and the power supply line 2 increases, and the signal The characteristic impedance of the line becomes low, making it unsuitable for use as a high-speed operation circuit board. This is due to the insulating layers 3 and 5 existing between the signal lines 4 and 6 and the power supply wiring 2. In the case of the normally used thick film insulating layer,
Its relative dielectric constant is 10 to 20, and the film thickness is 30 μm to 60 μm.
This is because the capacitance is about 1.5PF/mm 2 to 6PF/mm 2 .
本発明の目的は、上記の欠点を除き高集積化が
可能でかつ高速動作に適した混成集積回路基板を
提供することである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit board that is capable of high integration and is suitable for high-speed operation, eliminating the above-mentioned drawbacks.
本発明は、信号線あるいはさらに絶縁層の形成
された回路基板上に、ポリイミド等の絶縁性有機
物フイルムを介して、電源配線を形成することに
より信号線の形成可能本数を減少させることなく
信号線と電源配線間の静電容量を小さくしたこと
を特徴とする。 The present invention provides signal lines without reducing the number of signal lines that can be formed by forming power supply lines on signal lines or on a circuit board on which an insulating layer is formed, via an insulating organic film such as polyimide. The feature is that the capacitance between the power supply wiring and the power supply wiring is reduced.
以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.
第２図は、本発明による信号線２層、電源配線
１層の混成集積回路基板である。セラミツク等の
絶縁基板１上に任意の方法で、信号線４，６及び
絶縁層５，８を形成する。必要な場合にはさらに
抵抗体等の形成も可能である。 FIG. 2 shows a hybrid integrated circuit board having two layers of signal lines and one layer of power supply lines according to the present invention. Signal lines 4 and 6 and insulating layers 5 and 8 are formed on an insulating substrate 1 made of ceramic or the like by any method. If necessary, it is also possible to form a resistor or the like.
次に該回路基板上に所望の形状及び膜厚を有す
る絶縁性有機物フイルム１０を接着剤９等により
被着する。絶縁性有機物フイルムの材料として
は、化学的安定性の点からポリイミド等が適当で
ある。絶縁性有機物フイルムの場合、印刷、焼成
あるいはスパツタリング等で形成する無機物絶縁
層に比べ膜厚の調整範囲がはるかに広く、容易で
あり、さらに比誘電率も３から４程度であり、無
機物絶縁層（例えばAl2O3、SiO2等）の1/3以下
である。次に絶縁性有機物フイルム１０上に電源
配線１１を任意の方法で形成する。この電源配線
１１の形成方法としては各種の方法が考えられる
が、大電力消費を伴なう回路基板では、所望の膜
厚を有する金属箔をラミネートする方法が電源配
線抵抗を低くする上で有効である。 Next, an insulating organic film 10 having a desired shape and thickness is adhered onto the circuit board using an adhesive 9 or the like. Polyimide or the like is suitable as the material for the insulating organic film from the viewpoint of chemical stability. In the case of an insulating organic film, the adjustment range of film thickness is much wider and easier than that of an inorganic insulating layer formed by printing, baking, sputtering, etc. Furthermore, the dielectric constant is about 3 to 4, making it easier to adjust the thickness of an inorganic insulating layer. (For example, Al 2 O 3 , SiO 2 etc.) is 1/3 or less. Next, a power supply wiring 11 is formed on the insulating organic film 10 by an arbitrary method. Various methods can be considered for forming the power supply wiring 11, but for circuit boards that consume a large amount of power, a method of laminating metal foil having a desired film thickness is effective in lowering the power supply wiring resistance. It is.
尚、絶縁性有機物フイルム上に電源配線を形成
後、該回路基板上に接着剤等により被着すること
も可能である。 It is also possible to form the power supply wiring on the insulating organic film and then adhere it to the circuit board using an adhesive or the like.
次に金属ワイヤー１２等により、回路基板上の
電極４と電源配線１１の間に必要な電気的接続を
行うことにより、本発明の混成集積回路基板が形
成される。半導体チツプ７等の実装は従来の混成
集積回路基板と同様に行なうことが可能である。
なお実施例では信号線２層電源配線層１層の場合
を示したが高集積化が要求される場合には、信号
線３層以上、電源配線２層以上の構造も可能であ
ることはもちろんである。 Next, the hybrid integrated circuit board of the present invention is formed by making necessary electrical connections between the electrodes 4 on the circuit board and the power supply wiring 11 using metal wires 12 and the like. The semiconductor chip 7 and the like can be mounted in the same manner as a conventional hybrid integrated circuit board.
Although the example shows a case with two signal lines and one power supply wiring layer, if high integration is required, a structure with three or more signal lines and two or more power supply wiring layers is of course possible. It is.
以上説明したように、本発明によれば、信号線
と電源配線を異つた層に形成するため、信号線の
高集積化が可能であり、且、信号線と電源配線の
間に絶縁性有機物フイルムを介しているため、無
機絶縁層の場合に比べ静電容量を小さくすること
ができ高速動作回路基板として充分な特性が期待
できる。 As explained above, according to the present invention, since the signal line and the power supply wiring are formed in different layers, it is possible to achieve high integration of the signal line, and furthermore, an insulating organic material can be used between the signal line and the power supply wiring. Since the film is used, the capacitance can be reduced compared to the case of an inorganic insulating layer, and sufficient characteristics can be expected as a high-speed operation circuit board.
また電源配線の形成も従来の印刷焼成あるいは
蒸着法等で形成する場合に比べ、金属箔のラミネ
ート法を利用すれば、導体抵抗の減少が容易とな
り、大電力容量の電源配線が可能となるため、そ
の効果は大である。 In addition, compared to forming power supply wiring using conventional printing and baking or vapor deposition methods, using the metal foil lamination method makes it easier to reduce conductor resistance, making it possible to create power supply wiring with a large power capacity. , the effect is great.
第１図は電源配線１層、信号線２層からなる従
来の混成集積回路基板の断面図、第２図は本発明
による信号線２層、電源配線１層からなる混成集
積基板の断面図である。
１……絶縁基板、２，１１……電源配線、３，
５，８……絶縁層、４，６……信号線、７……半
導体チツプ、９……接着剤、１０……絶縁性有機
物フイルム、１２……金属ワイヤー。
FIG. 1 is a sectional view of a conventional hybrid integrated circuit board consisting of one layer of power wiring and two layers of signal lines, and FIG. 2 is a sectional view of a hybrid integrated circuit board of the present invention consisting of two layers of signal wiring and one layer of power wiring. be. 1... Insulating board, 2, 11... Power supply wiring, 3,
5, 8... Insulating layer, 4, 6... Signal line, 7... Semiconductor chip, 9... Adhesive, 10... Insulating organic film, 12... Metal wire.
Claims (1)
成された回路基板上に絶縁性有機物フイルムを介
して電源供給用配線を形成したことを特徴とする
混成集積回路基板。1. A hybrid integrated circuit board characterized in that a power supply wiring is formed on a circuit board on which a desired pattern such as a circuit wiring layer, an insulating layer, etc. is formed, via an insulating organic film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7439978A JPS54164252A (en) | 1978-06-19 | 1978-06-19 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7439978A JPS54164252A (en) | 1978-06-19 | 1978-06-19 | Hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54164252A JPS54164252A (en) | 1979-12-27 |
| JPS633478B2 true JPS633478B2 (en) | 1988-01-23 |
Family
ID=13546060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7439978A Granted JPS54164252A (en) | 1978-06-19 | 1978-06-19 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54164252A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0463277U (en) * | 1990-10-04 | 1992-05-29 | ||
| JPH04111477U (en) * | 1991-03-19 | 1992-09-28 | 株式会社タク・プロジエクト | business card |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5816176Y2 (en) * | 1976-07-16 | 1983-04-01 | 三洋電機株式会社 | Large scale integrated circuit device |
-
1978
- 1978-06-19 JP JP7439978A patent/JPS54164252A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0463277U (en) * | 1990-10-04 | 1992-05-29 | ||
| JPH04111477U (en) * | 1991-03-19 | 1992-09-28 | 株式会社タク・プロジエクト | business card |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54164252A (en) | 1979-12-27 |
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