JPS633479B2 - - Google Patents
Info
- Publication number
- JPS633479B2 JPS633479B2 JP52033312A JP3331277A JPS633479B2 JP S633479 B2 JPS633479 B2 JP S633479B2 JP 52033312 A JP52033312 A JP 52033312A JP 3331277 A JP3331277 A JP 3331277A JP S633479 B2 JPS633479 B2 JP S633479B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- metal
- ceramic substrate
- mask
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
本発明は多層配線基板の上に薄膜配線を施す多
層配線基板の製造方法、特に大型高密度の多層配
線基板に薄膜配線の位置合せを正確にすることが
できる多層配線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer wiring board in which thin film wiring is formed on a multilayer wiring board, and in particular, to a multilayer wiring board that can accurately align thin film wiring on a large, high-density multilayer wiring board. The present invention relates to a method for manufacturing a substrate.
従来、多層配線構造を有する厚膜セラミツクス
基板に薄膜配線を施して大型高密度の多層配線基
板を製造するには第1図a〜kの工程図に示すよ
うに先ず基板1の上に位置合せマーク用金属2を
蒸着し(第1図b参照)次に写真蝕刻により位置
合せマーク3をつくり(第1図c〜f)、更に配
線用金属4の蒸着を行ない(第1図g参照)これ
を前記位置合せマーク3に薄膜配線パターンを位
置合せして写真蝕刻をなし(第1図h〜k)配線
部分5を形成する方法を採つている。この複雑な
操作を必要とする方法を用いている理由は薄膜微
細配線を施すためセラミツクス基板の表面を研磨
するので厚膜と薄膜との接続部であるバイア1a
が配線用金属蒸着膜の上から見えず配線用パター
ンを光学的方法で正確に位置合せをすることがで
きないためである。又別の方法でセラミツクス基
板上に厚膜法にて位置合せマークを形成する方法
は、セラミツクス基板が大型化すると配線印刷ペ
ーストの焼成時における収縮率の不安定により精
度の高い位置合せには不適当である。更に又周知
の手法であるフオトレジストを用いた「リフトオ
フ法」ではレジストに耐熱性がないため蒸着時に
基板加熱ができず従つてセラミツクスと配線金属
間で満足すべき強度が得られないことと、セラミ
ツクスには多数の空孔が存在するためレジストが
空孔に残存し除去及び洗浄が難かしい等の理由で
この方法も使用できない。 Conventionally, in order to manufacture a large, high-density multilayer wiring board by applying thin film wiring to a thick film ceramic substrate having a multilayer wiring structure, first, as shown in the process diagram of FIG. Mark metal 2 is deposited (see Figure 1b), then alignment marks 3 are created by photolithography (Figure 1c to f), and wiring metal 4 is further deposited (see Figure 1g). A method is adopted in which the thin film wiring pattern is aligned with the alignment mark 3 and photolithographically etched (FIG. 1h to k) to form the wiring portion 5. The reason for using this method, which requires complicated operations, is that the surface of the ceramic substrate is polished in order to apply thin film fine wiring, so the via 1a, which is the connection between the thick film and the thin film, is used.
This is because the wiring pattern cannot be accurately aligned by an optical method because it cannot be seen from above the metal vapor-deposited film for wiring. Another method of forming alignment marks on a ceramic substrate using a thick film method is that as the size of the ceramic substrate increases, the shrinkage rate during firing of the wiring printing paste becomes unstable, making it difficult to achieve highly accurate alignment. Appropriate. Furthermore, in the "lift-off method" using a photoresist, which is a well-known method, since the resist has no heat resistance, the substrate cannot be heated during vapor deposition, and therefore, satisfactory strength cannot be obtained between the ceramic and the wiring metal. This method cannot be used because ceramics have many pores and the resist remains in the pores, making it difficult to remove and clean.
したがつて本発明の目的は前記欠点を除き厚膜
セラミツクス基板の上に精度よく薄膜配線を施す
ことが簡単にできる多層配線基板の製造方法を提
供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a multilayer wiring board, which eliminates the above-mentioned drawbacks and allows thin film wiring to be easily and precisely formed on a thick film ceramic substrate.
このような目的を実現するため本発明では、導
体が充填された接続孔を有するセラミツク基板上
に耐熱性を有する透明な樹脂から成る膜を形成
し、この膜に配線パターン用の写真蝕刻を施して
マスクを形成した後、前記セラミツク基板を加熱
しつつその前記マスクを有する面に配線用金属を
蒸着し、しかる後、前記のマスクと該マスク上に
被着した前記の金属を除去することにより、セラ
ミツク基板に金属配線を形成することを特徴とす
るものである。 In order to achieve this purpose, in the present invention, a film made of heat-resistant transparent resin is formed on a ceramic substrate having connection holes filled with conductors, and this film is photo-etched for a wiring pattern. After forming a mask, heating the ceramic substrate and depositing a metal for wiring on the surface having the mask, and then removing the mask and the metal deposited on the mask. This method is characterized by forming metal wiring on a ceramic substrate.
以下図面を参照しながら本発明を詳細に設明す
る。第2図は本発明にかゝる実施例の各工程に於
ける断面図を示したものである。図において先ず
基板1の上に耐熱性透明塗料6としてポリイミド
を塗布乾燥し、(第2図B参照)更にこの上にホ
トレジスト7を塗布乾燥する。(第2図C参照)
このホトレジストを露光現像し、(第2図D参照)
次にポリイミド6をエツチングする。(第2図E
参照)次で残存しているホトレジスト7を除去し
(第2図F参照)配線金属8を蒸着する。(第2図
G参照)最後にポリイミド6を除去して完成す
る。 The present invention will be explained in detail below with reference to the drawings. FIG. 2 shows cross-sectional views at each step of an embodiment according to the present invention. In the figure, polyimide is first applied and dried as a heat-resistant transparent paint 6 on a substrate 1 (see FIG. 2B), and then a photoresist 7 is further applied and dried thereon. (See Figure 2 C)
This photoresist is exposed and developed (see Figure 2D).
Next, polyimide 6 is etched. (Figure 2 E
(See FIG. 2F) Next, the remaining photoresist 7 is removed (see FIG. 2F) and a wiring metal 8 is deposited. (See Figure 2G) Finally, polyimide 6 is removed to complete the process.
上記工程において、ホトレジストの露光時には
ポリイミド膜6、ホトレジスト膜7共に透明であ
るから容易にバイヤ1aを確認することができ
る。従つて厚膜と薄膜の配線パターンの位置合せ
は正確容易にできるのである。又配線金属を蒸着
する際、基板と配線金属の接着を良好にするため
約300℃の加熱を必要とするが、ポリイミドは耐
熱性に優れており、この加熱に耐え金属配線パタ
ーンも変形することはない。更に又ポリイミドの
除去も苛性カリ溶液、ヒドラジン等にて容易にで
きるのでセラミツクス基板の空孔に残存すること
もない。 In the above process, since both the polyimide film 6 and the photoresist film 7 are transparent during exposure of the photoresist, the via 1a can be easily confirmed. Therefore, alignment of thick film and thin film wiring patterns can be easily and accurately performed. Also, when depositing wiring metal, heating to approximately 300°C is required to ensure good adhesion between the board and wiring metal, but polyimide has excellent heat resistance and can withstand this heating without causing the metal wiring pattern to deform. There isn't. Furthermore, since the polyimide can be easily removed using a caustic potash solution, hydrazine, etc., it does not remain in the pores of the ceramic substrate.
以上説明した本発明は従来の方法に較べ、厚膜
セラミツク基板上に薄膜配線を施す際の位置合せ
が正確にできると共にその製造工程は簡略化され
ている。又配線金属をエツチングする必要がない
のでエツチング性の難易に拘らず自由に配線金属
を選ぶことができ、且つ信頼性の高い配線ができ
る。更に配線金属蒸着時に充分加熱ができるので
素子ボンデイング及び回路改造の為のボンデイン
グに対し充分強度の保証できる金属−金属間及び
金属−セラミツク間の密着性が得られる。 Compared to the conventional method, the present invention described above enables accurate alignment when thin film wiring is formed on a thick film ceramic substrate, and simplifies the manufacturing process. Furthermore, since there is no need to etch the wiring metal, the wiring metal can be freely selected regardless of the difficulty of etching, and highly reliable wiring can be achieved. Further, since sufficient heating can be performed during metal wiring deposition, metal-to-metal and metal-to-ceramic adhesion can be obtained to ensure sufficient strength for element bonding and bonding for circuit modification.
第1図は多層配線基板の従来の製造方法の工程
説明図、第2図は本発明にかかる多層配線基板の
製造方法の工程説明図である。
1……基板、2,4,8……蒸着金属、6……
ポリイミド、7……ホトレジスト。
FIG. 1 is a process explanatory diagram of a conventional method for manufacturing a multilayer wiring board, and FIG. 2 is a process explanatory diagram of a method for manufacturing a multilayer wiring board according to the present invention. 1...Substrate, 2, 4, 8... Vapor deposited metal, 6...
Polyimide, 7...photoresist.
Claims (1)
基板上に耐熱性を有する透明な樹脂から成る膜を
形成し、この膜に配線パターン用の写真蝕刻を施
してマスクを形成した後、前記セラミツク基板を
加熱しつつその前記マスクを有する面に配線用金
属を蒸着し、しかる後、前記のマスクと該マスク
上に被着した前記の金属を除去することにより、
セラミツク基板に金属配線を形成することを特徴
とする多層配線基板の製造方法。1. A film made of heat-resistant transparent resin is formed on a ceramic substrate having connection holes filled with a conductor, and a mask is formed by photo-etching a wiring pattern on this film, and then the ceramic substrate is By depositing a wiring metal on the surface having the mask while heating, and then removing the mask and the metal deposited on the mask,
A method for manufacturing a multilayer wiring board, characterized by forming metal wiring on a ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331277A JPS53118767A (en) | 1977-03-28 | 1977-03-28 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3331277A JPS53118767A (en) | 1977-03-28 | 1977-03-28 | Method of producing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53118767A JPS53118767A (en) | 1978-10-17 |
| JPS633479B2 true JPS633479B2 (en) | 1988-01-23 |
Family
ID=12383032
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3331277A Granted JPS53118767A (en) | 1977-03-28 | 1977-03-28 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53118767A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2507508B2 (en) * | 1988-01-18 | 1996-06-12 | 株式会社日立製作所 | Wiring pattern forming method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632800B2 (en) * | 1973-07-17 | 1981-07-30 |
-
1977
- 1977-03-28 JP JP3331277A patent/JPS53118767A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53118767A (en) | 1978-10-17 |
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