JPS6335129B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable logic array circuit, and more specifically, it has a plurality of writable memory cells, and by rewriting the memory contents thereof, it is possible to easily perform arbitrary logic functions. The present invention relates to a writable logic array circuit that can be programmed into a programmable logic array circuit.

A programmable logic array (hereinafter abbreviated as PLA) is a general-purpose logic integrated circuit that has a regular structure and can be programmed to realize any logic function, and is also a type of semiconductor memory device.

For many types of PLA, each logic function is realized by creating individual wiring masks during the manufacturing process or by blowing fuses pre-placed on the wiring using a special writing device. It is specialized and used according to the logical function. In other words, in many conventional PLAs, programs representing logical functions are fixedly stored, so
It cannot be rewritten at any time. This means that, for example, when developing a digital device that uses PLA, if there is a design change or correction due to a mistake, the PLA must be remade each time.
This will bring about a major disadvantage in terms of development period, costs, etc.

Generally, some semiconductor memory devices are writable in such a fixed memory that the stored contents can be changed at any time. PLA can also be made writable using this semiconductor memory device technology. As an example, it is a part of PLA.
Since the AND logic array performs an associative function, the special case of writable PLA is realized using conventional associative memory. However,
A feature of PLA is that its AND logic array stores three values: logical "1", "0", and "X" (indicating either "1" or "0"). , and the conventional associative memory device is 2
Since it stores values, storing the above-mentioned ternary values requires 20% of the cells that store binary values, resulting in an increase in circuit configuration and poor storage efficiency. As mentioned above, PLA is originally an element suitable for integration, but if it were made writable using conventional technology, the circuit scale would increase, making large-scale integration impossible.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a writable logic array circuit having a circuit configuration with high storage efficiency and suitable for large-scale integration.

According to the present invention, the ternary write input signal, which has three stable states and is input under the control of the write control signal, is stored in correspondence with the stable state, and the content stored in the stable state is converted into a binary value. A plurality of tristable memory cells that can be read associatively according to a predetermined rule according to a logic input signal, and a plurality of diodes that receive output signals from the tristable memory cells are arranged in a matrix. The plurality of logic input signals supplied to each row are commonly input to the plurality of tristable memory cells in the same row, and the output terminals of each column are connected to each other in common through the plurality of diodes. A writable logic array circuit comprising an AND logic array in which output signals of a plurality of said tristable storage cells in a column are ANDed, and the results of said AND operation for each column are outputted as a plurality of binary output signals. can get. and a writable logic array in which the write control signal is input to a selected column (or row) in the AND logic array, and the plurality of ternary write input signals are respectively input to each row (or column). A circuit is obtained. Furthermore, the AND logic array;
Consists of multiple diodes divided into multiple groups.
A writable logic array circuit with an OR logic array is obtained.

Alternatively, a writable logic array circuit can be obtained that includes the AND logic array and an OR logic array formed by arranging a plurality of bistable memory cells in a matrix. Furthermore, a writable logic array circuit is obtained, comprising the AND logic array, the OR logic array, and a write control circuit.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1 is a write control circuit, which outputs a write control signal input from the outside through a signal line 103 to any one of signal lines 104-1, . . . , 104-N. Further, a reset signal and a clock signal are supplied from the outside through signal lines 101 and 102, respectively. 2 is an AND logic array with M rows and N columns, in which M binary logic input signals are input from the outside through signal lines 201-1, . . . , 201-M, and N logic output signals are subjected to an AND operation. is output to signal lines 203-1 and 203-N. Furthermore, M ternary write input signals are input to the AND logic array 2 from the outside through signal lines 202-1,...,202.
-M, and the above-mentioned write control signal is also input through signal lines 104-1, . . . , 104-N. 3 is an OR logic array with L rows and N columns, and the output signal of the AND logic array 2 is inputted through signal lines 203-1, . . . , 203-N.
The L logic output signals that have been ORed are connected to the signal line 30.
1-1, ..., 301-L.

Next, this embodiment will be described in more detail with reference to FIGS. 2 to 7.

FIG. 2 is a block diagram showing a specific configuration of the write control circuit 1. As shown in FIG. Reference numeral 11 denotes a K-bit counter which, after being initialized by a reset signal on a signal line 101, receives a clock signal on a signal line 102 and sequentially counts the column numbers of the AND logic array 1. 12 is a decoder, which sends the K-bit output signal of the counter 11 to signal lines 105-1, . . . , 105.
- input through K and decoded to signal line 106-
1,..., 106-N. 13-1,...,
13-N is an AND gate, each of which is controlled by N output signals of the decoder 12, and only one of them can pass the write control signal input through the signal line 103. The write control signal is input in synchronization with the clock signal, and the counter 11 sequentially instructs the AND gates 13-
1,..., 13-N to its output signal line 104-
1, . . . , 104-N to the corresponding columns of the AND logic array 2. Although an example of the write control signal 1 is shown, the counter 11
can be replaced with a register or shift register, etc., and the column number of the AND logic array 2 can be arbitrarily designated from outside. Signal line 104-1...,
104-N may be connected to an external terminal and a write control signal may be directly supplied from the outside, but by accommodating a write control circuit like this example in one chip, the number of external terminals can be greatly increased. can be reduced to

FIG. 3 is a block diagram showing the configuration of the AND logic array 2.

21-11, . . . , 21-MN are tristable memory cells arranged in a matrix of M rows and N columns. A common binary logic input signal and a common ternary write input signal are input to the tristable storage cells in the same row;
Write control signals are simultaneously input to tristable memory cells in the same column. For example, the signal line 201 is connected to the tristable memory cells 21-11,..., 21...1N in the first row.
A binary logic input signal and a ternary write input signal supplied to the -1 and signal lines 202-1, respectively, are input to the tristable memory cell 21-1 in the first column.
A write control signal supplied to the signal line 104-1 is input to 1, . . . , 21-M1.

22-11,...,22-MN are diodes, and tristable memory cells 21-11,...,2, respectively.
1-MN output signals are received, and the output ends thereof are shared by each column and connected to signal lines 203-1, . . . , respectively.
203-N. Signal line 203-1,
. . , 203-N are also the output signal lines of the AND logic array 2, and are supplied with positive voltage from the power supply line 204 via resistors 23-1, . . . , 23-N, respectively. As a result, for example, the output signal of the tristable memory cell in the first column is transferred to the diode 22-1.
1,...,22-M1, and the result is output to the signal line 203-1, etc. The output signals of the tristable memory cells in the same column are ANDed and the result is is the signal 203-1,
..., 203-N.

Fig. 4 shows tristable memory cells 21-11,...,21.
- Shows the specific configuration of MN. 51, 52,..., 5
9 is a NAND gate. A binary logic input signal is provided through two signal lines 201a and 201b, represented by its affirmative signal _X1 and negative signal ₁ . The three direct write input signals are represented by three binary signals A, B and C and are provided through three signal lines 202a, 202b and 202c. Write control signal W is signal line 1
04 and NAND gates 51,5
2 and 53 to control the input of write input signals A, B and C. NAND gate 54,5
5 and 56 are configured to form a return loop and create three stable states, and store the input ternary signal according to these stable states. The memory content is
Output signals Y ₁ of NAND gates 54, 55, 56,
NAND gates 57, 58 and 5 are identified by Y ₂ , Y ₃ and the logic input signal X ₁ (and ₁ )
9 is read out associatively. Reference numeral 205 is an output signal line of this tristable memory cell, from which the read output signal Z is derived.

Referring to FIG. 5, the operation of the tristable storage cell of FIG. 4 will be more clearly explained. Here, the ternary signals “1”, “X”, and “0” are represented by a combination of three binary signals, respectively (1, 1, 0), (1,
0,1) (0,1,1). Further, the set (Y ₁ , Y ₂ , Y ₃ ) corresponding to each of the ternary signals corresponds to three stable states. FIG. 5a shows the relationship between (A, B, C) and (Y ₁ , Y ₂ , Y ₃ ) for each of the three values when W is 1. Although omitted, if W is 0
In this case, the values of (Y ₁ , Y ₂ , Y ₃ ) are maintained as they are. That is, this figure explains the relationship related to writing. For example, the write input signal (A,
If B, C) are set as (1, 1, 0) and a pulse is supplied to the write control signal W, the same ( _{1, 1, 0) is stored in (Y 1} , Y ₂ , Y ₃ ), and this becomes a ternary signal. This is the writing of “1”. FIG. 5b shows the relationship between the logic input signal X ₁ and the read output signal Z for each storage content (Y ₁ , Y ₂ , Y ₃ ). That is, there is an explanation of association rules related to reading out the same figure. For example, when (Y ₁ , Y ₂ , Y ₃ ) is (1, 1, 0), X ₁
If X 1 is set to 1, Z becomes 1, and if X ₁ is set to 0, Z becomes 0. This is reading of the storage state "1". In other words, such associative reading means that Z=X ₁ , Z
= 1, Z = ₁ , which is nothing but a logical output.

Referring again to FIG. 3, it is clear from the comparison with FIG. 4 that the signal lines 2d-1, . , 202-M are signal lines 202a, 202b, 202c, respectively.
Pay particular attention to the fact that it is made up of pairs.

In the AND logic array 2 configured in this way, the M ternary write input signals inputted through the signal lines 201-1,..., 201-M are configured so that the write control signals are input to the signal lines 104-1,..., 104. -N
are input through one of the lines and written simultaneously to each of the tristable storage cells of that selected column. Furthermore, when a write control signal is supplied synchronously from the write control circuit 1, each column is selected in turn, and if a total of M ternary write input signals are supplied to each column, all A desired ternary signal can be written into the tristable memory cell of the . Furthermore, M binary logic input signals are connected to signal lines 201-1,
..., 201-N, and the output signals read out associatively from each tristable memory cell are transmitted through diode connections in each column.
ANDed signal lines 203-1,...,203-
Output to N. That is, the output of the AND logic array 2 is N binary output signals obtained by AND operation controlled by the storage contents of each tristable storage cell of M logic input signals. Please refer to the following diagram for better understanding.

Referring to FIG. 6, this AND logic array 2
A specific example of how a logical function is realized is shown. As an example, the figure assumes that a ternary signal has already been written to each of the tristable memory cells 21-11, ..., 21-32 in a matrix of 3 rows and 2 columns. Therefore, some parts have been omitted. When logic input _{signals X 1} , ”, “X” are stored, so the output signal read from each is
X ₁ , ₂ , 1, and these are ANDed
An AND logic signal X _{1 2} , etc. is obtained _, and AND logic signals _{X 1 2} , ₁ When these AND logic signals are supplied to an OR logic array 3, which will be described later, a more complex logic function such as X _{1 2} + ₁ X _{2 3} is realized.

A few points to note regarding the configuration of AND logic array 2 will be described. Diode 22-11,
..., 22-MN, the mechanism for performing the AND operation is specifically specified as a representative example. Therefore, it is used in PLA etc. by conventional technology.
Any AND operation mechanism can be applied, and if, for example, the output of the NAND gate 59, which is the input to each diode, is an open collector, the diode may be omitted. A binary logic signal conveyed by two positive and negative signals can be converted to 1 by having an inverter in each tristable storage cell.
It can be transmitted as one signal. Regarding the supply of the write control signal and the ternary write input signal, for example, the relationship between rows and columns may be reversed, and any configuration that generally allows writing to the selected tristable memory cell may be used.

FIG. 7 is a circuit diagram showing a specific configuration of the OR logic array 3. 31-1,...,31- is the first
, and the first to second output signal lines 203-1, ..., 2 of the AND logic array 2.
03- has been received. 31-J,...,31-N
is the Lth set of diodes, and similarly
The Jth to Nth output signal lines 203-J, . . . , 203-N of the AND logic array 2 are received. The first set of diodes 31-1, . . . , 31- have their output ends in common and are connected to the signal line 301-1. Similarly, the Lth set of diodes 31-J,
..., 31-N share the output end with the signal line 301
- connected to L. Signal lines 301-1,...,30
1-L is also an output signal line for each row of the OR logic array 3, and one end is connected to a resistor 32-1,..., 3, respectively.
It is grounded via 2-L. With this configuration, the output signals of the AND logic array 2 that are input to the OR logic array 3 through the signal lines 203-1, . , ..., 301-L. According to this embodiment, the OR operation is based on a predetermined combination, but the advantage is that the configuration of the OR logic array 3 is simple.

FIG. 8 is a block diagram showing another embodiment of the present invention, in which the configuration of the OR logic array is different from the previous embodiment. Therefore, the write control circuit 1,
The AND logic array 2 and each signal line having the same reference numeral is constructed in the same manner as in FIG. 3' is an OR logic array according to this embodiment, which is composed of writable bistable memory cells as described later, and is connected to signal lines 302-1, . . . , 302.
-L, L binary write input signals are supplied from the outside through signal line 1, similar to AND logic array 2.
A write control signal is supplied through 04-1, . . . , 104-N.

Referring to FIG. 9, a specific configuration of the OR logic array 3' is shown. 33-11,...,3
3-LN is a bistable memory cell, which is arranged in a matrix of L rows and N columns. Each bistable storage cell in the same row is provided with a common binary write input signal, and each bistable storage cell in the same column is provided with a common write control signal and the output signal of AND logic array 2. For example, bistable storage cell 33 in the first row
A binary write input signal supplied through the signal line 302-1 is input to -11,..., 33-1N, and the bistable memory cells 33-11,..., in the first column are inputted.
Signal line 104-1 and signal line 2 to 33-L1
The write control signal supplied through each of 03-1 and the output signal of the first column of the AND logic array are input. 34-11,..., 34-LN are diodes, each of which is a bistable memory cell 33.
-11,...,33-LN output signals are received, and the output terminals are shared by each row, and the signal line 30
1-1, 301-L. Signal line 3
01-1,...,301-L is OR logic array 3'
It is also the output signal line of , and one end is connected to resistor 35-1,
..., 35-L. As a result, for example, the bistable memory cell 33-1 in the first row
The output signals of 1,..., 33-1N are connected to the diode 34.
-11,...,34-1N, and the result is output to the signal line 301-1.
The output signals of the tristable memory cells in the same row are ORed and the result is sent to the signal line 301-1,
..., 301-L.

FIG. 10 shows bistable storage cells 33-11,...,3
FIG. 3 is a circuit diagram showing a specific configuration of 3-LN. 6
1, 62, 63, 64 are NAND gates,
Configure the reset flip-flop. 2
The value write input signal is a set of signal lines 302a, 3.
02b, it is supplied as its affirmation signal D on the one hand and its negation signal on the other. At this time, a write control signal is input through the signal line 104, and the binary write input signal D is stored in the flip-flop. Reference numeral 65 denotes an AND gate, which gates one of the output signals of the AND logic array 2 inputted through the signal line 203 according to the above-mentioned stored contents, and outputs the gated signal to the signal line 303. That is, this bistable memory cell is
When the stored content is 1, one of the output signals of the AND logic array 2 inputted is passed through and output as is, and when the stored content is 0, 0 is always output.

Referring again to FIG. 9, signal lines 302-1,
..., 302-L are each a set of signal lines 302
a, 302b, and the binary write input signals supplied to each are signal lines 104-1,...,
The bistable storage cells of the selected column are written to by a write control signal provided through 104-N.
The output signals of the AND logic array supplied through the signal lines 203-1,..., 203-N are input to the bistable memory cells 33-11, 33-, respectively.
Only when the stored content of LN etc. is 1, it is transmitted to each diode 34-11, . . . , 34-LN, and an OR operation is performed in each column. That is, this
According to the OR logic array 3', the OR operation can be controlled by rewriting the storage contents of each bistable memory cell 33-11, . . . , 34-LN.

To summarize the above explanation, the effects of the present invention are that tristable memory cells can reduce the amount of circuitry and efficiently store ternary signals, and by providing a memory cell that includes these, electrically rewriting can be performed at any time to create arbitrary signals. The present invention provides a logic array circuit that performs logic operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing the configuration of the write control circuit 1, FIG. 3 is a block diagram showing the configuration of the AND logic array, FIG. 4 is a circuit diagram showing the configuration of the tristable memory cell, and FIGS. 5 a, b 6 is a block diagram showing an example of realizing a logic function using an AND logic array. FIG. 7 is a circuit diagram showing the configuration of an OR logic array.
Figure 9 is a block diagram showing another embodiment of the present invention.
The figure is a block diagram showing another configuration of the OR logic array, and FIG. 10 is a circuit diagram showing the configuration of a bistable memory cell. In the same figure, 1...Write control signal, 2...AND logic array, 3,3'...OR logic array, 13-1,...,13-N...AND gate, 21-11,...,21-MN ...Tristable memory cell, 22-11,...,22-MN...Diode, 23-1,...,23-N...Resistor, 51,
...,59...NAND gate, 31-1,...,3
1-N...diode, 33-11,...,33-
LN...Bistable memory cell, 34-11,...,34
-LN...Diode, 35-1,...,35-L
...Resistor, 61,...,64...NAND gate,
65...This is an AND gate.

Claims (1)

[Claims] 1. Having three stable states, storing a ternary write input signal controlled by a write control signal and inputting it in correspondence with the stable state, and inputting a binary logic input signal to A plurality of tristable memory cells whose contents stored in a stable state can be read associatively according to a predetermined rule are arranged in a matrix, and the output signals of the plurality of tristable memory cells are respectively transmitted. A plurality of diodes are provided in each column with their output terminals commonly connected, and a plurality of the tristable memory cells in the same row receive the same logic input signal, and a plurality of the tristable memory cells in the same column receive the same logic input signal. The output signal of the cell is subjected to an AND operation through the plurality of diodes, and when a plurality of the logic input signals are input to each row from the outside, the results of the plurality of AND operations are output to each column. What is claimed is: 1. A writable logic array circuit comprising an array and performing logical operations according to the storage contents of the plurality of tristable memory cells. 2. The plurality of tristable memory cells in the same row (or column) are supplied with the same ternary write input signal, and the plurality of tristable memory cells in the same column (or row) are simultaneously supplied with the write control signal. After receiving the supply,
When a plurality of the ternary write input signals are externally input to each row (or column) and at the same time, the write control signal is input to a selected column (or row), the plurality of ternary write inputs are input. 2. A writable logic array circuit as claimed in claim 1, comprising said AND logic array in which signals are simultaneously written to each of said plurality of said tristable storage cells of said selected column (or row). 3. It has three stable states, stores a ternary write input signal inputted under the control of a write control signal in correspondence with the stable state, and stores a binary logic input signal according to the stable state by inputting a binary logic input signal. A plurality of tristable memory cells whose contents can be read associatively according to a predetermined rule are arranged in a matrix, and a plurality of first memory cells each receive an output signal from the plurality of tristable memory cells. Diodes are provided in each column with their output terminals connected in common, and the plurality of tristable memory cells in the same row receive the same logic input signal, and the outputs of the plurality of tristable memory cells in the same column are supplied with the same logic input signal. The signal is ANDed through multiple said first diodes
When a plurality of logic input signals are input to each row from the outside, the results of the AND operation are output to each column.
A logic array and a plurality of second diodes each receiving a plurality of output signals of the AND logic array are divided into a plurality of groups and the output terminals of each group are connected in common. and an OR logic array in which an output signal is ORed for each set through the plurality of second diodes and output, and performs a logical operation according to the storage contents of the plurality of tristable memory cells. A writable logic array circuit featuring: 4. A plurality of the tristable memory cells in the same row (or column) are supplied with the same ternary write input signal,
The plurality of tristable memory cells in the same column (or row) are simultaneously supplied with the write control signal, and the plurality of ternary write input signals are inputted to each row (or column) from the outside. When a write control signal is input to a selected column (or row), the plurality of ternary write input signals are simultaneously written to each of the plurality of tristable storage cells of the selected column (or row). 4. The writable logic array circuit of claim 3, comprising said AND logic array. 5. It has three stable states, stores a ternary write input signal inputted under the control of a write control signal in correspondence with the stable state, and inputs a binary logic input signal to store the stored state according to the stable state. A plurality of tristable memory cells whose contents can be read associatively according to a predetermined rule are arranged in a matrix, and a plurality of first memory cells each receive an output signal from the plurality of tristable memory cells. Diodes are provided in each column with their output terminals connected in common, and the plurality of tristable memory cells in the same row receive the same logic input signal, and the outputs of the plurality of tristable memory cells in the same column are supplied with the same logic input signal. The signal is ANDed through multiple said first diodes
When a plurality of logic input signals are input to each row from the outside, the results of the AND operation are output to each column.
a logic array and a binary write input signal inputted under the control of the write control signal;
A plurality of bistable memory cells that receive one of the output signals of the AND logic array, gate it with its storage content, and output it are arranged in a matrix, and a plurality of bistable memory cells that receive the output signal of the plurality of bistable memory cells, respectively, are arranged in a matrix. Two diodes are provided in each row with their output ends connected in common.
A plurality of the bistable storage cells in the same column are connected to the AND
Provided with output signals from the same column of the logic array, the output signals of the plurality of bistable storage cells in the same row are ORed through the plurality of second diodes to output the plurality of bistable storage cells of the AND logic array. an OR logic array in which an output signal is input to each column and a result of the plurality of OR operations is output to each row, and according to the storage contents of the plurality of tristable memory cells and the plurality of bistable memory cells. A writable logic array circuit characterized in that it performs a logic operation. 6. The plurality of tristable memory cells in the same row (or column) are supplied with the same ternary write input signal, and the plurality of tristable memory cells in the same column (or row) are simultaneously supplied with the write control signal. After receiving the supply,
When a plurality of the three-value write input signals are externally input to each row (or another) and at the same time, the write control signal is input to a selected column (or row), the plurality of three-value write input signals the AND logic array in which a signal is simultaneously written to each of the plurality of tristable storage cells in the selected column (or row), and the plurality of bistable storage cells in the same row (or column) write to the same two or more bistable storage cells; A plurality of bistable storage cells in the same column (or row) are supplied with a value write input signal, and the plurality of bistable memory cells in the same column (or row) are simultaneously supplied with the write control signal, and a plurality of binary write input signals are input from the outside to each row (or column). ) and simultaneously, when the write control signal is input to a selected column (or row), the plurality of binary write input signals are input to the plurality of binary write input signals of the selected column (or row). each written to a bistable storage cell simultaneously.
6. A writable logic array circuit according to claim 5, comprising an OR logic array. 7. It has three stable states, stores a ternary write input signal inputted under the control of a write control signal in correspondence with the stable state, and inputs a binary logic input signal to store the stored state according to the stable state. A plurality of tristable memory cells whose contents can be read associatively according to a predetermined rule are arranged in a matrix, and a plurality of first memory cells each receive an output signal from the plurality of tristable memory cells. diodes are provided in each column with their output ends connected in common, and the plurality of tristable memory cells in the same row are supplied with the same logic input signal,
The output signals of the plurality of tristable memory cells in the same column are subjected to an AND operation through the plurality of first diodes, and when a plurality of the logic input signals are input to each row from the outside, the plurality of the AND operations are performed. an AND logic array in which the results of
A plurality of bistable memory cells that receive one of the output signals of the logic array, gate it according to its storage content, and output it are arranged in a matrix, and a plurality of second bistable memory cells that each receive the output signal of the plurality of bistable memory cells. diodes are provided in each row with their output terminals connected in common, and the plurality of bistable memory cells in the same column receive output signals from the same column of the AND logic array, and the plurality of bistable memory cells in the same column receive output signals from the same column of the AND logic array. The output signals of the stable storage cells are ORed through the plurality of second diodes, the plurality of output signals of the AND logic array are input to each column, and the results of the plurality of OR operations are outputted to each row. a write control circuit that selects columns of the AND logic array and the OR logic array one by one and supplies the write control signal, and a plurality of the tristable storage cells in the same row A plurality of the bistable storage cells in the same row are supplied with the same ternary write input signal and a plurality of the tristable and bistable storage cells in the same column are supplied with the same binary write input signal. simultaneously receives the write control signal, and externally sends a plurality of ternary write input signals to each row of the AND logic array, and a plurality of binary write input signals to each row of the OR logic array. When the write input signal is simultaneously input to a selected column of the AND logic array and the OR logic array, the plurality of ternary write input signals and two
A value write input signal is simultaneously written to each of the plurality of tristable storage cells and the bistable storage cells of the selected column, and the stored contents of the plurality of tristable storage cells and the plurality of bistable storage cells are What is claimed is: 1. A writable logic array circuit, characterized in that it performs logical operations according to the following.