JPS6336022B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a bus extension method used when extending a bus line in a microprocessor or the like.

Prior Art and Problems In microprocessor circuits, etc., when peripheral circuits are connected to a common bus connected to the processor, the number of circuits that can be connected to the bus line is determined by the standard, and the number of circuits that can be connected to the bus line is determined by the standard. cannot be connected, and if more connections are required, it is necessary to provide an extension adapter and connect to it.

FIG. 1 shows an example of a system configuration to which the conventional bus extension method and the present invention bus extension method are applied. In the figure, a processor (CPU) 1 connects a memory 3 and an input/output device (I/O) 4 via a master bus 2.
DMA type I/O 5 can be accessed. On the other hand, when it is necessary to add I/O, connect the slave bus 7 via the extension adapter 6,
The additional I/Os 8 and 9 are connected to this.

When such an extension adapter is installed, the capacity determined by its length and number of connections is added.
This causes the waveform of the transmitted signal to become blunt, so it is necessary to guarantee the leading and trailing edges of data and addresses transmitted via the bus.

FIG. 2 shows a conventional data transfer method during bus extension, and explains guaranteeing leading and trailing edges of data and addresses during writing. As shown in the figure, when the master bus sends the address and data and also sends the service outwrite *SVOW, which is a command to instruct writing, the address and data are sent to the slave bus via the bus extension adapter. *SVOW is sent. When a service in *SVI is generated indicating a response from a circuit connected to the slave bus, this signal is transmitted through the master bus via a bus extension adapter and returned to the processor, which allows the processor to read the *SVOW of the master bus. *SVOW of the slave bus stops accordingly. At this time, as shown in Figure 1, the leading and trailing edges of the address and data on the slave bus are guaranteed by delaying the slave bus command *SVOW by a time T ₁ from the address and data. The trailing edge guarantee was achieved by disabling the address and data after a time T ₂ from the slave bus command.

For this reason, the master bus unit must be designed with consideration to guaranteeing the trailing edge of the slave bus, and since units designed under this condition have a longer cycle time, systems that do not extend the bus There was a problem in that data transfer speed was compromised when used in

OBJECT OF THE INVENTION The present invention aims to solve the problems of the prior art, and its purpose is to provide special trailing edge guarantees for addresses and data on the slave bus even when the bus line is extended. The object of the present invention is to provide a bus extension method that allows the unit to be designed without any consideration.

Embodiment of the Invention FIG. 3 shows the configuration of an embodiment of the bus extension system of the present invention. In the same figure, 11, 12, 1
3 is a driver, 14 is a data latch, 15 is an AND circuit, 16 and 17 are NAND circuits, 18 is an OR circuit, 19, 20, and 21 are delay circuits, and 22 is a flip-flop (FF).

4 and 5 show a data transfer method during bus extension in one embodiment of the bus extension method of the present invention. Figure 4 shows the access timing of the additional I/O during reading,
FIG. 5 shows the master bus I/O access timing during writing.

The operation of the bus extension system of the present invention will be explained below based on these figures. When reading the expansion I/O, the processor (CPU) sends addresses *AB00 to 15 to the master bus as shown in Figure 4, and also sends an I/O read command *
IORC is set to “1”. In the bus extension adapter, when the *IORC signal of the master bus is set to "1", it controls the driver 13 to enable addresses *AB00 to *AB15 of the slave bus, and after 50nS via the delay circuit 20, the slave bus is Set the command *IORC signal to “1”. delay circuit 20
The 50nS delay in is for the leading edge guarantee of the address on the slave bus.

Expansion I/O whose address is specified by this
outputs data *DB00 to *DB15 to the slave bus, and also outputs a response signal *XACK. The bus extension adapter detects the *XACK signal of the slave bus, latches the data with the data latch 14, and outputs the *XACK signal to the master bus via the FF 22. At this time, the delay circuit 21 ensures the operation of the data latch 14 by delaying the data latch to some extent with respect to the data input. When the *XACK signal of the master bus becomes "1", the bus extension adapter changes the *IORC signal of the slave bus to "0". On the other hand, when the CPU detects the *XACK signal on the master bus, it sets the *IORC signal to "0" in 200nS and ends the read cycle. When the *IORC signal on the master bus becomes "0", the bus extension adapter controls the driver 13 to determine the address of the slave bus *
Disable AB00~15. At this time
The 200nS delay is for guaranteeing the trailing edge of the address on the slave bus.

When writing to master bus I/O, the fifth
As shown in the figure, addresses *AB00~15 and data *DB00~15 are sent from the CPU to the master bus.
is sent, and an I/O write command*
IOWC is set to “1”. bus extension adapter
When the *IOWC signal on the master bus is set to “1”, it controls drivers 11 and 13 and sends addresses *AB00 to 15 and data *DB00 on the slave bus.
~15 and through delay circuit 19
Set the *IOWC signal on the slave bus to “1” after 50nS.

On the other hand, the I/O on the master bus to which the address has been designated takes in data *DB00 to *DB15, and when finished, outputs a response signal *XACK to the master bus. Master bus *XACK signal is “1”
, the bus extension adapter is the * of the slave bus.
Set the IOWC signal to “0”. When the CPU detects the *XACK signal on the master bus, it sets the *IOWC signal on the master bus to "0" after 200nS and ends the write cycle. When the *IOWC signal on the master bus becomes “0”, the bus extension adapter
Controls drivers 11 and 13 to disable addresses and data on the slave bus.

The 200nS delay at this time is to ensure the trailing edge of the address on the slave bus, so that the slave bus address is maintained correctly when the master bus is accessed, and the slave bus I/O Malfunctions are prevented.

Effects of the Invention As explained above, according to the bus extension method of the present invention, when a read or write command sent from the processor along with an address is detected in the bus extension adapter, the command on the slave bus is turned on after a predetermined time. Guarantee the leading edge of the address on the slave bus by
Turns off the command on the slave bus when a peripheral circuit response signal to a processor read or write command is detected, and then turns off the address or data on the slave bus when the processor turns off the command after a predetermined period of time. Since the trailing edge of the address or data on the slave bus is guaranteed by this, special consideration must be given to guaranteeing the trailing edge of the address or data on the slave bus even if the bus line is extended. You can design the unit without having to worry about it.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of a system to which the conventional bus extension method and the present invention are applied, FIG. 2 is a diagram showing a data transfer method when extending the conventional bus, and FIG. FIGS. 4 and 5 are diagrams illustrating the configuration of an embodiment of the extension method, respectively, and are diagrams showing a data transfer method during bus extension in an embodiment of the bus extension method of the present invention. 1... Processor (CPU), 2... Master bus, 3... Memory, 4... Input/output device (I/O),
5...DMA type input/output device (I/O), 6...
...Bus extension adapter, 7...Slave bus, 8,
9... Expansion input/output device (I/O), 11, 12,
13...Driver, 14...Data latch, 15
...AND circuit, 16,17...NAND circuit, 1
8...OR circuit, 19, 20, 21...delay circuit, 22...flip-flop (FF).

Claims (1)

[Scope of Claims] 1. A slave bus 7 is connected to a master bus 2 connected to the processor 1 via a bus extension adapter 6, and the processor 1 sends an address ( In the bus extension method of reading or writing data (DB) by specifying AB), the bus extension adapter 6
When a read or write command (IORC, IOWC) sent with an address (AB) from The leading edge of the address (AB) is guaranteed, and when the response signal (*XACK) of the peripheral circuit to the command (IORC, IOWC) is detected, the response signal (*XACK) is sent to the master bus 2.
XACK) is output, and when the response signal (*XACK) from master bus 1 is detected, the commands (IORC, IOWC) on slave bus 7 are turned off,
Next, the processor 1 turns off the address (AB) or data (DB) of the slave bus 7 at the same timing as when it turns off the commands (IORC, IOWC) after a predetermined period of time. A bus extension scheme characterized by guaranteeing the trailing edge of AB) or data (DB).