JPS6336199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time slot replacement system in a digital data network.

In the conventional memory switch type time slot replacement system, when not only time slots are mutually replaced but also partial multiplexing and demultiplexing of some time slots, for example, the first
It is configured as shown in the figure. The figure shows input terminals 1-1 to 1-N for serial data signals, a time division multiplexing circuit 2, a serial/parallel conversion circuit 3, a first buffer memory 4 for temporarily storing parallel data signals, and a first buffer memory 4 for storing parallel data after conversion. Second buffer memory 5, parallel/serial conversion buffer memory 6, time division separation circuit 7, address switching circuit 8, time slot conversion memory 9-01~
9-20, an address generation circuit 10, and serial data output terminals 11-1 to 11-N, and an address switching circuit 12 is connected to the address input of the buffer memory 4. This address switching circuit 1
2 is connected to the output of a frame counter 14 connected to the frame synchronization circuit 13 and to the output of a time slot counter 15.

The output of the time slot counter 15 is sent to the time slot conversion memory 9-0 via the decoding circuit 16.
1 to 9-20.

The multiplexing and demultiplexing operation of the time slot replacement system configured as described above will be explained using the time charts shown in FIGS. 2 and 3. Here, input terminal 1
-1 to 1-N, especially 1-A, 1-B, 1-C,
An input signal having a universal format that is added to the four terminals of 1-D is the output terminal 11 of the multiplexed signal.
-N is multiplexed. The signal applied to the input terminal is an envelope signal consisting of a flag (hereinafter referred to as F) bit, data bits _D0 to _D5 , and a status (hereinafter referred to as S) bit as shown in Fig. 2a.
As shown in Figure _{2 b} to _e , data bytes _represented by A _D1 , _{A D2} . It has a universal form consisting of

When the data signals b to e in FIG. 2 are input, the time division multiplexing circuit 2 multiplexes each bit in accordance with the order of the input terminals, and then the serial/parallel converting circuit 3 converts the input terminals into multiplexed bits. Each address is converted into a parallel signal in envelope units. At the F bit position in FIG. 2f, each envelope is transferred to the buffer memory 4 and stored in the order of each address. Here, the timeslot conversion memories 9-01 to 9-20 store the numbers of output terminals that are desired conversion destinations corresponding to each input terminal. When a time slot number as shown in FIG. 2g generated by the time slot counter 15 is applied to the decoding circuit 16 in response to a timing signal from the address generation circuit 10, the time slot conversion memories 9-01 to 9-20 convert the number of timeslots into each time slot. Each memory is selected and addressed in accordance with the number as shown in Fig. 2h. 9-0 at this time
Each of the time slot conversion memories 1 to 9-20 has input terminals 1-A, 1- as shown in FIG.
The output terminal number "N" of the multiplexed signal is stored in the memory locations corresponding to B, 1-C, and 1-D in correspondence with the time slot of the multiplexed signal. That is, the time slot conversion memory 9 for time slot 1
-01 only at address "A", time slot conversion memory 9-02 only at address "D",
9-03 stores only address "B," 9-04 stores only address "C," 9-06 stores only address "A," and multiplexed signal output terminal number "N." Here, time slot conversion memory 9-01
~9-20 each address A, B, C, other than the above,
No conversion destination output terminal number is stored in the memory location corresponding to D.

This time slot conversion memory 9-01 to 9-
20 and buffer memory 4 are read out in address order for each time slot. That is, when the time slot is 1, the time slot conversion memory 9-01 is selected, and when the address is ``A'', the output terminal number ``N'' of the conversion destination is read out, is switched and selected by the address switching circuit 8, and is added to the buffer memory 5. It will be done. Therefore, at time slot 1, the parallel data at input terminal A stored in buffer memory 4 is read out at address "A", and is stored in buffer memory 5.
is stored at the address position of the output terminal 11-N as shown in FIG. 2j. The parallel data thus stored in the buffer memory 5 is stored at the address N of the parallel-to-serial conversion buffer memory 6 during the S bit time shown in FIG. 2k.

This parallel-to-serial conversion buffer memory 6 is sequentially read out using the address signal generated by the address generation circuit 10, and the separation circuit 7 performs parallel-to-serial conversion and separation corresponding to each output terminal, and reproduces it as a serial data signal as shown in FIG. Output to 11-N.

Next, at time slot 2, the parallel data signals A _S11 , B _S09 , stored in the buffer memory 4
When the data signal D _D1 at the input terminal D of C _S09 and D _D1 is at the address "D" of the time slot conversion memory 9-02, it is stored in the buffer memory 5 using the destination output terminal number "N" as the address. The parallel data signal stored in the buffer memory 5 is transferred to the parallel/serial conversion buffer memory 6 during the S bit time shown in FIG. is output as a serial data signal. Below, when time slot 3 is the parallel data of input terminal B _D1 , when time slot 4 is the parallel data of input terminal C
C _S101 , when the time slot is 6, the parallel data A _D2 of the input terminal A is transferred to the time slot conversion memory 9.
-03, 9-04, 9-06, the time slot is converted and output to the output terminal 11-N.
Therefore, the serial data signal at the output terminal 11-N is a signal obtained by multiplexing data from each of the input terminals 1-A, 1-D, 1-B, 1-C, . . . . Also, when addressing in each time slot other than the above, the time slot conversion memory 9-
Since no conversion destination address is stored in each of the address positions 01 to 9-20, the parallel data for these addresses read from the buffer memory 4 is not time slot converted.

As described above, the time slot conversion memory 9-01
By storing the same output terminal number only in the memory location of the address position of the time slot conversion memory corresponding to the time slot to be multiplexed in the memory of 9-20, multiplexing operation can be performed only by time slot conversion. will be carried out.

Next, a case will be described in which the data of each time slot of the multiplexed signal applied to the input terminals 1-N is separated using the time chart shown in FIG.
Figure a shows an envelope similar to Figure 2 a,
Figure b shows the time slot. When the hyperactivity signal shown in figure c is applied to the input terminals 1-N, the second
Similar to the operation described in the figure, the data is multiplexed in the multiplexing circuit 2 together with data signals from other input terminals, and then converted into parallel data in the serial/parallel converting circuit 3. Here, the F bit of data from the input terminals 1-N is applied to the frame synchronization circuit 13 to synchronize the frame of the multiplexed signal, and the time slot is output from the frame counter 14 in response to the time slot of the multiplexed signal. The lot number is output and added to the buffer memory 4 via the address switching circuit 12. According to the time slot number from the frame counter 14 and the address from the address generation circuit 10, the parallel data signals at the input terminals 1-N are stored in the buffer memory 4 as shown in FIGS. 3e to 3i. Here, e, f, g, h, and i in Figure 3 represent the accumulated contents of the buffer memory 4 for the addresses of input terminals 1-N at time slots ``1'', ``2'', ``3'', ``4'', and ``20'', respectively. It shows. This buffer memory 4 is sequentially read out using addresses from the address generation circuit 10.

Here, time slot conversion memory 9-01,9
-02, 9-03, 9-04, 9-06 in the memory locations corresponding to input terminals 1-N, respectively.
D, B, C, and A are stored. As shown in j and k of the same figure, this time slot conversion memory 9-
01 to 9-20 correspond to the time slot numbers of the time slot counter 15, and the decoding circuit 16
is selected for each time slot number, and the memory contents are added to the buffer memory 5 via the address switching circuit 8.

For example, when the time slot counter 15 is the time slot number "1" and the address generation circuit 10 is at the input terminal 1-N, the address N and time slot 1 are added to the buffer memory 4 and the parallel data is
A ₁ is read. At this time, the memory content "A" is read out from the time slot conversion memory 9-01 as _shown in FIG. It is stored as shown in A ₁ in Figure M. Thereafter, as in FIG. 2, the data is stored at address A of the buffer memory 6 at the S bit time in FIG. 3q. This data is read out in the order of the addresses from the address generation circuit 10, subjected to parallel-to-serial conversion and separation in the separation circuit 7, and then reproduced into serial data A _D1 shown in FIG. 3r, which is output to the output terminal 11-A.

Next, when the time slot counter 15 has the time slot number "2", parallel data is transferred from the memory location corresponding to the input terminals 1-N of the buffer memory 4.
D ₁ is read out and the time slot conversion memory 9
-02 to memory contents "D" shown in Figure 3 l
is stored in the buffer memory 6 as a conversion destination address, and is thereafter outputted as a serial data signal D _D1 in FIG. 3I to the output terminal 11-D through the same process as in time slot 1. At this time, the memory contents at address A of the buffer memory 5 are not transferred from the buffer memory 4, so the memory contents remain as _A1 , and this is transferred to the output terminal via the parallel-serial conversion buffer memory 6 and the separation circuit 7. 11-A as A _S11 in Figure 3r. This is a staff byte with the same contents as A _D1 described above, and is a universal format signal.

Similarly, as shown in n, o, and p in the figure, when the time slot number is 3, parallel data _B1 is read out from the buffer memory 4, and the memory content "B" is read out from the time slot conversion memory 9-03.
Accordingly, it is output as a serial data signal to the output terminal 11-B as B _D1 in FIG. 3s. When the time slot number is 4, parallel data _C1 is read from the buffer memory 4, time slot converted according to the memory content "C" from the time slot conversion memory 9-04, and a serial data signal is sent to the output terminal 11-C. It is output as C _D1 in Figure 3 t.

As described above, the multiplexed signal applied to the input terminal 1-N is sent to the output terminals 11-A and 11-B according to the contents stored in the time slot conversion memories 9-01 to 9-20 for each time slot. ,11-C,1
1-D as universal format signals.

However, the conventional time slot conversion memory 9
-01 to 9-20, in order to perform multiplexing and demultiplexing operations, memory for the number of time slots in the multiplex line frame is required for each address where each time slot is replaced, and the multiplexing It is necessary to maintain a time slot conversion memory even for lines that do not perform time slot switching, and to keep the memory contents of the corresponding addresses in the time slot conversion memory the same for normal time slot switching operations. If the number of time slots is 20 and the number of bits required to represent the number of input lines N in binary is N', a large capacity memory of (N x N' x 20) bits is required. It becomes necessary. For example, in the case of N=256 lines, N'=8 bits, so a memory of 256×8×20=40960 bits is required. Furthermore, it is necessary to store unused portions of the memory area and the same information, resulting in a large amount of waste, and has the disadvantage that it is not suitable for miniaturization and economicalization of the device. Further, even if the number of multiplexed lines is one, a memory amount twice as large as the number of time slots is always required for demultiplexing.

The purpose of the present invention is to eliminate the drawbacks of the conventional
It is an object of the present invention to provide a time slot replacement method suitable for downsizing and economical equipment by reducing the memory amount of a time slot replacement table for performing a separation operation.

The time slot switching method of the present invention includes a multiplexing circuit that multiplexes input data signals, a serial-to-parallel conversion circuit that converts the serial signal obtained at the output of this circuit into a parallel signal, and the output of this circuit as input. a first buffer memory, a second buffer memory inputting the output of this buffer memory, a buffer memory for parallel-to-serial conversion to which a signal read from this buffer memory is guided, and a separation circuit that separates the output of this buffer memory; In the time slot switching method, the time slot conversion memory includes a time slot conversion memory storing the number of an output terminal which is a predetermined conversion destination for each input terminal in order to perform time slot conversion. It has a lot switching memory, a multiplexing time slot memory, a time slot interval memory, and a time slot conversion memory for separation, and the output of the time slot switching memory and the time slot conversion memory for separation correspond to the output of the multiplexing flag memory. One of the outputs of the lot conversion memory is added as the address of the second buffer memory, and when the time slot numbers of the multiplex time slot memory and the output of the time slot counter match, the multiplex time slots are exchanged and the multiplex time slots are exchanged. The integrated time slot memory is calculated and updated according to the time slot interval memory, and for separation from the multiplexed signal, a pseudo address is stored in the time slot switching memory, and a pseudo address is stored in the time slot exchange memory, and a pseudo address is associated with the address and the time slot number. Separation time slots are exchanged using the output of the separation time slot memory as the address of the second buffer memory, and for time slot exchange for each time slot, the time slot interval memory is set to "1", and the time slot interval memory is set to "1". The present invention is characterized in that the multiplex time slot memory is set to an initial state of "1" and the multiplex time slots are exchanged.

Next, embodiments of the present invention will be described using the drawings. FIG. 4 is a block diagram showing an embodiment of the present invention. In this figure, the same parts as in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted. In Fig. 1, the time slot conversion memories 9-01 to 9-20 have capacity equal to the number of time slots of multiplexed frames, but
In the figure, it is divided into a time slot conversion memory 9 and a separation time slot conversion memory 18, and one of the outputs of both is applied to the address switching circuit 8 through a switching circuit 17. The time slot counter 15 is connected to the address switching circuit 12 and the comparison circuit 19, and its output is connected to the address generation circuit 10.
The gate circuit 20 is connected to the gate circuit 20 .
The time slot conversion memory 9 is internally subdivided into a multiplex flag memory 91, a time slot exchange memory 92, a multiplex time slot memory 93, and a time slot interval memory 94. The output of the slot memory 93 is applied to the arithmetic circuit 21, and the output of the arithmetic circuit 21 is again connected to the input of the multiplexed time slot memory 93.

The multiplexing and demultiplexing operations of the time slot replacement system configured as described above will be explained using the time charts shown in FIGS. 5 and 6. First, referring to FIG. 5, as in FIG. 1, input terminals 1-1 to 1-N
A case will be described in which universal format input signals applied to four terminals 1-A, 1-B, 1-C, and 1-D are multiplexed to the output terminal 11-N.
FIG. 5a shows an envelope similar to FIG.
Similarly to FIG. 2, when the data signals shown in FIG. 5 b to e are applied, the time division multiplexing circuit 2 inputs
After bits are multiplexed in the order of 1-2,...1-N,
The serial-to-parallel conversion circuit 3 converts each address corresponding to each input terminal into parallel signals in envelope units.
The data is stored in the buffer memory 4 in address order at the F bit time shown in FIG. The time slot conversion memory 9 is read out in the order of each address for each time slot as shown in FIG.

First, at time slot 1 (TS1), the memory locations of the time slot conversion memory 9 corresponding to each input terminal 1-A, 1-B, 1-C, and 1-D are as follows.
As shown in FIG. 5 m1 to m4, the address of the multiplexing flag time slot replacement destination, the multiplexing time slot number, and the multiplexing time slot interval are the multiplexing flag 91 and the time slot replacement memory 9, respectively.
2. Stored in multiplexed time slot memory 93 and time slot interval memory 94. That is,
At time slot 1, multiplexing flag memory 9
A multiplexing instruction flag 0 is stored in each address position of 1. At each address position of the time slot switching memory 92, the output number "N" of the multiplexed signal is stored.
However, the multiplexed time slot memory 93 has "1" in address A, "3" in address B, "4" in address C, and "2" in address D, and "5" in address A of time slot interval memory 94. "10" is stored in address B, "20" is stored in address C, and "5" is stored in address D.

At address A of time slot 1, the flag "0" from the multiplexing flag memory 91 causes the switching circuit 17 to apply the output "N" of the time slot switching memory 92 to the buffer memory 5 through the address switching circuit 8. It can be switched as follows. At this time, the time slot number "1" from the multiplexed time slot memory 93 is compared with the time slot number of the time slot counter 15 in the comparator circuit 19, and a coincidence pulse like n in FIG. 5 is applied to the gate circuit 20. , the fifth signal obtained by NANDing the timing signal from the address generation circuit 10
The _write pulse of FIG. The parallel data in the buffer memory 5 is read out at address N at the S bit time in FIG.
After being stored in the address N of the buffer memory 6 for parallel-serial conversion, the buffer memory 6 for parallel-serial conversion is sequentially read out using the address generated by the address generation circuit 10, and the separation circuit 7 separates the parallel-serial conversion corresponding to each output terminal. Then, it is outputted to the output terminal 11-N as the serial data signal shown in FIG. 5l. On the other hand, the time slot "1" from the multiplexed time slot memory 93 and the time slot interval "5" from the time slot interval memory 94 are added in the arithmetic circuit 21, resulting in "6" as shown in FIG. The data is stored in the multiplexed time slot memory 93 by the write pulse shown in FIG. 5o.

Next, at addresses B, C, and D of time slot 1, the outputs of the multiplexed time slot memory 93 are "3", "4", and "2", respectively, and the comparator circuit 19
When compared with time slot ₁ , since no matching pulse is output as _shown in _FIG . 5 cannot be stored at address N.

Addresses A, B, of time slot 2 (TS2)
At time C, time slots ``6'', ``3'', and ``4'' are output from the multiplexed time slot memory 93, and are compared with time slot 2 of the time slot counter 15 in the comparator circuit 19, and a match is found as shown in FIG. 5n. Since no pulse is output, the serial data signals A _S11 , B _S09 , C _S019 of buffer memory 4 are output from buffer memory 5.
cannot be stored at address N. time slot 2
At address D, time slot "2" is output from the multiplexed time slot memory 93, and compared with time slot 2 of the time slot counter 15 in the comparator circuit 19, and a matching pulse is output as shown in FIG. 5n. Ru. At this time, due to the flag 0 from the multiplexing flag memory 91, the output "N" of the time slot switching memory 92 is added to the address of the buffer memory 5 through the switching circuit 17 and the address switching circuit 8. The parallel data signal D _D1 at address D is stored in the buffer memory 5 as shown in FIG. 5j by the write pulse shown in FIG. 5o. When address N is S bit time in FIG.
After storing the data, the data is parallel-serial converted and separated through the separation circuit 7, and outputted to the output terminal 11-N as shown in FIG. 5I.

Hereinafter, when address B of time slot 3 (TS3), a coincidence pulse is obtained in the comparator circuit 19, and when the parallel data signal B _D1 of buffer memory 4 is at address C of time slot 4 (TS4), a coincidence pulse is obtained. are obtained, and the parallel data signals C _S101 of the buffer memory 4 are respectively time slot-switched and outputted to the output terminals 11-N as the serial data signals shown in FIG. 5I, where they are multiplexed.

The multiplexed time slot memory 93 and the time slot interval memory 94 are outputted for each time slot address and applied to the arithmetic circuit 21, and the arithmetic results are added to the input of the multiplexed time slot memory 93. However, the comparator circuit 19 When the time slot does not match the time slot of the time slot counter 15, no matching pulse and write pulse are obtained, so the multiplexed time slot memory 93 is not updated.

Also, at address C of time slot 4,
A match pulse is output. At this time, the arithmetic circuit 21
, a multiplexing time slot of ``4'' and a time slot interval of ``20'' are added. The result of this addition is 24
The number of time slots in the multiplexed signal frame is
Since it exceeds 20, 20 is subtracted, and the calculation result "4" is input to the multiplex time slot memory 93 and stored.

As described above, the multiplexed time slot memory 93
The outputs of the buffer memory 4 and the time slot counter 15 are compared in the comparison circuit 19, and only when they match, the time slot is converted from the buffer memory 4 to the buffer memory 5, and the time slot exchange memory 92
The multiplexing operation can be performed simply by storing the same multiplexed output terminal number N at a desired address position and performing time slot conversion only when the comparison circuit matches.

Next, a case will be explained in which the data of each time slot of the multiplexed signal applied to the input terminals 1-N is separated using the time chart shown in FIG.
Figure a shows an envelope similar to Figure 5a,
Figure b shows the time slot. When the multiplexed signal shown in figure c is applied to input terminals 1-N, the fifth
As described in the figure, the data is bit-multiplexed by the multiplexing circuit 2 for each address together with data from other input terminals, and then converted into parallel data by the serial/parallel converting circuit 3. Here, F bits of data from terminals 1-N are applied to the frame synchronization circuit 13, the frame synchronization of the multiplexed signal is achieved, and the frame counter 14 is set in correspondence with the time slot of the multiplexed signal.
The time slot number is outputted from the address switching circuit 12 and added to the address input of the buffer memory 4, and the parallel data of the multiplexed signal at the input terminals 1-N is sent to the buffer memory 4 at the F bit time in FIG. 6d. The data are stored as shown in Figures 6e to 6h.
Here, the data in FIGS. 6e to 6h show the contents stored in the buffer memory 4 at time slots "1", "2", "3", and "4" of the multiplexed signal, respectively.

The time slot counter 15 uses the timing signal generated by the address generation circuit 10 to
A time slot number such as . . . is output, and for each time slot, the time slot conversion memory 9 is read out in the order of the address of each input terminal.

First, at time slot 1 (TS1),
As shown in m1 to m4, the demultiplexing instruction flag "1" is sent from the multiplexing flag memory 91 corresponding to the address N of the time slot conversion memory 9, and the pseudo conversion address "n'" is sent to the time slot exchange memory 92. , "1" is stored in the multiplexed time slot memory 93, and "1" is stored in the time slot interval memory 94.

At this time, the switching circuit 17 is switched by the flag "1" from the multiplexing flag memory 91, and the output of the separated time slot conversion memory 18 is added to the address input of the buffer memory 5 via the address switching circuit 8. There is. At this time, the pseudo address "n'" from the time slot exchange memory 92 is added to the separated time slot conversion memory 18 together with the output of the time slot counter 15, and the conversion of time slot 1 of the multiplexed input terminals 1-N is performed. The first address "A" is output from the separated time slot conversion memory 18 as shown in FIG. 6q.
Also, the time slot "1" from the multiplexed time slot memory 93 is stored in the time slot counter 15.
It is compared with the output of n in the comparator circuit 19, and
A coincidence pulse such as is applied to the gate circuit 20,
It is NAND gated together with the timing signal from the address generation circuit and applied to the buffer memory 5 and the multiplexed time slot memory 93 as the write pulse shown in FIG. Therefore buffer memory 4
The parallel data signal _A1 of time slot 1 at address N is stored at the address A location of buffer memory 5 as shown in FIG. This buffer memory 5
The parallel data of is read out at address A of the S bit time in FIG. It is output as a serial data signal of w. On the other hand, the time slot "1" from the multiplexed time slot memory 93 and the time slot interval "1" from the time slot interval memory 94 are added in the arithmetic circuit 21, and as shown in FIG.
The signal becomes "2" and is stored in the multiplex time slot memory 93 by the write pulse shown in FIG. 6o.

Next, at time slot 2 (TS2) in FIG. The parallel data D1 of FIG. 6f in the buffer memory 4 is stored in the buffer memory ₅ as shown in FIG. 6u using the address "D" as shown in FIG.
This signal is parallel-serial converted and separated through a parallel-serial conversion buffer memory 6 and a separation circuit 7, and is outputted to an output terminal 11-D as a serial data signal as shown in FIG. 6j. At this time, since the parallel data at address A of buffer memory 5 is not time slot converted from buffer memory 4, it remains the parallel data A1 that was time slot converted from address N of buffer memory 4 at time slot 1, and this is the same as time slot 2. At address A of S bit time of
The data A in FIG. 6 w is output to A as _S11 .

Similarly, the contents of the buffer memory 5 shown in s and t in the figure and the terminals 11-B and 1 shown in x and y in the same figure
Referring to the output of 1-C, parallel data B1 is sent to the output terminal 11-B at time slot 3 (TS3) in the same figure j, and parallel data C1 is sent to the output terminal 11-C at time slot 4, respectively. output as a format signal. Also, at this time,
The multiplexed time slot memory 93 sequentially stores "4"
It is updated as "5", "6", etc.

Here, the memory capacity of the time slot conversion memory 9 and the time slot conversion memory 18 for separation is as follows, where N' is the number of bits required to represent the number of input lines N in binary, and M is the number of lines for multiplexed signals.
Since the number of time slots is 20, 5 bits are required to represent it in binary.
N′×20)] bits of memory. For example, N=
256, in the case of M = 8 lines, N' = 8 bits, so 256 x (1 + 8 + 5 + 5) + (8 x 8 x 20) =
It becomes 6144 bits.

As is clear from the above explanation, the time slot replacement method according to the present invention greatly reduces the amount of memory in the time slot conversion memory, and unlike normal time slot conversion, the same information is repeatedly stored in the time slot conversion memory. There is no need to store it, and there is no waste. In addition, when there is only one multiplexed line, the amount of memory for time slot conversion memory for demultiplexing is further reduced, and as in the past, there is no longer a need for memory times the number of time slots for constant demultiplexing. This has the effect of making it more compact and economical.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional example; Figure 2;
Figure 3 is a time chart showing the operation of Figure 1.
FIG. 4 is a block diagram showing one embodiment of the present invention, and FIGS. 5 and 6 are time charts showing the operation of FIG. 4. 1-1 to 1-N...input terminal, 2...time division multiplexing circuit, 3...serial to parallel conversion circuit, 4, 5...buffer memory, 6...buffer memory for parallel to serial conversion, 7...time division separation circuit, 8, 12, 17... Address switching circuit, 9, 9-01 to 9-20... Time slot conversion memory, 10... Address generation circuit, 11-1
~11-N... Output terminal, 13... Frame synchronization circuit, 14... Frame counter, 15... Time slot counter, 16... Decode circuit, 18... Time slot conversion memory for separation, 19... Comparison circuit, 20... Gate circuit, 21... Arithmetic circuit, 91...
Multiplexing flag memory, 92...Time slot switching memory, 93...Multiplexing time slot memory,
94...Time slot interval memory.

Claims (1)

[Claims] 1 a multiplexing circuit that multiplexes input data signals;
A serial-to-parallel conversion circuit that converts a serial signal obtained from the output of this circuit into a parallel signal, a first buffer memory that receives the output of this circuit as an input, a second buffer memory that receives the output of this buffer memory as an input, A buffer memory for parallel-to-serial conversion to which signals read from the buffer memory are led, a separation circuit that separates the output of this buffer memory, and the number of the output terminal that is a predetermined conversion destination for each input terminal to perform time slot conversion. In the time slot exchange method, the time slot conversion memory includes a multiplex flag memory, a time slot exchange memory, a multiplex time slot memory, a time slot interval memory, and a time slot conversion for separation. a memory, and adds either the output of the time slot switching memory or the output of the separation time slot conversion memory as an address of the second buffer memory according to the output of the multiplexing flag memory, and When the time slot numbers output from the multiplexed time slot memory and the time slot counter match, the multiplexed time slots are exchanged, and the multiplexed time slot memory is calculated and updated according to the time slot interval memory, and the multiplexed signal is updated. For separation from the time slot exchange memory, a pseudo address is stored in the time slot exchange memory, and the output of the separation time slot memory corresponding to the address and the time slot number is used as the address of the second buffer memory to create the separation time slot. In order to perform lot swapping and change time slots for each time slot, the time slot interval memory is set to ``1'', and the multiplexed time slot memory is set to the initial state ``1'' to perform multiplexed time slot swapping. A time slot replacement method characterized by the following.