JPS6336415B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic control device for an internal combustion engine, and in particular, to a control device that electronically and comprehensively controls an internal combustion engine (hereinafter referred to as the engine), it is possible to accurately measure even when the input interval of measurement detection signals is very wide. This invention relates to a clock signal supply means for the clock signal. As the demand for automobiles as a means of mass transportation increases, various social problems are occurring. The main ones are air pollution and petroleum energy consumption. In recent years, efforts have been focused on measures against exhaust gas. However, this measure reduces the overall efficiency of the engine. Efforts have been made to incorporate electronic control and improve control accuracy in order to suppress the decline in engine operating efficiency and further improve exhaust gas countermeasures. For example, electronically controlled fuel injection devices and ignition timing control devices have been announced, and more recently, ignition timing control devices using microcomputers have been announced. The trend in conventional control systems has been to replace each mechanical control with an electrical control. Therefore, electronic control devices were created for each individual controlled object. In order to take measures against exhaust gas and operate the engine efficiently, it is necessary to comprehensively control the engine. As mentioned above, if each engine control is made independent and each control circuit created for each independent control object is brought together, there is little organic interaction between each control object, making fine-grained control difficult. It was hot. Another drawback was that the circuit was unnecessarily complicated. In addition, the circuit for detecting the irregularly input sensor output, such as an angle sensor, has become complicated. Furthermore, when controlling such a complicated engine electronically and comprehensively based on digital calculation processing, it is desirable to monitor the engine load condition in synchronization with engine rotation in order to improve control accuracy. , a method has been proposed. Conventionally, when measuring vehicle speed, for example, a certain measurement time was obtained by counting measurement stage signals, and the number of pulses inputted in proportion to the vehicle speed was counted during that time. However, with this method, the number of input pulses is small, especially when the vehicle speed is very slow, so there is a problem that the measurement error becomes large. In order to solve this problem, Japanese Patent Laid-Open No. 55-472 and others have been proposed, but the circuit configuration of the counter becomes complicated, leading to an increase in circuit scale, which causes an increase in cost and a decrease in reliability. SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic control device for an internal combustion engine that has a simple circuit configuration and is capable of measuring measurement detection signals with wide input intervals with high precision. In order to achieve the above object, the present invention includes: an arithmetic processing unit that performs arithmetic processing; a storage element that stores a control program and fixed data; a readable and writable storage element that stores data associated with the arithmetic processing; An internal combustion engine control device comprising an input/output circuit that holds input data based on a measurement detection signal and output data obtained by the arithmetic processing, and has a register group that counts measurement stage signals and determines a measurement time. The input/output circuit calculates the logical product of the measurement stage signal, which determines a certain period of time for counting the measurement detection signals, and the interval interrupt signal to the arithmetic processing unit, and counts measurement detection signals with wide input intervals. AND increase the pulse interval of the measurement stage signal to
The present invention proposes an electronic control device for an internal combustion engine, characterized in that a circuit is provided in front of a circuit portion that counts the measurement stage signal. In the present invention, we focus on the induval interrupt signal, which has a wider pulse interval than the measurement stage signal, and increase the pulse interval of the measurement stage signal by calculating the AND of this signal and the measurement stage signal.
The count-up pace of the counter, which determines the measurement time by counting a fixed number of measurement stage signals, can be slowed down, so even if the measurement detection signal has a wide input interval, a relatively large number of pulses can be captured, increasing measurement accuracy. It turns out. Hereinafter, the present invention will be explained in detail based on embodiments shown in the drawings. FIG. 1 shows a control device for the entire engine system. In the figure, intake air passes through an air cleaner 2, a throttle chamber 4, an intake pipe 6, and is supplied to a cylinder 8. The gas burned in the cylinder 8 passes through the exhaust pipe 10 from the cylinder 8 and is discharged into the atmosphere. The throttle chamber 4 is provided with an injector 12 for injecting fuel, and the fuel injected from the injector 12 is atomized within the air passage of the throttle chamber 4 and mixed with intake air. A mixture is formed, and this mixture is supplied to the combustion chamber of the cylinder 8 through the intake pipe 6 when the intake valve 20 is opened. A throttle valve 14 is located near the outlet of the injector 12.
16 are provided. The throttle valve 14 is configured to mechanically interlock with the accelerator pedal and is driven by the driver. On the other hand, the throttle valve 16 is arranged so as to be driven by the diaphragm 18, and is fully closed when the air flow rate is small.As the air flow rate increases, the negative pressure on the diaphragm 18 increases, so that the throttle valve 16 It begins to open and suppresses the increase in inhalation resistance. An air passage 22 is provided upstream of the throttle valves 14 and 16 of the throttle chamber 4.
2 is an electric heating element 2 that constitutes an air flow rate detector.
4 is arranged, and a periodic electric signal that changes according to the air flow rate determined from the relationship between the air flow rate and the amount of heat transfer of the heating element 24 is extracted. Since the heating element 24 is provided within the air passage 22, it is protected from high-temperature gas generated when the cylinder 8 backfires, and is also protected from being contaminated by dust in the intake air. The outlet of the air passage 22 is opened near the narrowest part of the bench lily, and the inlet thereof is opened on the upstream side of the bench lily. The fuel supplied to the injector 12 is supplied from a fuel tanker 30 to a fuel pressure regulator 38 via a fuel pump 32, a fuel damper 34, and a filter 36. On the other hand, pressurized fuel is supplied from the fuel pressure regulator 38 to the injector 12 via a pipe 40.
From the fuel pressure regulator 38 to the fuel tank 3 so that the difference between the pressure in the intake pipe 6 where fuel is injected from the fuel tank 3 and the fuel pressure to the injector 12 is always constant.
Fuel is returned to zero via a return pipe 42. The air-fuel mixture taken in from the intake valve 20 is transferred to the piston 5.
0 and is combusted by the spark from the spark plug 52. This combustion is converted into kinetic energy. The cylinder 8 is cooled by cooling water 54, and the temperature of this cooling water is measured by a water temperature sensor 56, and this measured value is used as the engine temperature. A high voltage is supplied to the spark plug 52 from an ignition coil 58 in accordance with the ignition timing. Furthermore, a crank angle sensor (not shown) is provided on the crankshaft, which outputs a reference angle signal and an angle signal at every reference crank angle and every fixed angle (for example, 0.5 degrees) according to the rotation of the engine. The output 60 of the crank angle sensor, the output 56A of the water temperature sensor 56, and the electrical signal 24A from the heating element 24 are input to a control circuit 70 consisting of a microcomputer, etc., and are processed by the control circuit 70, and the output of this control circuit 70 is The injector 12 and the ignition coil 58 are driven by the injector 12 and the ignition coil 58. The operation of the engine described above will be explained with reference to FIG. 2. A in FIG. 2 shows the injection timing of fuel from an injector in a four-cylinder engine. The horizontal axis is the rotation angle of the engine crankshaft, and hatching indicates the intake stroke of each cylinder. As is clear from the figure, there is an intake stroke for every 180 degrees of the crank angle, with cylinder 1 between 0 degrees and 180 degrees, cylinder 3 between 180 degrees and 360 degrees, and cylinder 3 between 180 degrees and 360 degrees.
The range between 540 degrees and 540 degrees is the fourth cylinder, and the range between 540 degrees and 720 degrees is the second cylinder. As shown in FIG. 2B, a reference angle signal is generated every 180 degrees of the crank angle, the injector 12 is opened based on this signal, and the calculation is processed by the control circuit 70 based on the already measured data. Based on the result, the opening time of the injector 12 is determined. The fuel injection time, which is the valve opening time of the injector 12, is shown in C in FIG. Next, the control circuit 70 will be explained based on FIG. The input signals of the control circuit 70 can be roughly divided into three types.
Can be classified into types. That is, first, there are analog inputs sent from the output 24A of the heating element 24 that detects the amount of intake air, the output 56A of the sensor 56 that detects engine cooling water, and the like. These analog inputs are multiplexer (hereinafter referred to as MPX) 1
00, the output of each sensor is selected in a time-sharing manner, and the output is input to an analog-digital converter (ADC).
) 102, and is converted into a digital value by this ADC 102. The second information is input as an on/off signal, and this is, for example, a signal θTH indicating the fully closed state of the throttle valve.The signal 104A sent from the switch 104 that operates in conjunction with the throttle valve be. This signal can be handled as a 1-bit digital signal. Furthermore, the third possible input signal is a signal that is input as a pulse example, such as a reference angle signal (hereinafter referred to as PR) or an angle signal (hereinafter referred to as PC), and these signals are input by the crank angle sensor 106. It will be sent to you. PR is for 4 cylinders,
Output for every 180 degrees of crank angle, 120 for 6 cylinders
It is output every 90 degrees in the case of 8 cylinders. For example, the PC is output every 0.5 degrees of the crank angle. The CPU 108 is a central processing unit that performs digital arithmetic processing, and the ROM1
10 is a storage element for storing control programs and fixed data, and RAM 112 is a readable and writable storage element. Input/output interface circuit 114 (hereinafter referred to as input/output circuit 11)
4) receives input signals from the ADC 102 and sensors 104, 106, and sends the input signals to the CPU 108.
send a signal to Further, the signal from the CPU 108 is sent to the injector 12 and the ignition coil 58 as signals INJ and IGN. Note that voltage is applied from the power supply terminal 116 to each circuit and element constituting the control circuit 70, but their description is omitted in the drawing. Furthermore, the injector 12 and the ignition coil 58 are each provided with an electromagnetic coil for driving the valve and a primary coil for accumulating electromagnetic energy, and one end of these coils is connected to the power supply terminal 1.
16, and the other end is connected to the input/output circuit 114, so that the current flowing into the injector 12 and the ignition coil 58 is controlled. In addition, in Figure 3,
162 is a data bus, 164 is an address bus, 1
66 is a control bus. FIG. 4 shows a specific circuit of the input/output circuit 114 in FIG. 3. In the figure, a register group 470 is a reference register group and holds data processed by the CPU 108 or data indicating a predetermined constant value. This data is sent from CPU 108 via data bus 162. The register to be held is specified via the address bus 164, and the above data is input to the specified register and held. This register group 470 is made up of registers 402-428. The register group 472 is a momentary register group and holds the instantaneous state of the engine and the like. Instantaneous register group 472, latch circuit 476, and incrementer 4
78 performs a so-called counter function. The output register group 474 includes, for example, a register 430 that holds the rotational speed of the engine and a register 432 that holds the vehicle speed. These values are obtained by reading the values of instantaneous registers when certain conditions are met. Output register group 47
The data held in CPU 162 is sent to a related register by a signal sent from the CPU 108 via the address bus, and sent from this register to the CPU 108 via the data bus 162. Comparator 480 receives reference data from a selected register of the group of reference registers and instantaneous data from a selected register of the group of instantaneous registers at inputs 482 and 484, respectively, and performs a comparison operation. The comparison result is output from the output shaft 486. The output terminal is set in a predetermined register in the first comparison output register group 502 which functions as a comparison result holding circuit. Furthermore, it is then set in a predetermined register of the second comparison output register group 504. Reference register group 470, instantaneous register group 47
2. Read and write operations of the output register group 474, incrementer 478 and comparator 480
The operations of setting the output to the first comparison output register 502 and the second comparison output register 504 are processed within a certain predetermined time. Further, various processes are performed in a time-sharing manner according to the stage order instructed by the stage counter 572. For each stage, a predetermined register in each of the reference register group 470, instantaneous register group 472, first and second comparison result register groups, and, if necessary, a predetermined register in the output register group 474 is selected. . Also, incrementer 478 and comparator 480 are used in common. FIG. 5 is a diagram for explaining the timing of FIG. 4. A clock signal E is supplied from the CPU 108 to the input/output circuit 114. This signal is shown in A. From this clock signal E, a pulse generator circuit 574 generates two non-overlapping clock signals φ1 and φ2. This signal is shown in B and C.
The circuit shown in FIG. 4 operates according to these clock signals φ1 and φ2. FIG. 5D shows a stage signal, which is switched at the rise of the clock signal φ2, and the processing of each stage is performed in synchronization with φ2. In Figure 5
THROUGH indicates that the latch circuit or register circuit is enabled, and indicates that the output of these circuits depends on the input. Also
LATCH indicates that these circuits hold certain data and the output of this circuit does not depend on the input. The stage signal shown in D serves as a readout signal for the reference register 470 and instantaneous register 472, and reads out the contents from a selected predetermined register. E and F indicate the operation of reference register 470 and instantaneous register 472, respectively. This operation is performed in synchronization with the clock φ. The operation of latch circuit 476 is shown in FIG. This circuit enters the THROUGH state when φ2 is at a high level, writes data in a specific register read from the instantaneous register group 472, and clocks φ2.
When 2 becomes low level, it becomes LATCH state. In this way, the data of a predetermined register in the instantaneous register group corresponding to that stage is held. The data held in the latch circuit 476 is
Incrementer 478 not synchronized to clock signal
modified based on external conditions. Here, the incrementer 478 has the following functions based on the signal from the incrementer controller 490. The first function is an increment function that increases the value indicated by the input data by one. Second
The function is a non-increment function, which allows the input to pass through without increasing it. The third function is a reset function, which changes all inputs to data indicating a value of 0. Looking at the data flow of the instantaneous registers, one register in the instantaneous register group 472 is selected by the stage counter 572, and its held data is input to the comparator 480 via the latch circuit 476 and the incrementer 478. Additionally, a closed loop is created from the output of incrementer 478 back to the originally selected register. Therefore, when the incrementer functions to increase data by one, this closed loop functions as a counter. However, in this closed loop, if a situation occurs in which the data of the instantaneous register group is output from a specific selected register while the data is looped around and input, malfunction occurs. Therefore, a latch circuit 476 is provided to cut off the data. The latch circuit 476 enters the THROUGH state in synchronization with clock φ2, while the THROUGH state in which the input is written to the instantaneous register is synchronized with clock φ1. Therefore, data is cut between clocks φ2 and φ1. In other words, even if the value of a specific register in the register 472 is changed, the latch circuit 47
The output of 6 remains unchanged. Comparator 480, like incrementer 478, also operates out of synchronization with the clock signal. The input of the comparator 480 is transmitted through the incrementer of the latch circuit for the data held in one reference register selected from the reference register group 470 and the data held in one register selected from the instantaneous register group. received data. The result of this data comparison is synchronized with clock signal φ1.
It is set to the first comparison result register group 502 which enters the THROUGH state. Furthermore, this data is set in the second comparison result register group 504 which enters the THROUGH state at clock φ2. The output of this register 504 becomes a signal for controlling each function of the incrementer, and a drive signal for the fuel injector, ignition coil, exhaust gas recirculation device, etc. Also, based on this signal, the measurement results of the engine rotational speed and vehicle speed at each stage are written from the instantaneous register group to the output register group 474.
Now, for example, when writing the engine rotation speed, the second signal indicating that a certain period of time has elapsed is
It is held in the comparison result register RPMWBF552,
At the RPM stage in Table 1, which will be described later, data held in the instantaneous register 462 is input to the register 430 of the output register group based on the output of this register 552. At this time, the second comparison result register
If the signal indicating that a certain period of time has elapsed is not held in the RPMWBF 552, the operation of inputting the data held in the register 462 to the register 430 is not performed even in the RPM stage. On the other hand, based on the signal held in the second comparison result register VSPWBF 556, data in the instantaneous register 468 is inputted to the output register 432 as data representing the vehicle speed at the timing of the stage VSP. Writing of data representing the engine rotational speed RPM and vehicle speed VSP to the output register group 474 is performed as follows. In Figure 5,
The stage signal STG is RPM or VSP, and the data in the instantaneous register 462 or 468 is at the high level of the clock φ2, and the latch circuit 476 is activated.
It becomes THROUGH state and is written, and the clock φ
2 becomes low level, the above data becomes
LATCHed. The data held in this way is stored in the register RPMWBF552 or
Based on the signal from the VSPWBF 556, the output register group 474 enters the THROUGH state as shown in FIG. 5K in synchronization with the high level of the clock φ1, so that data is written there and LATCHed at the low level of the clock φ1. When the CPU 114 reads data held in the output register group 474, the CPU 114 specifies the register via the address bus 164, and the data is fetched in synchronization with the clock signal E shown in FIG. 5A. Next, FIG. 6 shows a generation circuit for the stage signal STG. A stage counter SC570 is counted up by the signal φ1 from the pulse generator circuit 574, and the outputs C0 to C6 of the stage counter SC570 and the output of the T register in FIG. 4 are input to the stage decoder SDC. The stage decoder SDC writes signals 01 to 017 as outputs to the stage latch circuit STGL in synchronization with the clock φ2. The stage latch STGL reset input has a fourth
When the ^20- bit signal GO of the MODE register shown in the figure is input and the ^20- bit GO signal of the MODE register becomes low level, all outputs of STGL become low level and all processing operations are stopped. On the other hand, when the GO signal becomes high level, the stage signal STG is outputted again in a fixed order, and processing is performed based on it. The above stage decoder SDC is READ.ONLY.
This can be easily achieved by using MEMORY etc. Table 1 shows the detailed contents of stages 00 to 7F of the stage signal STG, which is the output of the stage latch STGL.

【table】

[Table] First, the general reset signal GR is input to the reset terminal R of the stage counter SC570 shown in FIG. 6, and thereby the counter outputs C0 to C6 all become 0. This general reset signal is sent from the CPU when this control circuit is activated. When the clock signal φ2 is input in this state, the EGRP stage signal STG is output at the rising edge of φ2. EGRP processing is performed based on this stage signal. Next, the stage counter SC570 counts up by one at clock φ1, and ANGL of the next stage signal STG is output at clock φ2. ANGL processing is performed based on this stage signal ANGLSTG. Next is the stage signal
CYLSTG is output and CYL is processed, and then stage signal ADV is output and ADV is processed. In this way the stage counter
When the SC 570 continues counting up in synchronization with φ1, a stage signal STG is output in synchronization with φ2, and processing is performed in accordance with this signal. When C0 to C6 of stage counter SC570 all become 1, stage signal INJSTG is output.
The INJ process is performed and all the processes in Table 1 are completed. With the next clock signal φ1, all C0 to C6 of the stage counter SC570 become 0, and with the clock signal φ2, the stage signal EGRPSTG is output, and STG processing is performed. In this way, the processing in Table 1 is repeated. Table 2 shows the processing contents of each stage shown in Table 1.

【table】

[Table] Output from the stage latch circuit STGL in Figure 6
The STG0 and STG7 signals are circuits for synchronizing the input input from the outside with the internal clock signal of the input/output circuit 114.
Output when , stage counter of output STG7
It is output when C0 to C2 of SC570 are all 1. FIG. 7 shows details of register groups 470 and 472 shown in FIG. 4. To explain the input of data to register group 470, data from CPU 108 is input to latch circuit 802 via data bus 162. At the same time as this input, the CPU 108 sends a read/write signal R/
W, signal VMA is input to AND gates 806 and 808. Furthermore, a register within the input/output circuit 114 is selected by an address signal sent from the address bus 164. In this method, as is already known, the data on the address bus 164 is changed by a decoder into a signal corresponding to each register, and this is carried out by the address decoder 804 in FIG. 4. The output of this decoder 804 is input to each register 402 to 428, but the input signal wiring is omitted in the figure. Then, the read/write signal R/W, the signal VMA, and the address bit A1 indicating that it is the input/output circuit 114.
5, the gate 806 outputs the select chip write signal CCW, and the gate 808 outputs the select chip read signal CCR. When writing data from the CPU 108 to a predetermined register, a select chip write signal CCW is output, and the signal CCW is applied to each register 402 to 4.
It is input to the input terminal of 28. In this case, since the select chip read signal CCR is not output, the condition of the gate 810 is not satisfied, and the three-state buffer 812 is closed. In this state, data sent via the data bus 162 is held in the latch circuit WDL802 by the timer φ2. Latch circuit 802
The data held in the write bus driver
The signal is sent to each register of the reference register group 470 via the WBD, and is input to and stored in the register selected by the address decoder at timing φ1. Register 40 of this reference register group 470
8,410,412,414,416,426,
428 is a 10-bit register, while CPU
Since the data bus 108 and the data bus 162 are 8 bits, different addresses are assigned to the lower 8 bits and the upper 2 bits. Therefore, data is sent to these 10-bit registers twice. On the other hand, reading data from each register of the reference register group 470 is an operation completely opposite to the above-mentioned write operation. That is, the control bus 16
Chip select gate with control signal 6
CSR 808 is opened, and as a result, buffer 812 is opened with timing signal E via gate 810, and in this state, a read operation is performed.
That is, since a predetermined register is selected by the address signal on the address bus 164, the data stored in the predetermined register is transferred to the data bus 162 via the three-state buffer 812.
and transmitted to the CPU 108. Next, the operation in which the reference register and instantaneous register are selected by the stage signal will be explained. A stage signal is input to each register of register groups 470 and 472, respectively. This stage signal selects the register corresponding to each stage. Among the registers of the reference register group 470, registers 412, 414, and 416 are associated with the comparison result holding register group 504.
When the outputs INJBF, ADVBF, and DWLBF are output, the stage signals are sent to the registers 412, 414,
416 and these registers are not selected. Instead of this, INJBF, ADVBF,
When the DWLBF signal is output, stage INJ
A zero register 402 is selected in each of ADV and DWL. On the other hand, two stage signals EGRP and EGRD, NIDLP and NIDLD are input to registers 456 and 458 of instantaneous register group 472, respectively. This is because by selecting in these two stages, the registers are selected corresponding to the two registers 418 and 420 and 422 and 424 of the reference register group, respectively. FIG. 8 shows the first comparison output register 5 in FIG.
02, a detailed circuit of the second comparison output register 504 is shown. In the figure, the output of comparator 480 is divided into a signal indicating an "equal" condition and a signal indicating "greater than", and NAND gate 830,
It is input to NOR gate 832. NOR gate 8
The output of 32 indicates the "greater than or equal" condition.
However, the selection condition of the zero register 402 shown in FIG. 7 and the comparator 4 shown in FIG.
Since the "equal" condition of 80 is input, when the zero register 402 is selected,
The signal with the "equal" condition is cut off by the NAND gate. As a result, the only condition for the output of NOR gate 830 is "large". Each register of the first comparison output register group needs to be selected in synchronization with each register of the reference register group and each register of the instantaneous register group, and in order to achieve synchronization, the set timing of the first comparison output register group is selected. The clock φ2 and the corresponding stage signals are input as input signals. Therefore, at each stage, the comparison result of that stage is the first
It is latched into the corresponding register of the comparison output register group at timing φ1. Note that φ2 is inputted as the set timing for the second comparison output register, and the comparison result is set in the second comparison output register at the next timing φ2 following the above-mentioned φ1. As a result, BF outputs are output from the second comparison output register group 504, respectively. Note that registers 512, 528, 552, 55
6, 516, 520 have waveform shaping circuits 840, 842, 844, 846, 84 at their outputs, respectively.
8,850 is connected, and the pulse ANGLD has a duty only while the next stage zero signal comes after the second comparison output register is set.
ADVD, RPMWD, VSPWD, INTVD,
ENSTD occurs respectively. In order to detect the pulse train signals input from the sensor to the input/output circuit 114, it is necessary to synchronize these pulse train signals with the operation of the input/output circuit. The reason for this is that the period and pulse width of these pulse train signals change with changes in engine rotational speed, vehicle speed, etc., and the width of the change is large. This is because the pulse train is much shorter than the stage period for corresponding or detecting it, and disappears before the stage signal is generated, making it difficult to accurately count the pulse train. FIG. 9 shows a synchronization circuit that synchronizes the external pulse train signal with the stage signal in the input/output circuit, and FIG. 10 shows a timing chart for explaining its operation. As external input pulses such as sensor output, for example, reference angle signal PR, angle signal PC, and vehicle speed signal PS generated in synchronization with wheel rotation are shown in Figure 6.
The latch circuit 600 in FIG. 9,
They are latched at 602 and 604, respectively. In Fig. 10, A is the clock signal φ2, B is the clock signal φ1, and C and D are the stage signal STG7.
STG0. This stage signal is generated in synchronization with φ2, as explained in FIG. The signal shown at E is an output pulse from the crank angle sensor or vehicle speed sensor and indicates the reference angle signal PR, angle signal PC, or vehicle speed signal PS.The generation timing, pulse duty, and period of this signal are irregular, and the stage signal It is input unrelated to. Assuming that signals as shown in FIG. 10E are input to latch circuits 600, 602, and 604, they are each latched by stage signal STG0 (pulse S1 in the figure). Therefore, as shown in FIG. 10F, it becomes high level at time S2. Furthermore, for the stage signal STG0 indicated by S3, the input signals PR, PC,
PS is high level so latch circuit 600,60
The high level is latched at 2 and 604, respectively. However, in the stage signal STG0 shown in S4, the input signals PR, PC, and PS are at low level, so the low level is latched. Therefore, the outputs A1, A2, of the latch circuits 600, 602, 604,
A3 becomes as shown in F. latch circuit 606,
Since the outputs A1, A2, and A3 are latched at S5 of the stage signal STG7, the outputs 608 and 610 rise from the time indicated by S6. Also, since the high level is latched at S7 of the stage signal STG7, the high level continues. Therefore, the latch circuit 60
6,608,610 output signals B1, B2, B3
are as shown in G. The signal A1 and signal B1 sent via the inverter 605 are input to the NOR circuit 612, and a synchronized reference signal PRS is generated as shown at H. This synchronized reference signal PRS
captures the rising edge of the reference angle signal PR,
This is the pulse width from the rise of stage signal STG0 to the rise of STG7. The EXCLUSIVELYOR circuits 614 and 616 receive signals A2 and B2 and signals A3 and B3, respectively, and the condition is that the signal PC or PS changes from L level to H level, and furthermore, at the timing of STG0, signal S8 shown in I is input. condition occurs and the signal PC or PS changes from H to L.
Furthermore, a signal S9 is generated at the timing of the rise of STG0. The duty of signals S8 and S9 is H
is the same as the duty shown in , and the stage signal
Determined by STG0 and STG7. In the above explanation, it is assumed that the signals PR, PC, and PS are input at the same time with the same duty, but in reality, these signals are not input at the same time and their duties are also different. Furthermore, even when looking at the same signal itself, its period and duty differ each time. However, due to FIG. 9 and the synchronization circuit, the pulse has a constant width. This pulse width is the stage signal STG
It is determined by the time difference between STG 0 and STG7. Therefore, latch circuits 600, 602, 604 and 606, 608, 6
By changing the stage signal applied to 10, the pulse width can be adjusted and changed. This pulse width is determined in relation to the timing of the stages in Table 1. In other words, as shown in Table 1, the ANGL stage is stage counter C0~
C2, C3 to C6 are allocated in the state of (1, 0), and further (1, 1), (1, 2), (1, 3)...
...and are assigned to each 8th stage. Since each stage is set to 1 microsecond, an ANGL stage is assigned once every 8 microseconds. Since the ANGL stage needs to detect the angle signal PC and control the incrementer, when the output PC of the angle sensor is applied to the synchronization circuit shown in Figure 9, the synchronization circuit will always hit the ANGL stage. Create a synchronization pulse like this and based on this synchronization pulse PCS
Control the incrementer controller in the ANGL stage. This synchronized angle signal PCS is also detected in stages ADV and RPM. This stage ADV
The RPM is assigned to the stage counters C0 to C2 being in the state of 3 and 6, respectively, and the values of C3 to C6 counting up by one. The assigned stage rotates in a cycle of 8 microseconds. The STG0 signal in Figure 9 is the C of the stage counter.
Output when the value of 0 to C2 is 0, while STG7
is output when C0 to C2 have a value of 7. This output is produced independently of C3-C6. Therefore, the first
As can be seen from Figure 0, the synchronized angle signal PCS always has a pulse width from the value of 0 to the value of 6 for the stage counter outputs C0 to C2, and this pulse is detected by the stages ANGL, ADV, and RPM, and the incrementer Control the controller. As above, the CYL stage that detects the synchronized reference signal PRS outputs the stage counter output C.
Since it is always assigned when the value of 0 to C2 is 2, the reference angle signal is sent from the angle sensor 98.
When PR is input, stage counter C0~
It is necessary that the synchronization reference signal PRS be output when C2 is 2. The circuit in Figure 9 is STG0
Since the pulse width between STG and STG7 is obtained, this information is fully satisfied. Next, the VSP stage for detecting the wheel speed is assigned when the stage counter outputs C0 to C2 always have a value of 5. Therefore, it is sufficient that the synchronized PSS signal is output when the value of C0 to C2 is 5. The circuit shown in FIG. 9 satisfies this condition because the values of C0 to C2 range from 0 to 6. 9th
In the figure, instead of the STG0 signal, create a signal STG4 that always appears when the value of C0 to C2 is 4, use this signal, and use this signal instead of the STG7 signal.
A signal STG6 that is always output when the value of 2 is the value of 6 may be used. In this case, when the signal PS is input, the synchronization signal PSS is the output C of the stage counter.
It will always be output when the values of 0 to C2 are 4 and 5. The stage cycle will now be explained.
In Table 1, stage counter outputs C0 to C6
128 types of stage signals with values from 0 to 127 are created, and when all of these signals have been generated, the large cycle is completed and a new large cycle begins again. This large cycle is further composed of 16 small cycles, and this small cycle is composed of 8 types of stage signals. This small cycle corresponds to the values of stage counter outputs C0 to C2 of 0 to 7, respectively, and is completed in 8 microseconds. The pulse outputs PR, PC, and PS from the sensor are reliably synchronized, and the synchronized pulses PRS, PCS,
In order to reliably generate PSS, it is necessary that the output from the sensor has a pulse width longer than this short cycle. For example, the duty of an angle sensor for a PC becomes narrower as the engine rotates faster. For example, at 9000 revolutions per minute, the time is approximately 9 microseconds. Therefore, in order to achieve sufficient synchronization with respect to 9000 revolutions per minute, it is necessary to make this small cycle shorter than this, and in this embodiment it is 8 microseconds. FIG. 11 shows a detailed circuit of incrementer 478. Input terminals A0 to A9 each receive 10-bit data from a register of the instantaneous register group selected in accordance with each stage signal. First, the A0 bit will be explained. A0 bit and count signal are exclusive OR850
is input to. Here, if the A0 bit is 0 (zero) and the count signal is 0 (L), it remains 0 (zero).
is output. Conversely, if the A0 bit is 1, 1 is output as is. In other words, the count signal is 0
If it is (L), the A0 bit signal is output as is. On the other hand, if the count signal is 1 (H), the A0 bit signal is inverted, and if A0 is 1, 0 (zero) is also inverted.
If A0 is 0 (zero), 1 is output. As a result, when looking at the A0 bit, it is counted by 1 according to the count signal. However, if the A0 bit is 1 and the count signal is 1, a carrier signal is sent to the processing gate 854 of the upper bit A1. The NOR gate 852 is a circuit that detects a carrier signal, and only when there is a carrier signal, the A1 bit is inverted and outputted as B1. If there is no carrier signal, the A1 signal becomes the B1 output. Gates 856, 860, 864,
The presence or absence of each carrier signal is detected at 868, 872, 876, 886, and 884,
Each input bit A2 to A9
OR, 858, 862, 866, 870, 87
4,878,882,886. If there is a carrier signal, these signals are inverted and output from B0 to
This becomes the output of B9. In this way, when the count signal is present, the input bits A0 to A9 count up by 1 and become output signals B0 to B9. AND gates 890-908 are circuits that perform a reset function, and when a RESET signal is input, outputs B0-B9 become zero regardless of the outputs of exclusive OR circuits 850-886. The count signal and RESET signal controlling the incrementer of FIG. 11 are produced by the incrementer controller FIG. 12. 12A and 12B are detailed views of the incrementer controller 490 of FIG. 4. 12th
Figure A shows a circuit that outputs a count signal (Count) and reset (Reset) to control the incrementer 478, and Figure 12B shows a move signal output circuit that transfers data to output register groups 430 and 432. be. As mentioned above, this incrementer 478 has three functions; the first function is to increase the input data by a value of 1, the second function is to reset the input data, and the third function is to increase the input data by a value of 1. The function is to output input data as is. The increment function is performed by the count signal, and the reset function is performed by the RESET signal.
When the count signal is high level, it is an increment function, when it is low level, it is a non-increment function, and when the RESET signal is high level, it is a reset function, and the RESET signal has priority over the count signal. The conditions may be selected based on the stage signals commanded by each process. The conditions include synchronized external input and the register group 504 of the second comparison result.
This is the output of Further, the conditions for transferring and writing data to the output register 474 are also similar to the conditions for the incrementer. Next, measurement of wheel speed will be explained. First, use your calculator to determine a certain amount of time called the window time. Measurement is performed by counting the number of pulses input each time the wheel rotates within this fixed period of time. For this reason, wheel speed requires a function to count pulses from sensors attached to the wheels and a function to determine whether a certain period of time has elapsed. These two functions cannot be performed by a single stage signal, so the stage signals are separated. That is, the stage for checking whether a certain period of time has elapsed is the VSPW stage "0B" in Table 1. This VSPW has a very long time width, so the VSPW stage pulse only comes in occasionally. The operation for determining whether or not this certain period of time has elapsed is as follows. That is, at the VSPW stage, the registers 428, 428 related to the VSPW registers shown in FIG.
464, 554, and 556 are connected. Then,
A window time (this is the time to be measured that is set by the computer and can be changed in various ways) is set in the register 428 and input to the comparator circuit 480. Also, register 464
The value of + is passed through the latch circuit 476 to
1'' and input to the comparison circuit 480 for comparison. This comparison circuit 480 constantly checks to see if they are equal to the set value from the computer, and if they are equal at a certain VSPW, it sets "1" in register 554 and "1" in register 556. do. In this case, when the next stage signal
The AND gate condition can be taken. In this case, if a match occurs during the VSPW stage, "0" is output in the incrementer 478 and the counter is reset. This VSPW
The value of is determined by the time interval set by the programmer, and the pulse is not long. Its length is between "0B" and "0C" in Table 1. The wheel speed during this period is measured by determining whether a pulse is received from the wheel speed, that is, whether a pulse called PSS is received from the sensor and processed by the circuit shown in FIG. 9. this
The PSS pulse is an internally synchronized crank angle sensor pulse. This sensor pulse is a pulse that is output once between "0-7" in Table 1, and does not have a length longer than "0-7" in Table 1. Even if the pulse is shorter than this, this thinning is extended. This is because the VSP stage signal always comes once between "0 to 7", and if it is delayed for a long time, it will be counted only once. At the VSP stage, only the count up is done, and register 468 is
The circuit passes from the latch circuit 476 to the incrementer 478 which adds "+1", but whether the "+1" or "+0" is determined depends on whether or not the PSS in FIG. If the wheel is running slowly, ``+0'' will be selected forever, and if the wheel is moving slowly, ``+1'' will be selected from time to time). Then, at the final time when the vehicle speed is measured, the window VSPWD pulse is output, a reset is applied, and the value returns to "0".
It is latched before this reset is activated, and new data is written into the register 432 at regular intervals. In order to accurately measure even when the wheel speed is very slow, it is necessary to increase the measurement time, so the timing of an interval interrupt signal, which is a computer interrupt signal, is used as the clock that determines the window.
That is, in FIG. 8, the clock period can be substantially reduced by receiving the VSPWSTG signal and the INTVBF signal from register 516 in an AND circuit and calculating the logical product of both signals. The effect will be explained while comparing FIG. 18 and FIG. 19. If there is no AND circuit, the 18th
As shown in the figure, the VSPWSTG signal becomes the VSPWD signal, so the VSPW counter for specifying the measurement time is the VSPWD signal with the same period as the VSPWSTG signal.
Count the signals. In contrast, AND
If a circuit is provided, as shown in Figure 19,
The VSPWD signal is output only when the VSPWSTG signal and the INTVD signal match, and the VSPW counter has a pulse interval that is much wider than the VSPWSTG signal.
The VSPWD signal will be counted slowly. Therefore, it takes a long time for the VSPW counter to count up to a predetermined value, and even a signal with a wide pulse interval, such as a vehicle speed signal, can be taken in a large amount during that long time, improving accuracy. Generally, measurement accuracy is proportional to measurement time. By measuring the number of pulses input over a certain period of time, the frequency of that pulse can be determined. If a pulse with a frequency of f (Hz) is input during the measurement time T (sec),
The count value is f×T. At this time, the pulse measurement includes a quantization error of ±1 count, so the error is 1/fT.
have. The smaller T is, the larger 1/fT becomes, which has an adverse effect on control. Furthermore, since the measurement resolution is proportional to the count value, the larger T is, the greater the resolution can be obtained. For example, a signal of about 5Hz
If you count for 1 second, you will get 5 counts, but the quantization error of 1 count corresponds to ±20%. The resolution is also similar. If T is doubled to 2 seconds, the count value will be doubled to 10 counts, and the accuracy will be ±10%. Here, considering that the vehicle speed signal is very slow and f is low, it is important to take a long measurement time. Although this embodiment has been explained using VSPW, the same effect can be obtained by ANDing EGRP and INTVBF using an AND gate when determining the duty of the pulse that determines the EGR pulse period. Can be done. FIG. 13 is a diagram illustrating the process of generating the constant angle signal ANGLD. Synchronized reference signal PRS
register 444, which acts as ANGLCOUNTER, is incremented by the high level of the synchronized angle signal PCS. And from the reference angle signal PR
ANGL that maintains the angle until ANGLD occurs
If it is greater than or equal to the register 406, the ANGL FF 510 of the first register 502 is set to 1.
and also sets the second register 504.
ANGL BF512 is set to 1. this
The rising edge of ANGL BF is shaped by a waveform shaping circuit 840 to generate a signal ANGLD. This signal ANGLD
is one of the STATUS REGISTERs shown in Figure 4.
Sets the bit to 1 and generates an interrupt signal. By changing the value set in the ANGL register 406 in this way, it is possible to change the time from the reference angle signal PR to generation of the interrupt signal. FIG. 14 is a diagram explaining the processing of the fuel injection signal INJ. Since the start of injection is different depending on the number of cylinders, the synchronization reference signal is
PRS is counted and the result is compared with the CYL register 404 which holds a value related to the number of cylinders, and when the result is greater or equal, CYL FF 506 in the first register group 502 is set to 1. , and further the second register group 504.
Set CYLBF508 to 1. This CYLBF
= 1, CYL COUNTER 442 is reset. Also, when CYL BF=1, the INJ TIMER 450 that measures the injection time is reset.
INJD register 4, which is always unconditionally incremented by the time and has the injection time set.
12 and when greater or equal, the first
1 is set in the INJ FF522 of the register group. Also, 1 is set in INJ BF524 of the second register group. When this INJ BF=1,
Incrementing by time is prohibited. This INJ
The reverse output of BF becomes the fuel injection time width, which becomes the valve opening time of the fuel injector. FIG. 15 is a diagram illustrating processing of signals that control ignition. The synchronization reference signal PRS resets the register 452, which acts as an ADV COUNTER, and is incremented by the high level of the synchronization angle signal PCS. Then, the ignition angle from the reference angle signal PR is compared with the ADV register 414 holding the ignition angle, and if the ignition angle is greater than or equal, the ADV FF 526 of the first register 502 is set to 1, and the ignition angle of the second register 504 is set to 1. ADV BF528 is set to 1. ADVD indicating the rising edge of ADV BF causes the DWL COUNTER to start energizing.
454 and is incremented by the synchronization angle signal PC8 being at a high level. Then, it is compared with the DWL register 416 that holds the angle from the previous ignition position to the start of energization, and if it is greater or equal, the DWL FF 530 of the first register 502 is set to 1,
Also, the DWL BF532 of the second register 504
is set to 1. The output of this DWL BF532 becomes the ignition control signal ING1. FIG. 16 is a diagram explaining EGR (NIDL) processing. All of these EGR controls use proportional solenoids, so duty control is performed. There are two registers: an EGRP register 418 that holds the cycle and an EGRD register 420 that holds the on-time.
56. In processing, EGRP
When processing STG, unconditional increment,
Also, EGRP register 418 and EGR TIMER 45
6, and if the data is greater than or equal to EGRP FF5 of the first register group 502.
Set 1 to 34. Additionally, EGRP BF 536 in second register group 504 is set to 1. When processing EGRD STG, unconditional non-increment, or EGR with EGRP BF=1.
TIMER 456 is reset. EGRDFF5
38 is the EGRD register 420 and EGR TIMER
456 and the results are greater than or equal, EGRD BF540 is set to 1.
is set to The inverted output of this EGRD BF540 is the EGR control signal. The operation is similar to NIDL. Figure 17 shows the engine speed RPM (and vehicle speed).
FIG. The measurement method uses a certain measurement time width as RPMW.
It is determined by the TIMER 460 and obtained by counting the synchronized angle pulses PC within that time width. RPMW TIMER460, which measures time width,
is unconditionally incremented and also RPMW
It is reset when BF552=1. RPMW
FF550 is set to 1 because the RPMW register 425 holding the time width and RPMW
This is when the TIMER 460 is compared and the result is greater than or equal. RPM COUNTER462 that counted the PC by RPMWD indicating the rise of RPMW BF552
The contents of are transferred to the RPM register 430 of the output register 474 and written. Also, RPMW BF
When 552=1, RPM COUNTER462
will be reset. VSP STG processing is also similar to RPM. Table 3 shows the functions of each register.

【table】

【table】

【table】

【table】

[Table] Next, a method for setting reference data in the reference register 470 will be explained. Register 402,4
04,410 are set when the device of this embodiment is started up. Once set, these values do not change. Data setting in registers 406 and 408 is then performed by program processing. Data INJD representing the opening time of the fuel injector 66 is input to the register 412. This data INJD is determined, for example, as follows. Air flow meter 14 output signal
QA is taken through multiplexer 122 to analog-to-digital converter 124 . Here, it is converted into digital data and held in a register (not shown). The load data TP is obtained from the data representing the intake air amount and the data held in the register 430 in FIG. 4 through calculation processing or information stored in a map form. In addition, intake temperature sensor 1
6. Digitally convert the outputs of the water temperature sensor and atmospheric pressure sensor, and make corrections based on this data and the engine operating status. Let this correction coefficient be K1. Furthermore, the battery voltage is also digitized, and correction is performed according to this data. This correction factor is TS
shall be. Correction is then performed by the λ sensor 80. Let this correction coefficient be α. In other words, data INJD is expressed as follows. INJD=α(KI・TP+TS) In this way, the valve opening time of the fuel injector is determined. However, the method shown here is just one example, and it is of course possible to define it using other methods. The register 414 contains data representing the ignition timing.
ADV is set. This data ADV is created, for example, as follows. Map-shaped ignition data θIG with the load data TP and rotational speed as factors is held in the ROM 118, and is determined from this map. Furthermore, starting correction, water temperature correction,
Add acceleration correction etc. In this way the data
ADV is created. The register 416 contains data DWL as data for controlling the primary current charging time of the ignition coil.
is set. This data DWL is the above data
It is calculated from the ADV value and the digital value of battery voltage. Data EGRP representing the period of signal EGR and data NIDLP representing the period of signal NIDL are set in registers 418 and 422, respectively. These data are predetermined. Data EGRD representing the energization width of the EGR valve (exhaust gas recirculation device) is set in the register 420. As the energization width increases, the valve opening ratio of the exhaust gas recirculation device increases, and the exhaust gas recirculation rate increases. The data EGRD is, for example, a map state in which the factors are the load data TP and the rotation speed.
18. Furthermore, this data is corrected based on water temperature, etc. Data NIDLD representing the energization width of the air regulator 48 is set in the register 424.
This data is subjected to feedback control such that the rotational speed of the engine in a no-load state becomes a predetermined rotational speed, and is determined as the feedback position. Data RPMW and VSPW representing fixed time periods are set in registers 426 and 428, respectively, when the circuit of this embodiment is activated. In the above explanation, the output of the air flow sensor is used as an input factor to control the fuel injection amount, ignition advance angle, exhaust gas recirculation amount, etc. However, it is possible to use a sensor other than this air flow sensor as a sensor that indicates the state of the intake air. For example, a pressure sensor that detects intake manifold pressure may be used. As explained above, the constant angle signal ANGLD
can be generated without affecting the fuel injection signal INJ, the ignition control signal IGN1, etc. Therefore, according to this embodiment, the vehicle speed can be measured with high accuracy even when the wheel speed is slow. As described above, according to the present invention, even if the input interval of measurement detection signals is wide, it is possible to measure with high accuracy.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the control device for the entire engine system, Fig. 2 is a time chart showing the operation of the engine, Fig. 3 is a block diagram showing the specific configuration of the engine control circuit, and Fig. 4 is Fig. 3. 5 is a block diagram showing details of the input/output interface circuit shown in FIG.
The figure is an explanatory diagram showing the operation of the circuit shown in Figure 4, and Figure 6 shows the operation of the circuit shown in Figure 4.
The figure is a block diagram showing details of the stage counter in the circuit in FIG. 4, FIG. 7 is a block diagram showing a concrete example of the reference register group and instantaneous register group shown in FIG. 4, and FIG. 9 is a circuit diagram showing details of the synchronization circuit, and FIG. 10 is an explanatory diagram showing the operation of the synchronization circuit shown in FIG. 9. , FIG. 11 shows the incrementer 4 shown in FIG.
78, FIG. 12A and 12B are circuit diagrams showing details of the incrementer controller, FIG. 13 is a diagram showing the operation of constant angle signal generation processing, and FIG. 14 is a fuel injection An explanatory diagram showing the operation of signal processing, Fig. 15 is an explanatory diagram showing the operation of ignition timing control, Fig. 16 is an explanatory diagram showing the operation of EGR or NIDL control, and Fig. 17 is an explanatory diagram showing the operation of engine rotation speed RPM or vehicle speed VSP. An explanatory diagram showing the detection operation, Fig. 18, shows the case without the AND circuit of the present invention.
FIG. 19 is a diagram showing the relationship between the VSPWSTG signal and the VSPW count when there is an AND circuit of the present invention. 70...Control circuit, 108...CPU, 110
...ROM, 112...RAM, 114...I/O circuit, 470...Reference register group, 402-4
28...Register.

Claims (1)

[Claims] 1. An arithmetic processing unit that performs arithmetic processing, a storage element that stores a control program and fixed data,
a readable and writable memory element for storing data associated with the arithmetic processing; and a register that counts measurement stage signals and determines measurement time while holding input data based on the measurement detection signal and output data obtained by the arithmetic processing. A control device for an internal combustion engine including an input/output circuit having a group of input/output circuits, wherein the input/output circuit receives the measurement stage signal and an interval interrupt signal to the arithmetic processing unit, which determines a predetermined time for counting the measurement detection signals. The internal combustion engine is characterized in that an AND circuit is provided in front of a circuit section for counting the measurement stage signals, and an AND circuit that widens the pulse interval of the measurement stage signal in order to calculate the logical product of the measurement detection signals with a wide input interval and count the measurement detection signals having a wide input interval. Engine electronic control unit.