JPS6336576B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter device in which coefficients of a transfer function are stored in advance and characteristics can be varied by switching the coefficients.

In recent years, digital filters consisting of multipliers, adders, delay circuits, etc. have been attracting attention instead of analog filters that can be realized using transistors, resistors, capacitors, coils, or operational amplifiers. A major feature of this digital filter is that filters with many characteristics can be easily constructed using the same circuit.

In Figure 1, the transfer function is H(Z)=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 /1+b ₁ Z ^-1 +b ₂ Z
^-2 ...A low-pass filter (or high-pass filter) with variable cutoff frequency is shown as an IIR (infinite response) digital filter expressed by equation (1).
In FIG. 1, an adder 1 is supplied with an input signal, an adder 2 is supplied with the output of this adder 1, and a multiplier 4 is supplied with the output of the adder 1 via a unit time delay circuit 3. , 5. This multiplier 4 has cutoff frequency data given to the ROM 6.
Data b ₁ selectively output according to c is further supplied, and the input signal is multiplied by b ₁ and applied to the adder 1 . Note that this input signal is designed to specify subtraction to the adder 1. Further, the multiplier 5 is further supplied with data a ₁ selectively output from the ROM 6, and the input signal is multiplied by a ₁ , and the adder 2
given to. The output of the delay circuit 3 is further applied to multipliers 8 and 9 via a unit time delay circuit 7. The above multipliers 8 and 9 each have
The data b _{2 and} a ₂ supplied from the ROM 6 are further supplied, and the input signal is multiplied by b ₂ and a ₂ , and then sent to the adder 1,
given to 2. Note that the signal given to the adder 1 is designed to instruct subtraction. and,
The output of the adder 1 and the outputs of the multipliers 5 and 9 are supplied, and the output of the adder 2 that adds them is applied to the multiplier 10 that is supplied with the output K of the ROM 6 selected by the cutoff frequency c. The signal is then multiplied by K to become the output signal.

However, when changing the cutoff frequency c from a filter with characteristics "A" to a filter with characteristics "B", an analog filter with the same function would appear as a smooth change, but In the case of a digital filter, each coefficient is switched from characteristic "A" to characteristic "B", so its output is not continuous.
Therefore, when changing characteristics, in order to make a smooth change, it is necessary to make the characteristics close to each other, and if you want to change the characteristics significantly, change the characteristics gradually.
It is necessary to make the change smooth. In particular, when such digital filters are applied to electronic musical instruments and various types of audio equipment, the problem becomes even more pronounced. Therefore, each coefficient is set at very small intervals.
It is necessary to store it in ROM6, so
It required a large capacity ROM.

This invention was made in view of the above circumstances,
In a digital filter device in which coefficients of a transfer function are stored in advance and the characteristics are varied by switching the coefficients, when the characteristics are switched, the coefficients before switching are changed logarithmically to the coefficients after switching. The present invention aims to provide a digital filter device that can perform smooth interpolation.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

Although FIG. 2 shows the circuit configuration of this embodiment, in order to simplify the explanation, the same parts as those in FIG. That is, the coefficient outputs a ₁ , a ₂ , b ₁ , b ₂ , and K of the ROM 6 in FIG.
9, 4, 8, and 10, respectively. Since the interpolation circuits 11 to 15 all have the same configuration, the interpolation circuit 15 will be explained next. FIG. 3 is a diagram showing details of the interpolation circuit 15. 16 in the figure is a register that is given a coefficient K (KI in the figure) from the ROM 6 and latches at the timing of clock ₁ . The coefficient K (in the diagram
KO) will be subtracted. Then, the subtraction result is outputted from output terminal AB and supplied to the shift circuit 19. The output of this shift circuit 19 is then supplied to an input terminal A of an adder 20. The register 18 is connected to the input terminal B of the adder 20.
The output is supplied, and the addition result is output terminal A+B.
It is latched into the register 18 via the clock ₁ timing.

FIG. 4 shows details of the shift circuit 19. The input data is expressed in two's complement, and the most significant bit is a 7-bit input of a sign bit. This 7-bit data is transferred to flip-flops 31-38 via transfer gates 21-28.
is supplied to input terminal D of. Incidentally, the sign bit data of the input data is transferred to the transfer gates 21 and 22.
The bit data below is supplied to flip-flops 33-38. Therefore, the input data is right-shifted by one bit and sent to flip-flop 3.
1 to 38. The flip-flops 32-38 are supplied with data output from the output terminals Q of each flip-flop 31-37 via transfer gates 42-48, and the flip-flop 31 receives its own output via transfer gates 41. will be supplied.
The input data of the flip-flops 31 to 38 is latched by the clock ₁ . The output is given to the input terminal A of the adder 20, and is also supplied directly to the decoder 50 and via the inverters 61 to 68, and only when each bit output is all "0" or all "1", A "1" signal is output on line 70. The output of this line 70 is directly supplied to the transfer gates 21-28, and when the output of the line 70 is "1", the input data is shifted to the right by 1 bit and applied to the flip-flops 31-38. The inverted signals are applied to the transfer gates 41-48 via the line 70, and when the output of the line 70 is "0", the output data of each flip-flop 31-38 is shifted to the right by 1 bit and input as feedback. There is.

Therefore, this shift circuit 19 sequentially shifts the input data at the timing of clock ₁ , and when the input data is positive, the shift circuit 19 shifts the input data sequentially at the timing of clock 1.
The shift operation is stopped when all outputs of flip-flops 31 to 38 become "0", and if the input data is negative, the shift operation is stopped when all outputs of flip-flops 31 to 38 become "1", and the next input data is Latch onto flip-flops 31-38.

Next, the operation of this embodiment will be explained. now,
When a digital filter with characteristic "A" is constructed by selecting each coefficient of the transfer function expressed by equation (1) to a predetermined value, the transfer function will be described as shown in equation (2) below for convenience of explanation.

H _A (Z)=K _A・1+a _1A Z ^-1 +a _2A Z ^-2 /1+b _1A Z ^-1 +
b _2A Z ^-2 ...Equation (2) That is, each coefficient a ₁ , a ₂ , b ₁ , b ₂ , K is a _1A , a _2A , b _1A , b _2A , depending on the cutoff frequency c _A K _A
The value will be read from the ROM6. It is assumed that the coefficients a _1A , a _2A , b _1A , b _2A , and K _A are supplied to multipliers 5, 9, 4, 8, and 10, respectively. From this state, the cutoff frequency is c _B
When a digital filter with characteristic "B" is constructed by changing the transfer function as shown in equation (3) below, H _B (Z)=K _B・1+a _1B Z ^-1 +a _2B Z ^{- 2} /1+b _1B Z ^-1 +
b _2B Z ^-2 ...Equation (3) Coefficients a ₁ , a ₂ , b ₁ , b ₂ , K read from ROM6
are respectively a _1B , a _2B , b _1B , b _2B , and K _B .

In that case, if we focus on the coefficient K, the registers 16 and ₁₈ in _FIG .
Then, "K _B - K _A = △K" is calculated.
This data .DELTA.K is shifted to the right by 1 bit and latched in flip-flops 31 to 38 at the timing when clock ₁ is supplied to the shift circuit as shown in FIG. 5a. As a result, adder 20
Then, the output data K _A of the register 18 and the output ΔK/2 of the shift circuit 19 are added. Therefore, at the next clock ₁ , "K _A +ΔK/2" is latched in the register 18 and supplied to the multiplier 10 as the coefficient K. At the same time, the shift circuit 19
Since the output on line 70 is "0", the data in each flip-flop 31-38 is shifted to the right by 1 bit, and shift circuit 19 outputs ΔK/2 ² . Therefore, the content latched into the register 18 via the adder 20 at the next clock ₁ becomes "K _A +ΔK/2+ΔK/2 ² =K _A +3/4ΔK".

Similarly, the clock is input from register 18.
At the timing of ₁ , "K _A +3/4△K+1/2 ³ △K=K _A +7/8△K", "K _A +7/8△K+1/2 ⁴ △K=K _A +
15/16 △K”, “K _A +15/16△K+1/2 ⁵ △K=K _A +31/32△
K''...and the output changes logarithmically. FIG. 5b shows this situation. Therefore, when the outputs of flip-flops 31 to 38 all become "0" (if K _B < K _A , all the outputs of flip-flops 31 to 38 become "1"), the output of line 70 becomes "1", Shift circuit 19 will latch new input data. However, in that case, since the outputs of register 18 and register 16 are K _B , the data supplied to input terminal A of adder 20 becomes "0", and therefore coefficient K retains the value of K _B. become.

At that time, since the other interpolation circuits 11 to 14 operate in the same way, all other coefficients a ₁ , a ₂ , b ₁ , b ₂ are also a _1A , a _2A , b _1A , b in the same way as the coefficient K above. _2A to a _1B , a _2B ,
It is interpolated stepwise to b _1B and b _2B , resulting in a logarithmically smooth change.

In the above embodiment, the case where 8-bit data is supplied as coefficient data has been described, but in that case, the lowest bit of the output of the subtracter 17 is ignored, but the interpolation error is small. However, if the bit length of the coefficient data is increased, there is almost no problem.

Further, although the above embodiment has been explained with respect to a second-order/second-order IIR digital filter, it is possible to apply the present invention to a higher-order digital filter.
Furthermore, it goes without saying that the present invention can be similarly applied even when a predetermined coefficient of a transfer function is approximated by another coefficient, and the present invention can also be applied to digital filters having various other characteristics. .

In addition, it is a theory that various modifications and applications can be made without departing from the gist of the present invention.

As described in detail above, in a digital filter device in which the coefficients of a transfer function are written in advance and the characteristics are varied by changing the coefficients, when the characteristics are changed, the coefficients before the change change from the coefficients after the change. By performing logarithmic interpolation on the coefficients, it is possible to smoothly change the coefficients, so it is possible to reduce the capacity of the storage means for storing the coefficients, such as a ROM, which is useful for integrating digital filter devices. In addition, when this digital filter device is applied to electronic musical instruments or various types of audio equipment, the output sound changes audibly smoothly even when switching characteristics, eliminating unnatural or This is very effective as it eliminates unpleasant noise output.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of a conventional digital filter device, FIG. 2 is a circuit diagram of a digital filter device showing an embodiment of the present invention, and FIG. 3 is a diagram showing the main part configuration of FIG. 4 is a block diagram of the main part of FIG. 3, and FIG. 5 is a diagram for explaining the operation of this embodiment. 1, 2... Adder, 3, 7... Delay circuit, 4, 5,
8, 9, 10... Multiplier, 6... ROM, 11 to 15
...Interpolation circuit, 17...Subtractor, 19...Shift circuit,
20...Adder, 21-28, 41-48...Transfer gate, 31-38...Flip-flop,
50...decoder, 71...inverter.

Claims (1)

[Scope of Claims] 1. In a digital filter device in which coefficients of a transfer function are stored in advance and characteristics are varied by switching the coefficients according to a desired cutoff frequency, at least when switching the coefficients, switching is performed. A first arithmetic logic means that calculates the difference between the previous coefficient and the coefficient after switching, and a division process by a numerical value "2" based on the coefficient difference calculated by the first arithmetic logic means. A second arithmetic logic means for calculating control data; and a sequential addition process of the coefficients before switching based on the control data calculated by the second arithmetic logic means, thereby switching the coefficients. A digital filter device comprising: third arithmetic logic means for sequentially calculating transient coefficients at the time of the digital filter. 2. The second arithmetic logic means is equipped with a shift means for performing a 1-bit shift operation on the coefficient difference, and then sequentially outputting control data divided by a numerical value "2" by performing a 1-bit shift operation on its own feedback data, The third arithmetic logic means adds the control data to the coefficients before switching, and then sequentially adds the control data to its own feedback data to sequentially calculate transient coefficients when switching the coefficients. A digital filter device according to claim 1, characterized in that: 3. According to claim 1 or 2, the digital filter device comprises a plurality of sets of the first to third arithmetic logic means corresponding to the number of coefficients of the transfer function. digital filter device.