JPS6337417B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device using a semiconductor memory element.

Semiconductor memory elements are currently mainly used in memory devices. Especially dynamic
MOSRAM has quadrupled its density approximately every two to three years due to continuous technological improvements in circuit technology and process technology, and since the early 1980s it has reached 64K bits.
MOSRAM ICs are about to become widely used. Furthermore, in some cases by the mid-1980s,
It was predicted that 256K-bit MOSRAM would be put into practical use, and it was thought that the degree of integration of not only dynamic MOSRAM but also semiconductor memory elements would increase for the time being. However, recently a phenomenon commonly referred to as a soft error has been discovered that puts a brake on this high degree of integration. This soft error occurs as a result of a drop in the signal level within the IC chip due to higher integration, or a drop in the energy stored in the memory cell as stored information, resulting in information being reversed by alpha rays emitted from the IC case material. It is a general term for phenomena that are not caused by the hardware, and although methods such as applying a coating agent to the chip surface have been adopted as a countermeasure against alpha rays, ultimately It is impossible to completely prevent this by using devices alone. In a storage device using such an element that is sensitive to alpha rays, even if it has the function of correcting a 1-bit error, there is a high probability that soft errors of 2 or more bits will occur, making the device unreliable. do not have.

Conventionally known storage devices have no countermeasures against such elements, and have had to rely on improvements in the elements themselves to deal with alpha rays.
Soft errors are particularly problematic when information once written to an element is stored without being rewritten for a long period of time. The longer the period of neglect, the higher the incidence of errors that result in device failure due to soft errors.

FIG. 1 is a block diagram schematically showing such a conventional storage device, and is an example of a dynamic MOSRAM in which addresses are transferred in two steps. This device includes a write data register 1, a selector 2, a Hamming generation circuit 3, a Hamming correction circuit 4 for detecting a 1-bit error, a read data register 5, an address circuit 6, a memory array 100, a control circuit or a timing circuit (not shown), etc. The memory array 100 for storing write data has M memory elements, which are write/read units, arranged in N columns.

FIG. 2 is a detailed circuit diagram of the address circuit 6 shown in FIG. configured.

Since the operation of the conventional storage device shown in FIG. 1 is already well known, only the refresh operation related to the present invention, which will be described later, will be described.

With this device, write data is not stored during refresh operation.
WD and read data RD are unrelated, and circuits related to these are normally not operated.

The address register 60 is also generally irrelevant, and only the X address (refresh address) of the storage element is generated by the counter 62 and distributed to all the storage elements of the storage array 100 via the selectors 63 and 64. In a normal read/write operation, the element column address bit AC for selecting a desired memory element column in the memory array 100 from the address register 60 is decoded by the decoder 61 and a signal is sent only to the expected element column. However, during the refresh operation, as is clear from the configuration of the gate circuit 65 or gate circuit 67, a signal (1 -),
The signal is inhibited to refresh all storage elements in storage array 100 simultaneously.

The refresh operation of the prior art has been explained above, but as is clear from these explanations, in the prior art, once written data in the storage array 100 is not rewritten unless it is rewritten with new data.
It is saved as is, only being refreshed. Therefore, if data is inverted due to a soft error, the inverted data will continue to be stored. In the example of the prior art shown in FIG. 1, a 1-bit error is corrected, so inversion of only 1 bit does not cause a problem. However, if after 1 bit is inverted, another 1 bit in the same address as that bit is further inverted, 2 bit errors occur during reading. Even though there is no problem with the hardware due to the bit error, the CPU that receives the read data will determine that the problem is with the storage device.

An object of the present invention is to provide a storage device that can reduce the probability of device failure occurring due to the above-mentioned soft errors.

In order to achieve the above object, a memory device according to the present invention uses a memory array in which semiconductor memory elements are arranged in an array, in which an arbitrary element column of the memory array is selected, and the selected memory element column is Writing back data read by accessing each memory element address using a load address and a column address is written back to the accessed address via a correction circuit using a partial write circuit, regardless of the presence or absence of an error. and a refresh means for refreshing an address in each memory element accessed by the load address in a memory element column other than the memory element column in parallel with writing back by the write back means.

According to the above configuration, the probability of failure occurrence due to soft errors can be suppressed to a low level, and the object of the present invention can be completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the storage device according to the present invention, in which an address circuit 7 is used in place of the address circuit 6 used in the prior art of FIG. 1, and a control circuit (not shown) is used. The timing circuit has been modified to enable the functionality described below.

FIG. 4 explains the details of the address circuit 7 shown in FIG. 3. The address circuit 7 has a counter 72 instead of the counter 62 of the address circuit 6 of the prior art shown in FIG. Gate circuits 77 and 78 are used, and a selector 170
and a selector 171 are added and configured as shown in the figure.

In FIGS. 3 and 4, selectors 170, 171, 63, and 64 are controlled so that addresses are given to storage array 100 from address register 60 during normal write and read operations, and during refresh operations. is the counter 72
It is controlled so that the address is given from The counter 72 has only the number of bits for the refresh address (X address), whereas the counter 62 of the prior art has only the number of bits for the refresh address (X address).
Address register 6 has the same number of bits as 0.
0 storage element column bit AC, Y address bit
Storage element column bits RC and Y address bits corresponding to AY and X address bits AX, respectively.
Consists of RY, X address bit AX, RX →
In the order of RC→RY or RX→RY→RC (in Figure 4)
(Explained in RX → RC → RY) It is counted up every time the refresh operation is completed.

Furthermore, the gate circuits 77 and 78 differ from the gate circuits 67 and 68 in FIG.
Since REF is not input, the memory element column bit RC of the counter 72 is decoded by the decoder 61 via the selector 170, and a signal is applied only to the corresponding memory element column.

In the present invention, the refresh operation of the storage device is controlled as if it were a partial byte write operation. The difference from normal partial byte write operation is
The fact that the RAS signal is applied to all the storage element columns means that the selectors 63, 170, and 171 are controlled to select the counter 72 side. Furthermore, in a normal partial byte write operation, newly rewritten data is set in write register 1,
After the 1-bit error in the read data from the storage array 100 is corrected by the Hamming correction circuit 4, only the data at the designated byte position is stored in the write register 1.
data is exchanged with the data in the selector 2, a new humming is added in the humming generation circuit 2, and the data is rewritten in the storage array 100. In contrast, in the refresh operation, the error-corrected read data is rewritten in the storage array 100 as it is. Selector 2 is controlled so that

Write/read designation signals from a timing circuit and a control circuit (not shown) are applied to storage array 100 during a refresh operation in the same way as in a normal partial byte write operation.

As is clear from the above description, in the present invention, during the refresh operation, the memory element column specified by the memory element column bit RC of the counter 72 performs a partial byte write operation, and the other memory element columns (
Since no signal is given, a refresh operation is performed. Moreover, in this partial byte writing, if there is a 1-bit error in the stored data, it is corrected and rewritten, so the data contents do not change before and after the refresh operation is completed.

As described above, in the storage device of the present invention, the counter 7
2, data will be rewritten at least once in all memory elements in the memory array 100, regardless of whether there is a write operation to the memory device. By the way, in order to estimate the rewriting cycle T _RW , M = 72 (i.e. data processing width 8B)
Let us perform calculations assuming that the capacity of the storage device is 8MB (N=64 if the storage element is a 16K-bit MOSRAM).

The refresh cycle of the memory element is 2ms, which is the standard for general dynamic MOSRAM, and if the number of refresh cycles is 128, then the memory array 1
Since 16 μs is required to rewrite one address within 00, T _RW =16 μs×2 ^(x+y+c) =16 μs×20 ²⁰ ≒17 seconds. (However, x, y, and c are the X address bits RX and Y address bits of the counter 72, respectively.
RX, the number of bits in the memory element row bit RC,) In other words, under the above assumption, all memory elements are rewritten at least once every 17 seconds, so the reliability of the memory elements against soft errors is If the probability that one bit of data will be reversed within the same address of an element is sufficiently negligible within 17 seconds, the storage device using the present invention can be made free from problems with soft errors. It is.

Although one embodiment has been described above, it is clear that the same effect as described above can be obtained not only by a partial byte write operation but also by a continuous operation of a read operation and a write operation during a refresh operation.

In addition, the data that has been read and whose errors have been corrected is written to the memory array through the Hamming generation circuit again, but this path is always present if the memory device has a partial byte write function. , it is clear that the same effect can be obtained even if the configuration is configured such that the path is simply used and the Hamming generation circuit is not used.

As explained above, the storage device according to the present invention is configured such that the storage device itself rewrites the stored information at regular intervals, so that the influence of soft errors can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram partially showing a conventional storage device, FIG. 2 is a circuit diagram showing an address circuit of the conventional storage device shown in FIG. 1, and FIG. 3 is an implementation of the storage device according to the present invention. FIG. 4 is a block diagram partially showing an example, and FIG. 4 is a circuit diagram showing an address circuit of the memory device shown in FIG. 3, which is an embodiment of the present invention. 1...Write data register, 2...Selector,
3... Hamming generation circuit, 4... Hamming correction circuit, 5... Read data register, 6... Address circuit, 7... Address circuit, 60... Address register, 61... Address decoder, 62... Counter, 63, 64...Selector, 65, 66...
...Gate circuit, 67, 68...Gate circuit, 72
... Counter, 77, 78 ... Gate circuit, 10
0...Storage array, 170, 171...Selector.

Claims (1)

[Scope of Claims] 1. In a memory device using a memory array in which semiconductor memory elements are arranged in an array, an arbitrary element column of the memory array is selected, and an address within each memory element of the selected memory element column is set. The data read by accessing by row address and column address is read regardless of whether there is an error or not.
a write-back means using a partial write circuit to write back to the accessed address via a correction circuit; and a refresh of each address in each memory element accessed by the row address in a memory element column other than the memory element column. A storage device characterized by comprising: a refresh unit that performs the write-back by the write-back unit in parallel with the write-back by the write-back unit.