JPS6337515B2 - - Google Patents
Info
- Publication number
- JPS6337515B2 JPS6337515B2 JP10127083A JP10127083A JPS6337515B2 JP S6337515 B2 JPS6337515 B2 JP S6337515B2 JP 10127083 A JP10127083 A JP 10127083A JP 10127083 A JP10127083 A JP 10127083A JP S6337515 B2 JPS6337515 B2 JP S6337515B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- copper foil
- etching
- plating
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 49
- 239000011889 copper foil Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 14
- 230000007797 corrosion Effects 0.000 claims description 9
- 238000005260 corrosion Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 239000011888 foil Substances 0.000 claims 1
- 239000000654 additive Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 2
- 229910000365 copper sulfate Inorganic materials 0.000 description 2
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、微細パターンを容易に得ることが出
来る印刷配線板の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a printed wiring board that can easily obtain a fine pattern.
(従来の技術)
近年印刷配線板の線巾、線間隔はLSIの高集積
化にともないますます細くなつている。印刷配線
板の製造方法としては、銅張り積層板をエツチン
グしてパターンを形成するサブトラクト法、必要
な部分にめつきにより回路を形成するアデイテイ
ブ法、5〜9μmの銅箔を用いた銅張積層板をベ
ースにめつきにより必要な部分にめつきをした
後、ベースの薄い銅箔をクイツクエツチするセミ
アデイテイブ法があり、特にセミアデイテイブ法
が微細パターンに適している。(Prior art) In recent years, the line width and line spacing of printed wiring boards have become thinner and thinner as LSIs become more highly integrated. Manufacturing methods for printed wiring boards include the subtract method in which a pattern is formed by etching a copper-clad laminate, the additive method in which circuits are formed by plating in the required areas, and copper-clad laminate using 5-9 μm copper foil. There is a semi-additive method in which the necessary parts are plated using a plate as a base, and then the thin copper foil on the base is quickly quenched.The semi-additive method is particularly suitable for fine patterns.
(発明が解決しようとする課題)
従来の製造方法では、例えば、銅張り積層板を
エツチングしてパターンを形成するサブトラクト
法では、線巾100μmが加工限界となり、これ以
下の線巾では、断線やシヨートを発生し易くな
る。これは銅張積層板製造工程において発生する
銅箔面のへこみ、キズなどが原因である。(Problems to be Solved by the Invention) In conventional manufacturing methods, for example, in the subtract method in which a pattern is formed by etching a copper-clad laminate, a line width of 100 μm is the processing limit, and a line width smaller than this may cause wire breakage or Shoots are more likely to occur. This is caused by dents, scratches, etc. on the copper foil surface that occur during the manufacturing process of copper-clad laminates.
また、線巾、線間隔が50μm以下のパターンを
形成する場合、銅張積層板の表面に微小な凹凸や
うねりがあると、所要のエツチングレジストを形
成する際に、レジストへの照射光の入射角度が一
定とならず、そのため、例えば、照射光が斜めに
入射するところでは線巾が広くなるなど一定の線
巾のパターンとならず、線巾精度のよいパターン
を形成できなくなる。 In addition, when forming a pattern with a line width and line spacing of 50 μm or less, if there are minute irregularities or undulations on the surface of the copper-clad laminate, when forming the required etching resist, the incidence of irradiation light on the resist may be affected. The angle is not constant, and therefore, for example, where the irradiation light is obliquely incident, the line width becomes wider, making it impossible to form a pattern with a constant line width, making it impossible to form a pattern with good line width accuracy.
また、通常銅箔が18〜35μmと厚いため100μm
以下というような細い巾のエツチングは非常に困
難である。5〜9μmの銅箔を用いればエツチン
グは容易になるが、内層回路部はともかく、表層
部には、スルーホールめつきが附加されるので、
全体の銅の厚さは30〜40μmとなり100μm以下の
線巾又は線間隔でのエツチングが困難である点に
ついては変わりがない。 In addition, copper foil is usually thick at 18 to 35 μm, so 100 μm
Etching a narrow width like the one shown below is extremely difficult. Etching will be easier if a copper foil of 5 to 9 μm is used, but since through-hole plating is added to the surface layer, aside from the inner layer circuit portion,
The overall copper thickness is 30 to 40 .mu.m, and there is no difference in the fact that etching with a line width or spacing of 100 .mu.m or less is difficult.
このような事から、エツチング法ではなく、必
要な部分にめつきにより回路を形成するアデイテ
イブ法が微細パターンの形成に適するが、現状で
は基板表面の粗度が大きく、また、不必要な場所
にもめつきが析出する銅フリ現象があり、サブト
ラクト法以上の微細パターンの形成ができない。 For these reasons, the additive method, in which circuits are formed by plating in the necessary areas, rather than the etching method, is suitable for forming fine patterns, but at present, the substrate surface has a large roughness, and it is difficult to place circuits in unnecessary places. There is a copper frizz phenomenon in which mottling precipitates, and it is not possible to form finer patterns than the subtract method.
セミアデイテイブ法においても、前記した銅張
積層板自体の欠陥や特性に支配され、80μm以下
の微細パターンの形成は困難である。 Even in the semi-dative method, it is difficult to form a fine pattern of 80 μm or less because it is dominated by the defects and characteristics of the copper-clad laminate itself.
(課題を解決するための手段)
本発明はこのような点に鑑みてなされたもの
で、銅箔1の一面に所要のめつきレジスト2を形
成した後この面に銅のエツチング液に耐蝕性のあ
る金属3をめつきし更に銅4をめつきして銅のエ
ツチング液に耐蝕性のある金属と銅とからなる回
路パターン5を形成し、前記めつきレジスト2を
除去し、前記回路パターン5を形成した面に絶縁
材料12を重ね合せ加熱加圧し、所要の穴あけ及
び穴内壁の銅めつき7を行い、前記銅箔1の他面
に所要のエツチングレジストを形成した後銅箔1
をエツチングすることを特徴とするものである。(Means for Solving the Problems) The present invention has been made in view of the above points, and after forming a required plating resist 2 on one surface of a copper foil 1, this surface is coated with a copper etching solution that is resistant to corrosion. A certain metal 3 is plated and copper 4 is further plated to form a circuit pattern 5 made of copper and a metal that is resistant to corrosion in a copper etching solution.The plating resist 2 is removed and the circuit pattern is The insulating material 12 is superimposed on the surface on which the copper foil 1 is formed and heated and pressurized, the required holes are drilled and the inner wall of the hole is copper plated 7, and the required etching resist is formed on the other surface of the copper foil 1.
It is characterized by etching.
すなわち、従来技術で用いられる銅張積層板自
体の特性や欠陥に基づく限界を打破するために本
発明では、回路パターン5を形成するベース材料
として銅箔を用いる。用いる銅箔はステンレス板
等に剥離可能なようにめつきした銅箔でも良い
し、すでに引きはがされた銅箔あるいは圧延され
た銅箔でもよい。第1図に示すようにこの銅箔1
の一面に、フオトレジストをラミネートし、焼
付、現像する等により所要のめつきレジスト2を
形成する。次に無電解めつき、または、電気めつ
きにより金、ニツケル、はんだなど銅のエツチン
グ液に耐蝕性のある金属3をこの面にめつきした
後更に銅めつき4を行う。めつきレジスト2を剥
離した後、この表面に接着処理を行う。 That is, in order to overcome the limitations based on the characteristics and defects of the copper-clad laminate itself used in the prior art, the present invention uses copper foil as the base material for forming the circuit pattern 5. The copper foil used may be a copper foil peelably plated onto a stainless steel plate or the like, a copper foil that has already been peeled off, or a rolled copper foil. As shown in Figure 1, this copper foil 1
A required plating resist 2 is formed by laminating a photoresist on one side of the substrate, and then baking and developing the photoresist. Next, a metal 3 such as gold, nickel, or solder which is resistant to corrosion by a copper etching solution is plated on this surface by electroless plating or electroplating, and then copper plating 4 is further performed. After peeling off the plating resist 2, an adhesive treatment is performed on this surface.
次に第2図に示すように、このようにして形成
した回路パターン5を有する銅箔1を表層とし
て、回路パターン5を内側にして内層回路板6と
共に層間位置決めをし、プリプレグ12を介して
積層接着する。さらに、穴あけ、スルーホールめ
つきを行う。次に、穴内壁および、銅箔1の所要
の部位をパツド部その他銅箔によつて形成したい
表面パターンが残るようにテンテイングまたはは
んだにより保護して、銅箔1をエツチングする。
ベースとなつた銅箔1がエツチング除去されると
あらかじめ形成された回路パターン5が基板内に
埋め込まれた形で露出する。 Next, as shown in FIG. 2, the copper foil 1 having the circuit pattern 5 formed in this way is used as the surface layer, and the circuit pattern 5 is placed on the inside for interlayer positioning together with the inner layer circuit board 6. Laminate and glue. Furthermore, drilling and through-hole plating are performed. Next, the copper foil 1 is protected by tenting or soldering so that the inner wall of the hole and a desired portion of the copper foil 1 are left with pads and other surface patterns to be formed with the copper foil, and the copper foil 1 is etched.
When the copper foil 1 serving as the base is removed by etching, the circuit pattern 5 formed in advance is exposed in the form of being embedded in the substrate.
第3図は、このようにして得られた印刷配線板
の断面を示すもので、7はスルーホールめつき、
8は内層回路、5はあらかじめ形成された回路パ
ターンで露出面には銅のエツチング液に耐蝕性の
ある金属3がめつきされており、1はエツチング
されずに残つた銅箔である。 Figure 3 shows a cross section of the printed wiring board obtained in this way, with 7 having through-hole plating;
Reference numeral 8 denotes an inner layer circuit, 5 a preformed circuit pattern, the exposed surface of which is plated with a metal 3 that is resistant to corrosion by a copper etching solution, and 1 a copper foil that remains without being etched.
(実施例)
ステンレス(SUS430―BA)表面をスコツチ
ブライト7448で研磨後、全面に30μm厚の硫酸銅
めつきを行つた。次に、フオトレジスト(リスト
ンT―1215)をロールラミネータによりラミネー
トした。40μmと65μmの線巾のパターンを有す
るポジマスクを当て紫外線を照射した後、現像液
をスプレーし現像した。次に、金めつきを1μm
の厚さで行い、さらに硫酸銅めつきを30μm行つ
た。レジスト剥離液に浸漬し、レジストを剥離
し、黒色酸化銅処理を行つた後、パターンの形成
された銅箔をステンレス板よりはがし取つた。こ
の銅箔とあらかじめエツチング法で作成した内層
板との間に接着用プリプレグを介して位置決めピ
ンにより位置決めできる多層化金型にセツトし、
170℃2時間60Kg/cm2の圧力で加圧加熱した。こ
のようにして積層した基板にNCドリルにより穴
あけを行つた後、無電解めつきによりスルーホー
ルめつきを行つた。(Example) After polishing the surface of stainless steel (SUS430-BA) with Scotch Bright 7448, the entire surface was plated with copper sulfate to a thickness of 30 μm. Next, a photoresist (Riston T-1215) was laminated using a roll laminator. After applying a positive mask having patterns with line widths of 40 μm and 65 μm and irradiating it with ultraviolet rays, a developer was sprayed and developed. Next, apply gold plating to 1μm.
Copper sulfate plating was further performed to a thickness of 30 μm. After immersing in a resist stripping solution to strip the resist and performing black copper oxide treatment, the patterned copper foil was peeled off from the stainless steel plate. This copper foil is placed in a multilayer mold that can be positioned using positioning pins via an adhesive prepreg between the inner layer plate prepared in advance by an etching method, and
The mixture was heated at 170° C. for 2 hours at a pressure of 60 kg/cm 2 . After drilling holes in the thus laminated substrates using an NC drill, through-hole plating was performed using electroless plating.
次に、フオトレジスト(リストンT―1215)を
ラミネートし、穴の周囲にパツドを形成するよう
に焼付、現像を行つた。続いて、内蔵された金め
つきが露出するまで表面の銅をエツチングして所
望の多層印刷配線板を製作した。得られた金と銅
とからなる回路パターンは、線巾40μmのもの及
び65μmのもののいずれもその線巾は極めて均一
であり断線やシヨートは全く認められなかつた。 Next, photoresist (Riston T-1215) was laminated, baked and developed to form a pad around the hole. Subsequently, the copper on the surface was etched until the built-in gold plating was exposed to produce the desired multilayer printed wiring board. The obtained circuit patterns made of gold and copper had a line width of 40 .mu.m and a line width of 65 .mu.m, both of which had extremely uniform line widths, with no wire breaks or shorts observed.
(発明の効果)
以上説明したように、本発明の印刷配線板の製
造法によれば、次のよな利点が達成される。(Effects of the Invention) As explained above, according to the method for manufacturing a printed wiring board of the present invention, the following advantages are achieved.
(1) 表面の平滑な銅箔面上にパターンを形成する
のでレジストに対する照射光の入射角を一定に
でき、線巾、線間隔がそれぞれ100μm以下の
微細パターンを精度よく得ることができる。(1) Since the pattern is formed on a copper foil surface with a smooth surface, the angle of incidence of the irradiation light on the resist can be kept constant, and a fine pattern with a line width and a line interval of 100 μm or less can be obtained with high accuracy.
(2) あらかじめ微細パターンを形成した後に積層
するので、積層前に検査でき歩留りが向上す
る。(2) Since fine patterns are formed in advance and then laminated, inspection can be performed before lamination, improving yield.
(3) 正確に形成されたレジスト像の間にめつきに
より導体を形成し、さらにこの導体が絶縁材料
に埋め込まれ更にその表面は銅のエツチング液
に耐蝕性のある金属で完全に保護されているの
で、サイドエツチがなく、線巾精度が極めて高
い。(3) A conductor is formed by plating between precisely formed resist images, and this conductor is further embedded in an insulating material, and its surface is completely protected by a metal that is resistant to corrosion by copper etching solution. Because of this, there is no side etching and the line width accuracy is extremely high.
(4) 第4図に示すように、耐蝕性金属3と銅4よ
り成る埋め込まれた導体のみよりなる回路9、
エツチングされずに残つた銅箔1のみよりなる
回路10又はそれらの双方の導体より成る回路
11が任意に形成できる。従つて、同じ線巾で
電流容量の異なつた回路を構成できる。(4) As shown in FIG. 4, a circuit 9 consisting only of an embedded conductor made of a corrosion-resistant metal 3 and copper 4;
A circuit 10 consisting only of the copper foil 1 remaining without being etched, or a circuit 11 consisting of both conductors can be arbitrarily formed. Therefore, circuits with different current capacities can be configured with the same line width.
(5) 大部分の回路を絶縁材料中に埋め込まれた形
とすることができるので、回路部分による凹凸
を少なくすることができる。このため、はんだ
レジストの塗布を均一に行うことができ、良好
なはんだづけができる。(5) Since most of the circuits can be embedded in the insulating material, unevenness caused by the circuit parts can be reduced. Therefore, the solder resist can be applied uniformly, and good soldering can be achieved.
第1〜4図は本発明の方法を説明するための断
面図である。
符号の説明、1:銅箔、2:めつきレジスト、
3:銅のエツチング液に耐蝕性のある金属めつ
き、4:銅めつき、5:回路パターン、7:スル
ーホールめつき、12:プリプレグ(絶縁材料)。
1 to 4 are cross-sectional views for explaining the method of the present invention. Explanation of symbols, 1: Copper foil, 2: Plating resist,
3: Corrosion-resistant metal plating with copper etching solution, 4: Copper plating, 5: Circuit pattern, 7: Through-hole plating, 12: Prepreg (insulating material).
Claims (1)
た後この面に銅のエツチング液に耐蝕性のある金
属をめつきし更に銅をめつきして銅のエツチング
液に耐蝕性のある金属と銅とからなる回路パター
ンを形成し、前記めつきレジストを除去し、前記
回路パターンを形成した面に絶縁材料を重ね合せ
加熱加圧し、所要の穴あけ及び穴内壁の銅めつき
を行い、前記銅箔の他面に所要のエツチングレジ
ストを形成した後銅箔をエツチングすることを特
徴とする印刷配線板の製造法。1 After forming the required plating resist on one side of the copper foil, plate this surface with a metal that is resistant to corrosion in a copper etching solution, and then plate copper and apply a metal that is resistant to corrosion in a copper etching solution. A circuit pattern made of copper is formed, the plating resist is removed, an insulating material is overlaid on the surface on which the circuit pattern is formed, heated and pressurized, the required holes are drilled, and the inner walls of the holes are plated with copper. A method for manufacturing a printed wiring board, which comprises etching the copper foil after forming a required etching resist on the other side of the foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10127083A JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10127083A JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59227185A JPS59227185A (en) | 1984-12-20 |
| JPS6337515B2 true JPS6337515B2 (en) | 1988-07-26 |
Family
ID=14296190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10127083A Granted JPS59227185A (en) | 1983-06-07 | 1983-06-07 | Method of producing printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59227185A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03613A (en) * | 1989-05-17 | 1991-01-07 | Dainippon Printing Co Ltd | Electronic component carrier creation device |
| JPH0462605U (en) * | 1990-10-09 | 1992-05-28 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4534575B2 (en) * | 2004-04-23 | 2010-09-01 | パナソニック電工株式会社 | Wiring board manufacturing method |
| TW200618705A (en) | 2004-09-16 | 2006-06-01 | Tdk Corp | Multilayer substrate and manufacturing method thereof |
| JP2011134758A (en) * | 2009-12-22 | 2011-07-07 | Meiko:Kk | Manufacturing method for printed board and printed board |
-
1983
- 1983-06-07 JP JP10127083A patent/JPS59227185A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03613A (en) * | 1989-05-17 | 1991-01-07 | Dainippon Printing Co Ltd | Electronic component carrier creation device |
| JPH0462605U (en) * | 1990-10-09 | 1992-05-28 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59227185A (en) | 1984-12-20 |
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