JPS6337976B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an improvement in a digital filter device that performs overflow processing for the dynamic range of calculations and also controls the gain of the filter in the event of an overflow. Conventionally, various digital filter devices including multipliers, adders, delay circuits, etc. have been considered. However, in this digital filter device, especially in a cyclic digital filter device, if an overflow occurs beyond the dynamic range of the operation, the filter will go into an oscillation state, causing serious problems such as malfunction. . Therefore, in digital filter devices, in order to prevent overflow from occurring as much as possible, calculations are performed with a wide dynamic range set in advance. Therefore, if the digital filter device is operated under normal conditions, the upper bits of the data are hardly used effectively, which is extremely uneconomical, and the noise ratio between the input and output of the digital filter device deteriorates. was imitating Furthermore, compared to the number of input bits, the digital filter device has a
When the number of output bits becomes large, for example, when the output of a digital filter device is supplied to a D-A converter, the number of processing bits for D-A conversion must be increased, and the digital filter devices must be connected in cascade. It was virtually impossible to do so due to the discrepancy in the number of input and output bits. However, when using such a digital filter device to achieve a resonance characteristic in which the amplitude characteristic has a peak at a selected frequency, as mentioned above, the dynamic range must be very wide, and it is completely difficult to This inevitably results in an uneconomical circuit configuration, and as the circuit scale increases, various problems arise, such as deterioration of the noise-to-noise ratio. Therefore, the present applicant has previously filed a patent application for an invention in which the gain coefficient of the filter is reduced when the calculated data overflows beyond the dynamic range. However, even in that case, if the gain coefficient is switched to a smaller value due to changes in the cutoff frequency while overflow is occurring, there is a possibility that 0 or negative data will be output as the gain coefficient. Ta. The present invention has been made in view of the above points, and
If the processing data overflows the dynamic range of the calculation, the gain coefficient of the filter is decreased, and if the decreased gain coefficient is no longer a positive value, the gain coefficient is set to a positive value. An object of the present invention is to provide a digital filter device which outputs data of . Hereinafter, one embodiment of the present invention will be described in detail. FIG. 1 shows the circuit configuration of the digital filter device of this embodiment. The transfer function H(Z) of the digital filter can be obtained from the transfer function H(S) of the analog filter by some kind of conversion, but in the case of this embodiment, it is obtained from the transfer function of the second-order analog low-pass filter as follows. By performing bilinear Z transformation, we obtain the transfer function H(Z) of the following formula, H(Z)=K・(1+Z ^-1 ) ² /1+b ₁ Z ^-1 +b ₂ Z ^-2 ...Equation
(1) A digital filter device is constructed based on this transfer function H(Z). However, the above formula (1)
In, the coefficients b ₁ and b ₂ are coefficients related to the characteristics of the filter, the position of the pole is determined, and the coefficient K is
This is the gain coefficient that determines the overall gain of the filter. 1 in the figure is a multiplier, which inputs data based on the coefficient K'' supplied from the gain coefficient control circuit 2.
The output of the adder 3 is then supplied to an overflow processing circuit 4, which will be described later, and after being subjected to overflow processing, is supplied to a delay circuit 5 that delays by a unit time. Along with being
The output of this overflow processing circuit 4 is supplied to an adder 6. Furthermore, the output of the delay circuit 5 is supplied to the adder 6 after being doubled by a multiplier 7, these data are added, and the resulting data is supplied to the adder 8. Further, the output of the delay circuit 5 is multiplied by _b1 in a multiplier 9 and supplied to an adder 10, and also to a delay circuit 11 which delays by a unit time. The output of this delay circuit 11 is directly supplied to the adder 8, and also supplied to the multiplier 12, multiplied by _b2 , and supplied to the adder 10. In the adder 10, the output of the multiplier 9 and the multiplier 1
Each of the two outputs is subtracted and applied to the adder 3.
Therefore, the adder 3 adds the output of the multiplier 1 and the output of the adder 10. Further, 13 in the figure is a gain control circuit which will be described later, and the output of this circuit is supplied to an adder 14, and the coefficient K
The gain of the filter is controlled by controlling the degree to which the filter is reduced. The adder 14 adds the coefficient K and the output of the gain control circuit 13 to obtain a coefficient K', which is supplied to the gain coefficient control circuit 2 described above. The output of the digital filter device configured in this manner is the output of the adder 8, which adds the output of the adder 6 and the output of the delay circuit 11. The coefficients K, b ₁ and b ₂ supplied to the adder 14 and multipliers 9 and 12 are given from a ROM (read only memory) and are data corresponding to the cutoff frequency. Further, the arithmetic processing of the digital filter device is performed entirely in parallel using two's complement representation, and its signal propagation lines are also provided in parallel. Next, an outline of the overflow processing circuit 4 will be explained. That is, assuming that the absolute value of the input signal from multiplier 1 to adder 3 is less than 1,
The following assumption is made: ``The absolute value of the output of the digital filter device is data less than 1.'' Furthermore, in order for the filter to operate stably, _all the poles of the transfer function must be within _the unit circle on the Z plane. ), (3) are obtained. |b ₁ |<2...Equation (2) |b ₂ |<1...Equation (3) Now, if the absolute value of the output of the overflow processing circuit 4 is less than d, the absolute value of the output of the multiplier 7 is
2d, so the absolute value of adder 6 output is
Therefore, the absolute value of the adder 8 output is less than 4d. Therefore, in order to satisfy the above assumption, the data d must be set to d=1/4. In this way, when d=1/4, the size of each data within the circuit path of this digital filter device is as shown in Table 1.

[Table] Therefore, the absolute value of the input to the overflow processing circuit 4 is less than 7/4, and the overflow processing circuit 4 has the absolute value of the output data less than 1/4 of this input data. It is controlled so that the The details of this overflow processing circuit 4 will be explained below with reference to FIG. As mentioned above, the input of this overflow processing circuit 4 has an absolute value of 7/4
Since it is less than
The decimal point is 8 bits. Of this data, the second and eighth bits below the decimal point are:
The first and second bits below the decimal point and the first and second bits above the decimal point are supplied directly to the AND gate 15 and also to the AND gate 20 via the inverters 16 to 19. be done. The outputs of the AND gates 15 and 20 pass through an OR gate 21 to become opening signals for the transfer gates 22 to 28, and also pass through an inverter 29 to serve as opening signals for transfer gates 31 to 37, which will be described later. That is, the sign bit, which is the second bit above the decimal point of the input data, is supplied to the transfer gate 31, and the sign bit is supplied to the transfer gate 31.
37 are each supplied with a signal in which the sign bit is inverted by the inverter 30. When the output of the OR gate 21 is "1", the outputs of the transfer gates 22 to 28 become the outputs of the overflow processing circuit 4.
1 output is “0”, transfer gate 3
The outputs 1 to 37 are the outputs of the overflow processing circuit 4. The overflow processing circuit 4 outputs a sign bit as the most significant bit, and weighted data of "2 ^-3 " to "2 ^-8 " as the second to seventh bits. Furthermore, the output of the inverter 29, ie, an overflow signal that outputs a signal "1" when the absolute value of the input exceeds 1/4, is supplied to the gain control circuit 13. Next, referring to FIG. 3, the gain control circuit 1
3 will be explained in detail. The output of the inverter 29 is given to one input terminal A of full adders 40 to 49, respectively, and the inverter 5
The signal inverted at 0 is applied to the carry input terminal C of the full adder 40. Furthermore, this adder 40
This full adder 40 is connected to the other input terminal B of ~49.
The signal outputted from the output terminal S of .about.49 is delayed for a unit time via the delay circuit 51, and the most significant bit (sign bit) of the output is directly transmitted from the 10th bit to the 2nd bit (" ^2-9 "). ˜“2 ⁻¹ ”) are applied via AND gates 52-60. Incidentally, the adders 40 to 48 provide carry signals from their carry output terminals CO to the carry input terminals C of the upper bit side full adders 41 to 49, respectively. The sign bit output of the delay circuit 51 is applied to one end of the AND gates 52 to 60, and only when this output is "1", that is, the output value is a negative number, the AND gates 52 to 60 are The 10th to 2nd bit outputs applied from the delay circuit 51 are supplied to the full adders 40 to 48, and also applied to the adder 14 in FIG. Next, referring to FIG. 4, gain coefficient control circuit 2
The details will be explained below. The gain coefficient control circuit 2 is given a coefficient K' by an adder 14.
This coefficient K' consists of data whose most significant bit is a sign bit and which is weighted from "2 ^-1 " to "2 ^-8 ". All bit data except the sign bit is
AND gates 61 to 67 and OR gate 68 respectively
It is also applied to AND gate 77 via inverters 69-76. Further, the sign bit is also inverted by an inverter 78 and applied to the AND gate 77. However,
The output of this AND gate 77 is applied to an OR gate 68 via an OR gate 79. Further, the code bit data is transferred to an inverter 80.
It is applied to the AND gates 61 to 67 and also to the OR gate 79 via the AND gates 61 to 67. Incidentally, the sign bit of the output of the gain coefficient control circuit 2 is set to always be "0". Therefore, when the coefficient K', which is the input data, is zero or negative, the gain coefficient control circuit 2 outputs data of "2 ^{- 8} ", which is the minimum positive value, as the coefficient K'', and the coefficient If K′ is positive, AND gates 61 to 67 are opened, and the coefficient
K′ will be output as a coefficient K″. Next, the operation of this embodiment will be explained. Namely,
First, the operation of the overflow processing circuit 4 will be explained with reference to FIG. FIG. 5A shows that when the absolute value of the input data to the overflow processing circuit 4 is smaller than 1/4, that is, when it is a positive value, the 4 bits from the second bit below the decimal point onwards are all 0, and the negative When the value is , the above four bits are all 1, so the signal "1" is output from the AND gate 15 or 20 in FIG. 2, and therefore the transfer gates 22 to 28 are opened. , the input data becomes the output data as is. Further, FIG. 5B shows a case where the absolute value of the input data to the overflow processing circuit 4 is 1/4 or more and less than 1/2. In this case, the output of the OR gate 21 becomes "0", so the transfer Agate 31-37
will be opened. Therefore, if the input data to the overflow processing circuit 4 is a positive value,
Only the sign bit is set to "0" and all other bits are set to "1" and output. On the other hand, if the above input data is a negative value, only the sign bit is set to "1" and the other bits are set to "1". All will be output as "0". Therefore, in this case, the output of the overflow processing circuit 4 becomes the maximum value of the dynamic range when it is positive, and becomes the minimum value of the dynamic range when it is negative. Furthermore, FIGS. 5C and 5D respectively show the case where the absolute value of the input data to the overflow processing circuit 4 is 1/2 or more and less than 1, and the case where it is 1 or more and less than 7/4, respectively. In this case, the overflow processing circuit 4 operates in the same way as in the case of FIG. It is something. Therefore, in the digital filter device shown in FIG. 1, overflow to the dynamic range is prevented by the overflow processing circuit 4, and it is possible to prevent overflow of the external device to which this digital filter device is connected. , it is also possible to prevent oscillation of the digital filter device. Therefore, when the output of the inverter 29 in the overflow processing circuit 4 is "0", that is, when there is no overflow with respect to the dynamic range, the full adder 4 of the gain control circuit 13 in FIG.
The value of data "2 ^-10 " is applied to the input terminal A of 0 to 49. Therefore, adders 40-4
9, the outputs of the AND gates 52 to 60 and the most significant bit of the delay circuit 51 are added, and after being delayed by the delay circuit 51 for a unit time, it is output, but at that time, the sign bit is " In the case of 0”,
That is, when a positive value is output from the delay circuit 51, all "0" data is applied to the B input terminals of the full adders 40 to 49, and
Data "0" is supplied to the adder 14 in FIG. Therefore, the adder 14 is a ROM
The coefficient data K given from is the direct data K' output. In that case, the coefficient K' from the gain coefficient control circuit 2 shown in FIG. 4 is directly provided as output data K'' to the multiplier 1. As shown, this is the case when this digital filter device is used as a normal low-pass filter, and the gain of its amplitude characteristic is also 1 (0 dB). ,
For example, when the coefficient _b2 of the transfer function H(Z) is controlled in order to make the amplitude characteristic peak at the cutoff frequency c (angular frequency ωc = 2πc), the overflow processing circuit 4 outputs a signal indicating an overflow. is supplied to the gain control circuit 13. Therefore, "-2 ^-8 (1-2 ^-1 )" is stored in full adders 40 to 49.
, i.e., the full adder 40 corresponding to the lowest bit.
, only the carry input terminal C is a "0" signal, and all "1"s are applied to the input terminals A of the full adders 40 to 49, and the data supplied from the input terminal B, for example, "0" is added. is performed and supplied to the delay circuit 51. Therefore, since the sign bit is output as "1" from the delay circuit 51, the AND gates 52 to
60 is opened, and as a result, the above-mentioned "-2 ^-8 (1-2 ^-1 )" is output to the adder 14 in FIG. As a result, the coefficient data K' is obtained, and the gain coefficient control circuit 2
is applied to multiplier 1 via . Furthermore, after the unit time has elapsed, the overflow processing circuit 4
Therefore, when a signal instructing overflow is applied to the gain control circuit 13, the output of the delay circuit 51 "-2 ^-8 (1-2 ^-1 )" and the currently supplied data "-2 ^-8 (1 -2 ^-1 )" are added by the full adders 40 to 49, and the resulting output "-2 ^-7 (1-2 ^-1 )" becomes the data supplied to the next adder 14. In this way, while the overflow processing circuit 4 outputs a signal instructing overflow, the adder 40
~49, the output value is sequentially decreased (that is, the absolute value is increased), and as a result,
It works to reduce the value of coefficient data K'' supplied to multiplier 1, lowering the overall gain of the filter.By decreasing coefficient data K'', the output of adder 3 increases above the dynamic range. When the value changes so as not to exceed the value, the output of the inverter 29 in the overflow processing circuit 4 becomes "0". Therefore, the full adders 40 to 40 in the gain control circuit 13
49 is now applied with a positive value "2 ^-10 " and is added to the output of the delay circuit 51. If the output value is negative, the above coefficient data K' is changed to the original coefficient. While setting the value to be smaller than the data K,
The value is gradually increased. Therefore, the gain of the filter increases. However, when the output of the delay circuit 51 becomes a positive value, the AND gates 52 to 60 are closed, so the output of the gain control circuit 13 becomes "0" and the adder 14
, the output data is greater than the input data K
Obtaining K′ is prevented. However, if the gain coefficient K is changed to a smaller value due to a change in the cutoff frequency c while the overflow instruction signal is being given to the gain control circuit 13 from the overflow processing circuit 4, the gain In the coefficient control circuit 2, when the data K' supplied from the adder 14 is positive, that is, when its most significant bit, the sign bit, is "0", the AND gates 61 to 67 are opened and the above input data is
K' is output as a coefficient K'', but when the data K' becomes "0", the output of the AND gate 77 is outputted via the OR gates 79 and 68. Therefore, the coefficient K'' is set to "2 ^-8 ". Also, if the above data K′ becomes a negative value,
The output of the inverter 80 becomes "0", the AND gates 61 to 67 are closed, and the OR gate 7
A "1" signal is outputted via the terminals 9 and 68. Also, the sign bit of coefficient K'' is forced to “0”.
Therefore, the output of this gain coefficient control circuit 2
K″ becomes “2 ^-8 ”. Therefore, a positive value is always applied to the multiplier 1 as coefficient data K'', making it possible to prevent filter oscillations, etc. Even when the gain coefficient is switched in this way, ,
The digital filter device is controlled so that it does not malfunction, and even when a resonance characteristic is added to the digital filter device as shown in FIGS. 6B and C, the maximum amplitude characteristic is the same as in FIG. 6A without the resonance characteristic. The value is controlled to always be 1, and the output level does not change. Although the above embodiment has been described with respect to a digital filter device whose transfer function H(Z) is given by equation (1), a general quadratic/quadratic digital filter device, that is, whose transfer function is given by H(Z) )=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 /1+b ₁ Z ^-1 +b ₂ Z ^-2
...The present invention can also be applied to a digital filter device given by equation (4). For example, in that case, in the _overflow processing circuit ₄ , the digital It becomes possible to prevent the absolute value of the output of the filter device from exceeding 1. In that case, the gain coefficient can be maintained at a positive value by performing the same operation in the gain coefficient control circuit 2. Further, in the present invention, the transfer function is H(z)=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 ...+a _n Z ^-m /1+b ₁ Z
Of course, the present invention can also be applied to a higher-order digital filter device expressed as ^-1 +b ₂ Z ^-2 ...+b _o Z ^-n . Furthermore, for one digital filter device,
When supplying coefficients from an external ROM to generate filters with various characteristics, the overflow processing circuit 4 calculates the maximum and minimum values from the coefficient data that determines the zero point of the transfer function.
A dynamic range is determined, and if the input data is within this dynamic range, the input data is the output of the overflow processing circuit 4, and if the input data is not within the dynamic range, the input data is correct. If the input data is a load, the maximum value calculated by the above calculation should be output, and if the input data is a load, the minimum value calculated by the above calculation should be output. At that time, if an overflow is detected, the above calculation will be performed. The gain control circuit 13 may be operated to lower the gain of the filter. In this case as well, the gain coefficient control circuit 2 can perform control in the same manner as described above so that the gain coefficient always takes a positive value. Furthermore, it goes without saying that the path positions in which the overflow processing circuit 4, the gain control circuit 13, and the gain coefficient control circuit 2 are provided can be variously changed as necessary. In addition, although the above embodiments apply the present invention to a digital filter device that operates by parallel computation, it goes without saying that the present invention can be applied to a digital filter device that operates by serial computation, and in that case. Of course, the configurations of the overflow processing circuit 4, the gain control circuit 13, and the gain coefficient control circuit 2 are suitable for serial calculation. In addition, when using the digital filter device according to the present invention, if the sampling frequency (which determines the unit time) is s according to Nyquist's sampling theorem, then the input signal of the filter is divided into frequency components of s/2 or more. It is even more effective to control the frequency component of the input signal of the filter at s/4 in relation to aliasing distortion. As described in detail above, in the digital filter device of the present invention, overflow processing is performed for the dynamic range of calculation, and when an overflow occurs, the gain coefficient of the filter is decreased, and By outputting data with the minimum positive value as the gain coefficient when the above-described gain coefficient becomes zero or negative, there is no need to set a wide dynamic range for the calculation in advance, and the data The upper bits can also be used effectively, and the number of bits of the input and output data of the digital filter device can be made equal, so connection to external devices is easy, and digital filter devices can be easily connected in cascade. In addition, waveform distortion can be greatly improved compared to a system that simply outputs the maximum or minimum value of the dynamic range from an overflow processing circuit at the time of overflow, and in that case, the gain coefficient is always maintained at a positive value. This prevents malfunctions such as oscillation of the digital filter device, and the output level of this digital filter device is always constant, so this digital filter device can be applied, for example, to electronic musical instruments or various types of audio equipment. Even in this case, the output volume can be kept constant. In addition, since the dynamic range of the digital filter device is determined in advance, it has the advantage that it is very effective for fixed-point arithmetic.

[Brief explanation of the drawing]

The drawings show an embodiment of the invention, FIG.
A circuit configuration diagram of this embodiment, FIG. 2 is a detailed diagram of the overflow processing circuit 4 of FIG. 1, FIG. 3 is a detailed diagram of the gain control circuit 13 of FIG. 1, and FIG. 4 is a detailed diagram of the gain coefficient control circuit. 2 and FIG. 5 are diagrams for explaining the operation of the overflow processing circuit 4, and FIG. 6 is a diagram showing the amplitude characteristics of the digital filter device of this embodiment. 1, 7, 9, 12... Multiplier, 2... Gain coefficient control circuit, 3, 6, 8, 10, 14... Adder,
4... Overflow processing circuit, 13... Gain control circuit.

Claims (1)

[Claims] 1. The transfer function is H(z)=K・1+a ₁ Z ^-1 +a ₂ Z ^-2 ...+a _n Z ^-m /1+b ₁ Z
^-1 +b ₂ Z ^-2 ...+b _o Z ^-n In a digital filter device, the signal at the input stage of the digital filter device has a positive or negative overflow with respect to a predetermined dynamic range. a detection means for detecting, when the detection means detects the positive overflow, outputs the maximum value of the dynamic range to the input stage of the digital filter device, and when the negative overflow is detected, the detection means outputs the maximum value of the dynamic range to the input stage of the digital filter device; , first control means for performing overflow processing by outputting the minimum value of the dynamic range to the input stage of the digital filter device; and when the detection means detects a positive or negative overflow, the transfer function a second control means for reducing the value of a gain coefficient K that determines the gain of the digital filter device and suppressing the signal at the input stage from continuously overflowing; and control of the second control means. detecting that the gain coefficient K reduced by has become zero or a negative value,
A digital filter device comprising: third control means for outputting a minimum positive value as the gain coefficient K. 2. Claims characterized in that the dynamic range is set based on a coefficient a _n (m=1, 2,...m) of the transfer function that determines the zero point of the transfer function of the digital filter device. The digital filter device according to item 1.