JPS6337981B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to time division multiple access communications (herein abbreviated as "TDMA") suitable for satellite communications. In particular, using the space diversity method
The present invention relates to a device for correcting timing differences that occur between signals transmitted from different antennas in the TDMA system.

In the TDMA system, signals transmitted from each TDMA terminal (earth station) are sent in the form of periodic continuous signals called bursts, and a repeater on the satellite transmits the burst-like signals arriving from each earth station. Transmission times must be controlled at each transmitting station so that they do not overlap with each other. For this reason, using a special synchronization signal (hereinafter abbreviated as "SUW") transmitted from an earth station called a reference station,
By defining a TDMA frame, assigning the burst array to be transmitted from each earth station to this TDMA frame, and monitoring and controlling the position of the synchronization signal (hereinafter abbreviated as "DUW") included in each burst. This enables the above control to be achieved.

When transmitting signals, the distance between each earth station and the satellite changes from moment to moment due to the movement of the satellite.
Each earth station transmits the burst DUW that it transmits.
The relative relationship of SUWs is monitored, and the transmission timing is controlled as necessary so that this relationship is determined. This control is called burst synchronization.

In addition, each earth station receives the SUW and synchronizes its receive frame counter, which is the standard for signal reception, with the value of this frame counter and the value of each burst.
Receives signals based on DUW.

In the space diversity method, in order to improve the reliability of communication, one earth station has multiple transmitting and receiving antennas, receives signals transmitted from the same satellite with multiple antennas, and compares the quality of the received signals. This method processes signals of good quality as received signals, and similarly transmits the own station's transmission signal from the antenna with the best communication condition.

Regarding the processing of the received signal for this purpose,
Since it is not directly related to the present invention, detailed explanation will be omitted.

The main cause of decreased communication reliability is radio wave attenuation due to rainfall, and to overcome this, antennas are installed so that the correlation with rainfall intensity is sufficiently small. For this reason, the two antennas must be separated by about 10 to 30 km. Such a difference in the antenna positions causes a non-negligible difference in the propagation delay time between the satellite and each antenna. In addition, the propagation delay time changes due to the movement of the satellite, which varies for each antenna.

For example, if a geostationary satellite moving ±0.5° north-south and ±1.0° east-west is located at 0°E, 0°N, then the antenna at 40°E, 50°N and the antenna 30 km away in a straight line distance The difference in propagation delay time between
~22.5Km corresponds to a time of 0 to 75μsec. Assuming that the maximum value of the variation is ±570 m, this corresponds to ±1.9 μsec.

On the other hand, the bit rate currently used in various TDMA systems is 30MHz to 120MHz, and when digitally correcting the delay time difference mentioned above, the fixed delay to correct the fixed difference is 75 × 10 ^-6 _sec × A variable delay of 2 x 1.9 x 10 ^-6 _sec x 120 x 10 ⁶ Hz = 456 bits is required to correct the variation of 120 x 10 ⁶ Hz = 9000 bits. This can be achieved with IC memory. A transmission route length equalization device is created by integrating the control circuits to synchronize the timing of the transmission signals so that the signals transmitted from two or more antennas arrive at the communication satellite at the same time by controlling the fixed delay, variable delay, and variable delay. It is called.

FIG. 1 shows a block diagram of a TDMA terminal station with a conventional diversity configuration. Here, the signals transmitted and received from the two antennas are called route 1 and route 2, respectively. The circuit shown with a double frame in Figure 1 is
Configure a transmission route length equalizer.

At the bottom right of FIG. 1, a received signal 101 and a regenerated burst clock 102 received from route 1 through a demodulation circuit 14 are input to an elastic clock converter 10 and converted into a continuous system clock. . In the elastic clock converter, in order to keep the delay time during conversion operation within a certain value for each burst, the state of the memory is reset by the reset pulse generating circuit 13 immediately before each burst DUW. The received data converted into a continuous clock is sent to the fixed delay circuit 1.
1, the fixed difference in propagation delay time between routes 1 and 2 is compensated, and the SUW detection circuit 12
and is input to the reception switching control circuit 31.

On the other hand, the received signal 111 and the burst clock 11 received from the route 2 through the demodulation circuit 24
2 is input to an elastic clock converter 20 and converted into a continuous system clock. The elastic clock converter 20 is
The reset pulse generating circuit 23 resets the state of the memory immediately before the DUW of each burst.

The received data converted into a continuous clock is input to the variable delay circuit 21, and the variation in propagation delay time of routes 1 and 2 is compensated for.
SUW detection circuit 22 and reception switching control circuit 31
is input. Two SUW detection circuits 12 and 22 detect SUW from data 104 and 114 received through route 1 and route 2, respectively, and input detection pulses 103 and 113 to symbol phase difference detection circuit 30. When detecting SUW, in order to avoid error detection due to a pattern that is the same as SUW included in the data, once SUW is detected, ±3 bits before and after this are centered on a timing one frame apart from here. 7
Only the SUW detection signal that passes through the bit-width gate is considered to be the correct SUW detection signal. This 7-bit wide gate is called an aperture. In some systems, the width of this aperture is not 7 bits, but a slightly different value may be used. The symbol phase difference detection circuit 30 measures the interval between two input pulses, and uses the variable delay circuit 2 to cancel the interval.
By increasing or decreasing the delay amount of 1, the data 104 and 11
4 is controlled to be input to the changeover switch 31 with an error within ±1 symbol. Furthermore, if SUW is not detected on either route, the variable delay circuit is controlled to be fixed at the delay amount at that time.

If data passing through Route 2 is used as received data, moving the variable delay circuit rapidly may cause data to be lost.
In order to eliminate this, it is desirable to control one symbol per frame. Data 104 and 114 in which the difference in reception timing has been corrected in this way
is input to the reception switching control circuit 31.

Also, it was detected from route 1 and route 2.
Based on SUW, received frame pulses 105, 115 indicating the beginning of the frame of each route,
118,1 indicates that SUW is being received at a rate above a certain standard on route 1 and route 2.
19 and a signal 116 indicating that the timing difference between routes 1 and 2 is within a certain range, for example within ±3 symbols, is sent to the reception switching control circuit 3.
1 is input. The reception switching control circuit compares the reception status of the SUW of each route or the reception status of the error measurement burst, and outputs the data of the route with the better reception status as reception data 121 to the reception control circuit 32 and the LUW detection circuit 34. , outputs the reception frame pulse 122 of the same route to the reception timing generation circuit 33.

The reception timing circuit 33 resets the frame counter with the selected reception frame pulse 122, defines this as the beginning of the frame, and sets the reception timing 129, the data burst UW reference position pulse 125, and the data burst wide aperture 12.
6. Output the preliminary burst UW reference position pulse 127 and the preliminary burst wide aperture 128. Here, the data burst UW reference position pulse 125 is a synchronization signal (hereinafter abbreviated as "data burst LUW") included in the data burst transmitted by the local station with reference to the reception frame pulse 122.
is a pulse indicating the reference position from which the signal is received.

The data burst wide aperture 128 is a pulse that indicates the approximate timing in which the data burst LUW is always received, and is usually located around the data burst UW reference position pulse 125.
This is a pulse with a width of about 10 μs. The preliminary burst UW reference position pulse 127 is a synchronization signal (hereinafter referred to as “preliminary burst
Abbreviated as "LUW". ) is a pulse indicating the received reference position. Preliminary burst wide aperture 12
8 is a pulse indicating the approximate timing in which the preliminary burst LUW is always received, and is usually a pulse having a width of about 10 μs around the preliminary burst UW reference position pulse 127. The reception control circuit 32 decodes the reception timing 129, descrambles, separates or decodes the reception data 121, and distributes it as a reception signal.

The LUW detection circuit 34 detects a synchronization signal (hereinafter referred to as "LUW") within the own station's transmission burst from the received data 121.
It is abbreviated as ) and outputs the LUW detection pulse 124.

The aperture generation circuit 41 knows which of route 1 or route 2 the data burst and backup burst are being transmitted from the transmission selection signal 123 output from the transmission switching control circuit 44, and determines whether the data burst is transmitted to route 1 or not. If so, route the data UW reference position pulse 125.
The LUW detection pulse 124 is outputted as a 1UW reference position pulse 132, and the LUW detection pulse 124 input at a timing overlapping with the data burst wide aperture 126 is outputted as a route 1UW detection pulse 131. In this LUW detection, the
To avoid false detection due to a pattern equal to LUW, once LUW is detected,
Only the LUW detection pulses that pass through a 7-symbol-width gate of ±3 symbols before and after the timings separated by frames are considered to be correct LUW detection pulses. This 7-bit wide gate is called an aperture, and depending on the system, a slightly different value may be used instead of 7-bit wide. Appropriate apertures are used for each LUW detection below.

When the preliminary burst is sent to route 1, the preliminary burst UW reference position pulse 127 is output as the UW reference position pulse 132 of route 1, and the LUW detection pulse is input at a timing that overlaps with the preliminary burst wide aperture 128. 12
4 is output as the route 1 UW detection pulse 131.

Also, it is determined whether the burst being sent to route 2 is a data burst or a preliminary burst, and depending on the burst being transmitted in the same way, data burst reference position pulse 125 or preliminary burst reference position pulse 127 is is outputted to the variable delay control circuit as a UW reference position pulse 143,
The LUW detection pulse 124 inputted at a timing overlapping with the data burst wide aperture 126 or the preliminary burst wide aperture 128 is outputted to the variable delay circuit 43 as the UW detection pulse 141 of route 2.

Further, the aperture generation circuit 41 has a timer for controlling the transmission timing, and when the timing to perform the transmission timing control comes, it first outputs a pulse to the burst synchronization timing signal 133 and outputs a pulse to the transmission timing control circuit 42 to generate a burst signal. The synchronization is executed, and the end of the burst synchronization is known by the burst synchronization end signal 134. Next, a pulse is output to the variable delay control timing signal 143 to cause the variable delay control circuit 43 to correct the delay amount 152 of the variable delay. The end of the correction of the delay amount of the variable delay is known from the variable delay control end signal 144, the transmission timing control timer is reset, and the next burst synchronization timing signal 133 is sent after the return delay time from this point to the satellite has elapsed. Output.

The transmission timing control circuit 42 has a transmission frame counter that defines the transmission timing, and when a pulse is input to the burst synchronization timing signal 133 from the aperture generation circuit 41, the transmission timing control circuit 42 outputs the route 1UW.
The timing difference between the detection pulse 131 and the route 1 UW reference position pulse 132 is counted by the system clock, and this timing difference is output as the route 1 timing difference 135, and only an appropriate frame is counted to cancel out this timing difference. By changing the period of the transmission frame counter by ±1 symbol, the frame length is changed by +1 symbol or -1 symbol, and the transmission timing is corrected at a rate of 1 symbol per frame. The output of the transmission frame counter is always outputted as transmission timing 151. When the correction of the transmission timing, that is, the burst synchronization is completed, the transmission timing control circuit sends a burst synchronization end signal 134.
A pulse is output to inform the aperture generating circuit 41 that burst synchronization has ended.

When the variable delay control circuit 43 inputs a pulse to the burst synchronization timing signal 133 from the aperture generation circuit 41, the variable delay control circuit 43 outputs the UW detection pulse 1 of the route 2.
41 and the UW reference pulse 142 of route 2 is counted by the system clock, and this timing difference is stored as E2. At the same time, route 1 timing difference 135 is stored as E1. Next, when a pulse is input from the aperture generation circuit 41 to the variable delay control timing signal 143,
Assuming that E2-E1 is an error caused by an inappropriate delay amount of the variable delay, the delay amount 152 of the variable delay circuit is corrected at a rate of one symbol per frame to cancel this error. For example, if the current delay amount is M, the delay amount D will be increased or decreased by 1 until it becomes D=M-(E2-E1). When the delay amount has been corrected in this way, a pulse is output to the variable delay control end signal 144 to notify the aperture generating circuit 41 that the delay amount control has ended.

Furthermore, if the root 2UW detection pulse 141 is not input when a pulse is input as the synchronization timing signal 133 from the aperture generation circuit 41, the delay amount 117 of the variable delay circuit on the receiving side
is output as the delay amount 152 of the variable delay circuit on the transmitting side.

The transmission control circuit 51 controls the signal to be transmitted at an appropriate timing based on the transmission timing 151.
Performs PCM encoding, multiplexing, addition of a synchronization signal, scrambling, etc., and outputs burst-shaped transmission data 161. At the same time, a carrier-on data burst signal 162 indicating the timing to transmit as a data burst and a preliminary burst are output. A carry-on preliminary burst signal 163 indicating the timing of transmission and a clock are output to the transmission switching control circuit.

The transmission switching control circuit 44 routes the transmission data 161 to route 1 and route 2, and transmits the transmission data 171 and 181.
It is output together with clocks 173 and 183 as .
It also compares the LUW reception status of the data burst and backup burst, or the reception status of the error measurement burst, and determines which route the data burst should be sent to. converts the carrier-on data burst signal 162 to the carrier-on route 1 signal 17
When transmitting a preliminary burst, the carrier-on preliminary burst signal 163 is output as the carrier-on route 1 signal 172.

Similarly, the appropriate carrier-on signal is sent to route 2 by burst to send to route 2.
Output to signal 182. At the same time, it outputs a transmission selection signal 123 indicating which route the data burst is being transmitted. This determination of the transmission route is performed when a pulse is output to the variable delay control end signal, and is performed only once in the transmission timing correction period.

The fixed delay circuit 45 applies a preset fixed amount of delay to the transmission data 171 and the carrier-on-route 1 signal 172, and outputs it as the transmission data 174 and the carrier-on-route 1 signal 175. The modulation circuit 47 receives this signal and outputs a modulated output 177 modulated by the transmission data 174 only while the carrier-on-route 1 signal 175 is 1, and this is supplied to the route 1 antenna.

The variable delay circuit 46 delays the transmission data 181 and the carrier-on-route 2 signal 182 by a delay amount of 152.
The transmission data 18 is delayed by the delay amount determined by
4. Output as carrier on route 2 signal 185. The modulation circuit 48 inputs this signal and outputs a modulated output 187 modulated by the transmission data 184 only while the carrier-on-route 2 signal 185 is 1, and this is supplied to the route 2 antenna.

In this conventional device, when a data burst is transmitted on route 1 and a backup burst is transmitted on route 2, even if the backup burst cannot be detected, the delay amount of the variable delay circuit on the receiving side is By using it as a delay amount in a delay circuit, the timing of the preliminary burst could be maintained at a fixed position. However, if a backup burst cannot be detected when transmitting a backup burst to route 1 and a data burst to route 2, there is no way to control the burst synchronization circuit from the transmission/reception variable delay control circuit. It is necessary to maintain the synchronization of the data bursts by changing the delay amount of the transmission variable delay circuit in response to any deviation from the reference position of the data bursts transmitted from No. 2. However, in this case, the deviation of the data burst must be corrected by dividing it by the delay amount of the burst synchronization circuit and the transmission variable delay circuit, so the position of the preliminary burst is not necessarily guaranteed to be at the reference position. ran out and had to stop sending backup bursts.

In addition, if the communication condition of route 1 improves after this state continues for a long time, when the burst synchronization circuit corrects the timing difference of route 1 that has been accumulated up to that point, the data burst of route 2 will also be If a correction of ±3 bits or more is made and there is an error that goes outside the aperture, data burst transmission is temporarily stopped and the data burst transmission is stopped to prevent interference with other stations. , it has no choice but to start transmitting data bursts again after the synchronization state of route 2 becomes good. In this case, there was a drawback that data transmission was interrupted once.

Furthermore, due to the above-mentioned drawbacks, starting communication from the route 2 side has little meaning and could not be considered. Therefore, route 2 must be treated as a preliminary route, and the diversity effect will not be sufficiently enhanced.

In addition, in the conventional method, when transmitting data bursts from route 2, the data bursts are moved not only when performing burst synchronization but also when modifying the delay amount of the transmission variable delay circuit, which is undesirable. It was considered that.

Regarding the conventional method, "Satellite communication TDMA
There is a detailed description in "Synchronization in Space Diversity" (IEICE Technical Report CS76-101, September 28, 1976).

The present invention improves these drawbacks by allowing communication to be started from either route 1 or route 2, and when transmitting a data burst on route 2, the backup burst on route 1 is transmitted. Even if detection is no longer possible, if both routes 1 and 2 are being received on the receiving side, the timing of the preliminary burst is maintained at the reference position by referring to the delay amount of the variable delay circuit on the receiving side, and diversity is maintained. The purpose is to provide a device that can fully demonstrate the effects of.

In the present invention, the timing error from the reference position of the LUW detected from the data burst transmission route is always corrected by the burst synchronization circuit, and then the delay amount of the transmission variable delay circuit is corrected. When transmitting to a route that passes through a circuit, when increasing the delay amount of the transmission variable delay circuit by K symbols every frame, at the same time the transmission timing of the burst synchronization circuit is advanced by K symbols,
When reducing the delay amount of the transmission variable delay circuit by K symbols per frame, by simultaneously delaying the transmission timing of the burst synchronization circuit by K symbols,
It is characterized in that the delay amount is changed without changing the timing of the data burst on the satellite.
The above K is usually selected to be "1", but it can also take a larger value. In the following explanation, an example in which K is selected as "1" will be explained.

According to the present invention, it becomes possible to treat route 2, which conventionally had to be considered as a preliminary route, as being equivalent to route 1. Further, when the data burst is passed through route 2, which has been considered undesirable in the past, it is possible to avoid shifting the data burst when modifying the delay amount of the variable transmission delay.

First, an overview of the operation of the present invention will be explained with reference to FIG. 1 in FIG. 2 indicates received data, a indicates a data burst, and b indicates a preliminary burst. 2 is data burst UW detection pulse, 3 is data burst
UW reference position pulse, 4 indicates preliminary burst UW detection pulse, and 5 indicates preliminary burst UW reference position pulse. E _D indicates a data burst transmission timing error, and E _S indicates a preliminary burst transmission timing error.

The transmission timing error is defined so that the direction of delay from the reference position is expressed as a positive number. Further, the transmission timing error of the burst transmitted through route 1 is defined as E1, and the transmission timing error of the burst transmitted through route 2 is defined as E2.
At this time, the burst synchronization circuit corrects E1 when burst synchronization and transmission variable delay control are completed,
The transmission variable delay circuit only needs to correct E2-E1.

1. The data burst is transmitted through route 1, that is, through a fixed delay circuit, and the LUW of both the data burst and the preliminary burst can be detected,
If SUW can be detected on at least one route.

In this case, E1=E _D E2=E _S. Therefore, the burst synchronization circuit controls to correct the _ED , that is, to advance the _ED symbol transmission timing. The transmission variable delay circuit is controlled to correct E2-E1 = E _S - E _D , that is, to reduce the E _S - E _D symbol delay amount.

2 send a data burst through route 1;
Preliminary burst LUW cannot be detected, but SUW
is when both routes 1 and 2 can be detected.

The burst synchronization circuit compensates for _ED . The transmission delay circuit is controlled to match the delay amount of the reception delay circuit. This is the amount of delay in the transmission delay circuit.
When D _T is the delay amount of the reception delay circuit and D _R is the delay amount of the reception delay circuit, the fact that D _T −D _R ≈E2−E1 is established is utilized.

3 send a data burst through route 1;
When the backup burst LUW cannot be detected and the SUW is only detected on either route 1 or route 2.

In this case, it cannot be said that the delay amount of the receiving variable delay circuit has been corrected correctly, so the burst synchronization circuit only corrects E1 = E _D , and the delay amount of the transmitting variable delay circuit is the same as the previous value. maintain, and stop sending preliminary bursts.

4 send a data burst through route 1;
When both data burst and backup burst LUWs are detected, but SUW is not detected on either route 1 or route 2.

The burst synchronization circuit does not perform any correction. The transmission variable delay circuit corrects E2 - E1 = E _S - E _D. This corresponds to a case where SUW cannot be received on both routes 1 and 2 when the reference station is replaced, and if this state continues for a certain period of time or more, transmission will be temporarily stopped.

5 send a data burst through route 2;
LUW for both data burst and reserve burst
can be detected and at least one SUW can be detected.

a First, the data burst transmission timing error E _D =E2 is corrected by the burst synchronization circuit.

b Next, the delay amount of the transmission variable delay circuit is corrected by E _D - E _S = E2 - E1, and at the same time, the burst synchronization circuit corrects E _S - E _D = E1 - E2. That is, if E _D −E _S is positive, then
The variable transmission delay amount is decreased by one symbol per frame during E _D - E _S frames, the frame length is increased by one symbol during this period, and if E _D - _{E S} is negative, every frame during E _D - E _S frames. The transmission variable delay amount is increased symbol by symbol, and the frame length is shortened by one symbol during this period. As a result, the burst synchronization circuit corrects E _D + (E _S − E _D ) = E2 + (E1 − E2) = E1, and the transmission variable delay circuit corrects E _D − E _S = E2 − This means that only E1 has been corrected. The timing of the data burst changes on the satellite only in case a) above.

6 A preliminary burst is sent to route 1, a data burst is sent to route 2, and the LUW of the data burst is
However, SUW is detected in both route 1 and route 2.

c First, the data burst transmission timing error E _D =E2 is corrected by the burst synchronization circuit.

d Next, the delay amount of the transmission variable delay circuit is D _T −D _R
Correct only. Here, D _T −D _R ≒E2−E1=E _D −E _S. At the same time, the burst synchronization circuit allows D _R −D _T
Correct. Here, D _R −D _T ≒E _S −E _D =E1−E2. This corresponds to controlling the delay amount of the transmission variable delay to be equal to the delay amount of the reception variable delay, and at the same time controlling the burst synchronization circuit so that the data burst timing does not change on the satellite. Actual control is performed one symbol per frame as in 3 above.

7 When a data burst is sent to route 2, only the LUW of the data burst is detected, and the SUW is also detected only on either route 1 or route 2.

In this case, it cannot be said that the delay amount of the reception variable delay circuit has been corrected correctly, so the burst synchronization circuit only corrects E _D =E2 and stops transmitting the preliminary burst.

8 send a data burst through route 2;
LUW of both data burst and backup burst can be detected, but SUW is not detected on either route 1 or route 2.

The delay amount of the transmission variable delay circuit is corrected by E _D - E _S = E2 - E1, and at the same time, the burst synchronization circuit corrects E _S - E _D = E1 - E2. The burst synchronization circuit alone is not controlled. As a result, on the satellite, the position of the data burst does not move and the position of the preliminary burst is E _D
−ES It will be shifted to the back of _{the S} symbol. This state also corresponds to the case of reference station replacement, and if this state continues for a certain period of time or more, transmission will be temporarily stopped.

When performing an acquisition, the steps are as follows.
In this case, it is assumed that the approximate timing is known by a method such as prediction.

A: When performing an acquisition using route 1.

A known approximate timing is set in the burst synchronization circuit, a burst for acquisition corresponding to a data burst is transmitted from route 1, this LUW is detected, synchronization is established, and transmission of the data burst is started. Next, after confirming that SUW is being received on both routes 1 and 2, the delay amount of the transmission variable delay circuit is controlled using the method described in 2 above, and the difference between D _R and _DT is kept at a constant value. (for example, 3 symbols), then send a preliminary burst to route 2. Subsequent synchronization is maintained according to 1) above.

B When performing an acquisition using route 2.

The delay amount of the transmission variable delay circuit is set to a constant value, and the approximate timing with necessary corrections is set in the burst synchronization circuit using this value, and the acquisition burst corresponding to the data burst is transmitted from route 2. And this
Detects the LUW, synchronizes using the burst synchronization circuit, and starts transmitting data bursts. Next, according to 6 above, the preliminary burst is transmitted to route 1 after the difference between the delay amount of the transmission variable delay circuit D _R and _DT becomes less than a certain value (for example, 3 symbols). Subsequent synchronization will be maintained according to 6) above.

Next, the operation of one embodiment of the present invention will be explained using FIGS. 3 and 4.

FIG. 3 is a block diagram of a TDMA terminal station with a diversity configuration using a transmission route length equalizer according to an embodiment of the present invention. The circuit shown with a double frame in FIG. 3 constitutes a transmission route length equalization device.

In FIG. 3, 210, 220 are demodulation circuits, 211,
221 is an elastic clock converter, 2
12 is a fixed delay circuit, 222 is a variable delay circuit, 2
14, 224 is a reset pulse generation circuit, 21
3, 223 is a SUW detection circuit, 230 is a symbol phase difference detection circuit, 231 is a reception switching control circuit, 2
32 is a reception control circuit, 233 is a reception timing generation circuit, 234 is a LUW detection circuit 240 is a synchronization control circuit, 241 is an aperture generation circuit, 242 is a transmission timing and transmission variable delay control circuit, 24
3 is a transmission switching control circuit, 244 is a fixed delay circuit,
245 is a variable delay circuit, 251 is a transmission control circuit,
252, 253 are modulation circuits, 300, 310 are received signals, 301, 311 are demodulated data, 302,
312 is a reception clock. Reference numerals 304 and 314 indicate data that has been read as a system clock and has undergone timing correction, 303 and 313 indicate SUW detection pulses, and 305 and 315 indicate route 1 and route 2 reception frame pulses. Reference numerals 306 and 316 indicate SUW synchronization signals indicating that SUW is detected at a detection rate equal to or higher than the reference detection rate on route 1 and route 2.
317 is the delay amount of the reception variable delay circuit, and 318 is a reception variable delay circuit synchronization signal indicating that the timing difference between the data on route 1 and route 2 has been corrected to a reference amount or less. 321 is the received data selected by the reception switching control circuit, 322 is the reception frame pulse selected by the reception switching circuit, 323 is the reception timing, 324 is the data burst UW reference position pulse, 325 is the data burst wide aperture, 326 is a preliminary burst UW reference position pulse, 327 is a data burst wide aperture, 328 is a LUW detection pulse, 329 is received data, 330 is a reception route selection signal 331 is a data burst synchronization indication signal, 332 is a preliminary burst synchronization indication signal, 333 is the data burst UW detection pulse, 335 is the preliminary burst UW detection pulse,
342 is an acquisition timing signal, 343 is a burst synchronization start pulse, 344 is a burst synchronization display signal, 345 is a transmission variable delay control start signal,
346 is a transmission variable delay control display signal, 347 is a mode selection signal, and 348 is a transmission switching timing signal. 351 is a transmission frame pulse, 352 is a transmission timing, 354 is a transmission route selection signal 3
60,361,365,371,368,374
is the transmission data, 362 is the data burst carry-on signal, 363 is the preliminary burst carry-on signal, 384 is the acquisition burst carry-on signal 364, 367, 370, 373, 376 is the system clock, 366, 372 is the route 1 carry-on signal , 369, 375 are route 2 carry-on signals, 377 are route 1 transmission signals, 37
8 indicates a route 2 transmission signal 381 is an acquisition burst transmission signal, 382 is a data burst transmission signal, and 383 is a preliminary burst transmission signal.

If all the system clocks were written in Figure 3, the diagram would become complicated and difficult to understand, so only the important parts along the data flow are shown, and the others are omitted. The part surrounded by the two-dot chain line in FIG. 3 shows the circuit installed near the diversity antenna. Signals exceeding this two-dot chain line are transmitted to the diversity antenna by wire or wirelessly. At this time, the system clock is shown by a dotted line because if the data is scrambled and descrambled, it can be reproduced at the receiving end without being transmitted, so there may be cases where it is not transmitted.

The characteristic circuits of the present invention in FIG. 3 are a synchronization control circuit 240, an aperture generation circuit 241, a transmission timing and transmission variable delay control circuit 242, and a transmission switching control circuit 243. Since the circuits other than this are the same as those of the conventional system, repeated detailed explanations will be omitted.

Aperture generating circuit 241 operates as follows. data burst UW reference position pulse 324,
and preliminary burst UW reference position pulse 326
are signals indicating reference positions at which LUWs included in data bursts and preliminary bursts transmitted by the own station are received, with reference to the reception frame pulse 322, respectively, and are used within this circuit, as well as for transmission timing and transmission variable delay control. It is output to circuit 242. In this circuit, for the LUW detection pulse 328 input in the data burst wide aperture 325, an aperture with a width of 7 symbols, ±3 symbols before and after this, is created centered at a timing one frame away from the LUW detection pulse 328. Only the input LUW detection pulse 328 is outputted to the transmission timing and transmission variable delay control circuit 242 as a data burst UW detection pulse 333.

In addition, the data burst UW reference position pulse 32
4 as the center, create an aperture with a width of 7 symbols of ±3 symbols, count the number of detected LUW detection pulses input in this aperture, and calculate the number of detected LUW detection pulses that exceed a certain standard.
When the LUW detection pulse is input, the data burst synchronization display signal 331 is set to "1" indicating that the data bursts are synchronized. If out of synchronization, it is set to "0". The criteria for this LUW synchronization judgment is that if the LUW detection pulse enters the aperture for 5 consecutive frames, it is considered to be synchronized, and if the LUW detection pulse does not enter the aperture for 5 consecutive frames, it is assumed that the LUW detection pulse enters the aperture. is often used as a criterion for being out of synchronization.

Similarly, the preliminary burst wide aperture 327
For the LUW detection pulse 328 input within
A 7-symbol width aperture is created, and the LUW detection pulse that has entered the aperture is output as a preliminary burst UW detection pulse 335 to the transmission timing and transmission variable delay control circuit 242. At the same time, a 7-bit wide aperture is created around the preliminary burst UW reference position signal 326, and the input signal is
Count LUW detection pulses and create data burst LUW
The synchronization is determined using the same criteria as in the above, and if the synchronization is achieved, the preliminary burst synchronization display signal 332 is set to "1", and if the synchronization is out of synchronization, the preliminary burst synchronization display signal 332 is set to "0".

Synchronization control circuit 240 and transmission switching control circuit 2
43 operates as follows. First, if the transmitting side is completely out of synchronization, an acquisition will be performed. When performing an acquisition, the root
Refer to the 1SUW synchronization signal and the root 2SUW synchronization signal, and do not start acquisition unless at least one of them is in a synchronized state. If at least one side is synchronized, refer to the transmission route selection signal 354, output the acquisition timing signal 342 at an appropriate timing depending on the transmission route, reset the transmission frame timing,
Decide on the sending timing.

Next, the acquisition burst transmission signal 381 is set to "1" to start transmission of the acquisition burst. That is, the transmission switching control circuit 243 outputs an acquisition burst carry-on signal 384 to the carry-on signal of the route selected by the transmission route selection signal. The carry-on signal of the unselected route is always in a state in which no burst is transmitted. Transmission route selection signal 354
refers to the preliminary burst synchronization indication signal 332,
If the preliminary bursts are not synchronized, the reception route selection signal 330 is output as is. Therefore, since the preliminary bursts are not synchronized at the time of acquisition, the transmission route is determined by the reception route selection signal, and transmission is performed on the route with good reception conditions. In this way, acquisition bursts are transmitted to routes with good reception conditions. As the acquisition burst, a preamble burst, which is a data burst with the data portion removed, is usually used.

Next, after the satellite round-trip delay time (approximately 0.3 seconds) has elapsed since the start of transmission of the acquisition burst, a burst synchronization start pulse 342 is output, and the burst synchronization circuit corrects the transmission timing of the acquisition burst. . The transmission timing and variable delay control circuit 242 sets the burst synchronization display signal 344 to "1" while the transmission timing is being corrected. After the burst synchronization display signal 344 returns to "0" and the satellite round trip delay time (approximately 0.3 seconds) has elapsed, monitoring of the data burst synchronization display signal 331 is started, and if the data burst becomes out of synchronization, , temporarily stop sending the acquisition burst and start over from the beginning. After this, if the data burst is normally synchronized, the acquisition burst transmission signal 381 is returned to "0" and at the same time,
Data burst transmission is started by setting the data burst transmission signal 382 to "1", and thereafter, the burst synchronization is performed every time the satellite round trip delay time (approximately 0.3 seconds) passes after the burst synchronization display signal 344 returns to "0". One pulse is output as the start pulse 342 to perform burst synchronization and maintain normal data burst transmission timing.

After this, when performing variable transmission delay control (described later), a pulse is output to the variable transmission delay control start signal 345 immediately following burst synchronization to control this variable transmission delay circuit, and the variable transmission delay control is performed. The next burst synchronization start signal 343 is output after the transmission variable delay control display signal 346 indicating that the synchronization is being performed returns to "0" and the satellite round trip delay time has elapsed.

After the data burst is synchronized in this way, the SUW synchronization signal 3 of route 1 and route 2
06, 316 and the reception variable delay circuit synchronization signal 318, and if all three signals are synchronized, the mode selection signal 3 is output following burst synchronization.
47 as "0" to refer to the delay amount of the receiving variable delay circuit, and transmitting variable delay control start signal 345.
Outputs a pulse to. As a result, the transmission timing and transmission variable delay control circuit 342 corrects the delay amount 353 of the transmission variable delay circuit at a constant speed for each frame so that it becomes equal to the delay amount 317 of the reception variable delay circuit. In this way, if the delay amounts of the transmitting and receiving variable delay circuits are made equal, only a slight difference in timing between the preliminary bursts remains due to the delay difference in the transmission path of the transmitted and received data to the diversity antenna.

Next, the preliminary burst transmission signal 383 is set to “1”.
Then, a backup burst carry-on signal 363 is output to the carry-on signal of the route that is not transmitting data or bursts, and transmission of the backup burst is started. After this, the mode selection signal is set to "1" so that control is performed using the preliminary burst UW detection pulse. After the satellite round trip delay time (approximately 0.3 seconds) has elapsed, the burst synchronization display signal 344 returns to "0", and then the transmission variable delay control start signal 345 is output.

From the time of performing the second transmission variable delay control, the preliminary burst synchronization synchronization display signal 332 is monitored, and in the event of synchronization, the mode selection signal is returned to "0" and the delay amount of the transmission variable delay circuit is variable for reception. Let it be the delay amount of the delay circuit.

If the preliminary bursts are synchronized, even if the data bursts become out of synchronization, transmission switching is performed and relief is provided, so there is no return to acquisition. Further, the control to make the transmission variable delay circuit equal to the delay amount of the reception variable delay circuit is performed by the SUW synchronization signals 306, 316 of route 1 and route 2, and
This process is not performed unless all of the reception variable delay circuit synchronization signals 318 are in a synchronized state.

Also, when the reference station is replaced, the SUW loses synchronization on both routes 1 and 2. At this time, it stops outputting pulses to the burst synchronization start signal 343 and does not perform burst synchronization, but the LUW detects both data bursts and preliminary bursts. If it is possible,
A pulse is output as the transmission variable delay control start signal 345, and only the timing of the preliminary burst is corrected.

After the preliminary burst synchronization display signal 332 becomes synchronized, the transmission switching control circuit determines the transmission route by detecting the LUW detection state of the data burst, the preliminary burst, or the receiving state of each error measurement burst. The result is output as the transmission route selection signal 354, and the carry-on signals 366, 36 of route 1 and route 2 are output.
9, a data burst carry-on signal 362 or a preliminary burst carry-on signal 363 is output to select a transmission route. The switching of the transmission route is performed at the timing when the transmission timing control is completed by the transmission switching timing signal 348 outputted by the synchronization control circuit 240.

Next, the operation of the transmission timing and transmission delay control circuit 242 will be explained using FIG.

In FIG. 4, signals input and output from the outside to this circuit are given the same numbers as in FIG. 3. Although the system clock is omitted in FIG. 3, it is designated by the reference numeral 501 in FIG.

In FIG. 4, 401 is a transmission frame counter, 402 is a data burst time difference counter, 4
03 is a preliminary burst time difference counter 404, 40
5 is a latch and arithmetic circuit, 406 and 407 are selectors, 408 is a presettable down counter, 409 is a decoder, 410 is a delay counter,
411 is a comparison circuit 421 is an AND gate, 422
indicates an OR gate, and 423 indicates an inverter.

First, the operation when a pulse is input to the burst synchronization start signal 343 will be described.

When a pulse is input to the burst synchronization start signal 343, it is input to the data burst time difference counter 402, the preliminary burst time difference counter 403, and the latch and calculation circuit 405. The data burst time difference counter uses data bursts with the burst synchronization display signal 344 set to "1".
UW detection pulse 333 and data burst UW
The system clock 501 counts the timing difference between the reference position pulses 324 and outputs the result including the sign as the data burst timing difference 504, and at the same time outputs the strobe pulse 505.

The timing difference of this data burst is explained above.
Equivalent to E _D. A positive value of _ED indicates that the data burst lags behind the reference position by _ED symbols. Also, the fact that E _D is a negative value means that
Indicates that the data burst is ahead of the reference position by _ED symbols. Transmission frame counter 401
is an up counter that counts the system clock 501, and usually counts from 0 to N, assuming the length of one frame to be N+1 symbols. Transmit frame pulse 357 when counter value is 0
When the counter value is N-1, a pulse with a width of one symbol is outputted to the output line 522. Furthermore, when a 1-bit width pulse is added to the acquisition timing signal 342, this pulse causes the contents of the counter to become "0". This determines the transmission timing at the time of acquisition.

Also, if N-1, that is, 523 is "1",
This counter becomes "0" when counting up to N-1.
When N+1, that is, 524 is "1", it counts up to N+1 and returns to "0".

After outputting the data burst timing difference E _D , the data burst time difference counter 402
If this value E _D is positive, the output 502 is set to "1" and the input 522 is counted to keep the output 502 at "1" during the E _D frame. As a result, the transmitted frame is shortened by one symbol during the E _D frame,
The transmission timing is earlier by the _ED symbol.

If _ED is negative, the output 503 is similarly kept at "1" during the _ED frame, the transmission frame is lengthened by one symbol during this period, and the transmission timing is delayed by the _ED symbol. After correcting the data burst transmission timing difference in this way, the burst synchronization display signal 3
44 is returned to "0".

The reserve burst time difference counter is the reserve burst time difference counter.
The system clock 501 counts the timing difference between the UW detection pulse 333 and the preliminary burst UW reference position pulse 326, and outputs the result including the sign as the preliminary burst timing difference 506, and at the same time outputs the strobe pulse 507. The arithmetic circuit 405 calculates the delay amount 317 of the reception variable delay circuit,
The delay amount 353 of the transmission variable delay circuit is latched by the burst synchronization start signal 343 and held thereafter.
Also, calculate D _T − _DR by assuming that the delay amount of the reception variable delay circuit is D _R and the delay amount of the transmission variable delay circuit is _DT .
The magnitude of this result is output to 510, and the sign is output to 511. This sign is “1” when D _T −D _R is positive;
If D _T - D _R is negative, it becomes "0". Further, the arithmetic circuit 404 latches the data burst timing difference 504 with a strobe pulse 505 and the preliminary burst timing difference 506 with a strobe pulse 507. At the same time, the data burst timing difference is E _D ,
When the transmission route selection signal 354 is "0", that is, when the data burst is transmitted to route 1, assuming that the preliminary burst timing difference is E _S ,
E _S - E _D is calculated, and if the transmission route selection signal 354 is "1", that is, the data burst is route 2.
, calculate E _D −E _S ,
Its magnitude is output 508 and its polarity sign is output 5
Output on 09. This polarity sign is "1" if each calculation result is positive, and "0" if it is negative.

When the mode selection signal 347 is "0", the selectors 406 and 407 respectively output the input A and the output Q.
Therefore, the value E _S - E _D or E _D - E _S calculated from the timing difference between the data burst or preliminary burst described above is outputted to the down counter 4.
08 and AND gates 421 and 423 as signals 512 and 513, respectively, and when the mode selection signal 347 is "1", the selector 40
6 and 407 output the input B as the output Q, so the above-mentioned D _T -D _R is supplied as the signal 512 and the signal 513. If only the burst synchronization start signal 343 is input, the operation ends up to this point and the value of the delay counter 410 does not change.

Next, the transmission variable delay control start signal 345
A case will be described in which a pulse with a width of one frame is input.

The transmission variable delay control start signal 345 is ANDed with the output 522 of the frame counter, and the output 51
4 becomes the load pulse of the down counter 408. calculated earlier by this load pulse.
D _T - _DR or E _S - E _D or E _D - E _S is loaded into down counter 408. This value is output 51
5 to the decoder 409, and the decoder 40
9 sets 516 to "1" if the output 515 is not "0". As a result, the transmission variable delay control signal 346 becomes "1".

Comparison circuit 411 is an 1-bit comparison circuit. l represents the number of digits expressed in binary notation by the number of symbols N+1 in one frame. Also, n in Figure 4 is
This corresponds to the number of digits when the maximum value of the delay amount of the transmission variable delay circuit is expressed in binary. Normally, l≧n, so when l>n, the remaining high-order digits on the delay amount 353 side are connected to be “0”. As a result, this comparison circuit 411 outputs a timing pulse corresponding to the beginning of the frame when the transmission timing becomes equal to the delay amount of the transmission variable delay circuit, that is, when viewed from the output side of the transmission variable delay circuit.

This timing pulse 525, the output of the previous deducer 409 and the output 513 of the selector 407
The output of the delay counter 410 is connected by an AND gate and an inverter, and when the value calculated by the arithmetic circuit is positive, it is input as the down clock of delay counter 410, and when it is negative, it is input as the up clock. Therefore, if the calculated value is positive, the delay amount is reduced by one symbol per frame at the beginning of the frame as viewed from the output side of the transmission delay circuit.
If the calculated value is negative, the amount of delay is increased.

Also, this timing pulse 525 is the output 51
9 is fed back to the down counter 408, and if the calculated value is E _CORR , the value of the down counter becomes "0" when the E _CORR frame occurs, and the output 516 of the decoder 409 returns to "0", and no further transmission is possible. The delay amount of the delay circuit is no longer corrected. At the same time, when the transmission selection signal 354 is "1", that is, when the data burst is being transmitted from route 2, the signals 521 and 52
0 is added to the transmission frame counter 401 as signals 523 and 524. In this way, when the delay counter increases by 1 symbol per frame, the transmission timing is advanced by 1 symbol per frame, and when the delay counter decreases by 1 symbol per frame,
The transmission timing is delayed by one symbol per frame. As a result, the timing of the data burst does not change when viewed from the output side of the transmission variable delay circuit.

A microprocessor can be applied to the various controls described above. Even with the processing speed of microprocessors currently available on the market, the low-speed parts of the synchronous control circuit, transmission switching circuit, transmission timing, and transmission variable delay control circuit, for example, can be realized by software. In this case, the hardware will be much smaller than if it were made up of individual logic circuits. The above description has been given by exemplifying the case where there are two antennas, but when there are three or more antennas, the following applies. In other words, signal reception is performed using all antennas, and the quality of the received signal is
Count and monitor errors such as LUW. Normally, two antennas are used to transmit signals, and the operation described above is performed. In this manner, in the above-described operation, when the transmission of the preliminary burst is stopped, acquisition can be performed by transmitting the preliminary burst through the antenna with the best reception condition among the antennas that are not transmitting signals.

As explained above, according to the present invention, TDMA signals are transmitted using a route with good communication conditions, either the route with a fixed delay circuit (route 1) or the route with a variable delay circuit (route 2). When the other route becomes available for communication, the timing of the data burst is corrected without moving on the satellite so that the propagation delay time of both routes is equal, and the route with good communication conditions is selected. and can be switched without interruption. According to the present invention, there is no need to consider the conventional route including a variable delay circuit as a preliminary route, and both routes can be considered equally when switching.

When the present invention is used for satellite communication, particularly when a high frequency of 10 GHz or more is used, a particularly large effect can be expected. The present invention can also be used for digital communication using space diversity for moving objects other than communication satellites.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional transmission route length equalizer. FIG. 2 is an explanatory diagram of a TDMA signal with a diversity configuration. FIG. 3 is a block diagram of a transmission route length equalizer according to an embodiment of the present invention. FIG. 4 is a block diagram of a transmission timing and transmission variable delay control circuit according to an embodiment of the present invention.

Claims (1)

[Claims] 1. In a transmission route length equalizer for a time division multiple access (hereinafter referred to as "TDMA") communication system that has a diversity configuration using multiple antennas, a predetermined length equalization device is used for a signal transmitted from one of the multiple antennas. means capable of imparting a fixed amount of delay, means capable of imparting a delay amount that can be arbitrarily set to a signal transmitted from at least one antenna of the plurality of antennas, and TDMA for a route passing through each antenna;
means for detecting a timing difference from a terminal station to a repeater; and means for controlling TDMA signal transmission timing; and means for applying a data burst to any one of the plurality of antennas; and means for controlling the TDMA transmission timing so that the timing of the data burst passing through the repeater remains unchanged by changing the amount of delay given to the signal to be transmitted, at the same time changing the TDMA transmission timing. Equalizer.