JPS6337986B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention receives a plurality of orthogonally multiplexed quadrature amplitude modulation (hereinafter referred to as QAM) signals via a transmission line, samples them, and converts them into analog-digital (hereinafter referred to as QAM) signals.
A digital processing receiving device for orthogonal multiplexed signals that demodulates multiple source baseband (hereinafter referred to as baseband) signals by performing AD (abbreviated as abbreviated) conversion, wave manipulation, and discrete Fourier transform (hereinafter referred to as DFT) operations, etc. This invention relates to a pilot phase control circuit. The orthogonal multiplex transmission method, in which multiple QAM signals are orthogonally multiplexed and transmitted, and each baseband signal is demodulated on the receiving side, enables highly efficient data transmission.Moreover, by introducing DFT into the digital signal processing process, transmission and reception are possible. It has already been proposed that the device can be significantly simplified (for example, patent application no.
150238, 1978 Patent Application No. 19364 and 1978
(Please refer to the specification of Patent Application No. 19366). However, conventionally, no simple configuration regarding demodulation carrier phase control on the receiving side of the orthogonal multiplex transmission system has been proposed. In view of this point, it is an object of the present invention to provide a pilot phase control circuit for a digital processing receiving apparatus for orthogonal multiplexed signals, especially when a pilot is inserted into a predetermined channel on the transmitting side for transmission. Next, the present invention will be explained in detail with reference to the drawings. Figure 1 is a diagram showing the spectrum arrangement of transmission signals in the orthogonal multiplex transmission system, where the reference number 1 indicates the first signal modulated by a complex carrier with a frequency of ₁ .
QAM signal, reference number 2 is the second QAM signal modulated with a complex carrier of frequency ₂ , reference number 3 is frequency _N-1 (however, N≧3 here)
The (N-1)th modulated by the complex carrier
The QAM signal, reference numeral 4, is a pilot signal with frequency _N. However, according to the principle of orthogonal multiplex transmission system, it is assumed that the following relationship holds: _k+1 - _k = _B (1≦k≦N-1, _{and B} is the baud rate of each baseband signal). . On the receiving side, each QAM is
The signal is demodulated to obtain a complex baseband signal, and in this demodulation process, N demodulation carriers are generally required corresponding to the N modulation carriers. However, if demodulation processing on the receiving side is performed by digital signal processing using DFT, the phase of the sampling clock is simply controlled using the phase information of the complex baseband signal obtained by demodulating the pilot signal. It is possible to equivalently control all demodulation carriers. Now, the received signal is y
(t), y(t) is expressed as follows. y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt } …(1) However, x _o (t) is a complex baseband signal modulating a modulation carrier with frequency _o . be. Let Y(z) be the output obtained by sampling y(t) with a sampling clock having a frequency _s (where _s = Mf _B ). However, Z=e ^j2 〓 ^f/fn . At this time, the k-th demodulated complex baseband signal β _k (z) is expressed as β _k (z)=Y(e ^−j2 〓 ^fk/fsz ) G(z) (2). However, 1≦k≦N, and G(z)
is a low frequency filter with an effective band of _B /2 on one side. Here, Y(z) and G(z) are demultiplexed as follows. That is, At this time, equation (2) is The sequence of sample values of β _k (z) every T/2 seconds (T=1/ _B ), _β˜k (z ^M/2 ), is given by the following equation. Here, if we use the relationships f _k = f ₁ + (k-1) f _B and f _s = Mf _B , we get The signal processing expressed by equation (7) is performed using a preprocessing circuit as described in Patent Application No. 150238 of 1972,
This is achieved using DFT processing circuits, polyphase circuits, etc. According to this configuration, the multiplication coefficient e ^-j2 〓 ^(k-1)l/M in the DFT processing circuit is the sampling frequency _s
The frequency offset term e ^-j2 〓 ^f1/fs is also determined by the ratio of ₁ and _B predetermined on the transmitting side (e ^-j2 〓 ^f1/fB ) ^1/M as read-only memory, In other words, it is sufficient to store it in a read-only memory (hereinafter abbreviated as ROM) or the like. Therefore, all demodulation carriers ₁ , ₂ ..., _N are frequencies _s
It is generated from the sampling clock of Here, the phase shift between the k-th modulation carrier and the k-th demodulation carrier is defined as θ _k (t), and this is regarded as the phase shift of the modulation carrier with respect to the demodulation carrier. In this case, equation (1) is expressed as y(t)=2Re{ _N 〓 ⁿ⁼¹ x _o (t)e ^-j2 〓 ^fnt+j 〓 ^n(t) }...(8). Here, as described above, since a pilot signal with frequency _N is inserted into the Nth channel, x _N (t)=1. Therefore,
The demodulated output of the Nth channel is obtained from equations (6) and (8) as follows (taking into account the band-limiting effect of filter G(z)). Figure 2 shows the spectrum of β~ _N (z ^M/2 ) expressed by equation (9), and reference numeral 5 indicates (9).
In the bright line spectrum obtained as the average of the first term of the equation, reference numeral 6 is the spectrum broadening due to phase noise, and reference numeral 7 is the interference from the adjacent channel expressed by the second term of equation (9). As is clear from FIG. 2, if β~ _N (z ^M ₂ ) is passed through a low-pass filter having a pass characteristic as shown by reference numeral 8, the signal γ _N (z ^M/2 ) obtained as its output. is the first of equation (9)
It is expressed by the following equation. However, φ _N (t)=e ^j 〓 ^N(t) . φ _N (t) to T _s
If we let φ _N (z) be the z-transformed sample value sequence sampled every second, then from equations (10) and (4), γ _N
(z ^M/2 ) is after passing φ _N (z) through filter G(z),
It can be seen that the regulations are based on sample values taken every T/2 seconds. Here, G(z) is a low-pass filter, and the band of φ _N (z) is usually sufficiently narrow compared to the band of G(z), so γ _N (z ^M/2 ) is eventually reduced to φ _N (z ), it can be seen that the sample value series is obtained by extracting sample values every T/2 seconds. That is, Therefore, a sample value sequence with a phase error θ _N (t) can be obtained from the complex sample value sequence γ _N (z ^M/2 ). By the way, it is clear from the signal processing process that the phase shift θ _N (t) follows the phase shift θ _s (t) from the normal phase of the sampling clock and is expressed as θ _N (t) = (f ₁ /f _s +N-1/M) θ _s (t)…(12) Therefore, the sample value of θ _N (t) is θ _s
(t) is proportional to the sample value. Therefore, γ _N
By controlling a voltage controlled oscillator with an oscillation frequency _s using the sample value of θ _N (t) obtained from (z ^M/2 ) and using its output as a sampling clock, a phase-controlled sampling clock can be obtained. Therefore, it is possible to equivalently control the phase of all demodulation carriers. The present invention is based on the above principle, and provides a novel pilot phase control circuit that does not require a phase comparison circuit, a frequency division circuit, etc., which are required in a normal phase synchronization circuit. FIG. 3 is a block diagram showing one embodiment of the present invention. One embodiment shown in FIG. 3 includes an input terminal 10, a sampling circuit 11, an AD converter 12, and a pre-processing described in the specification of Patent Application No. 150238 of 1982 of an orthogonal multiplexed signal digital processing receiver. It includes a digital arithmetic processing section 13 including a polyphase circuit, a DFT processing circuit, etc., output terminals 14 and 15, low-pass wave circuits 17 and 18, a phase difference detection circuit 19, and a voltage controlled oscillation circuit (VCO) 20. The part surrounded by the broken line 16 is a conventionally known processing part,
The remaining portions constitute the pilot phase control circuit of the present invention. In FIG. 3, a signal received at an input terminal 10 is sampled by a sampling circuit 11 using a sampling clock of frequency _s , and digitally encoded by an AD converter 12. Further, this digitally encoded signal is subjected to the demodulation process as described above in the digital arithmetic processing section 13, and the output terminals 14 and 15 receive signals β~ ₁ (z ^M/2 ), β expressed by equation (7). ~ ₂ (z ^M/
2 )
is output. On the other hand, β~ _N (z ^M/2 ) containing the demodulated complex pilot signal given by equation (9) has its real part and imaginary part passed through the low-pass wave circuits 17 and 18, respectively, and is expressed by equation (11). The complex signal γ _N (z ^M/2 ) represented
is converted to The phase difference detection circuit 19 detects a phase difference from the complex signal γ _N (z ^M/2 ), converts it into an analog quantity, and uses it as a control voltage for the voltage controlled oscillator 20 . Through this control, the sampling circuit 11 is supplied with a phase-controlled sampling clock from the voltage controlled oscillator 20. FIG. 4 is a circuit diagram showing a specific example of the configuration of the phase difference detection circuit 19 shown in FIG. 3. Input complex signal γ _N
A digital code representing the real part of (z ^M/2 ) is input to the address section of the ROM 23 from an input terminal 21, and a digital code representing the imaginary part from the input terminal 22. The ROM 23 stores the correspondence between the complex quantity of γ _N and the phase quantity. For example, if the real part of γ _N is
0.500, and the imaginary part of γ _N is 0.866, then the phase amount θ is
It becomes 1.047 radian. Since the maximum absolute value of the phase amount θ is π radian, if θ is normalized and expressed by π, the relationship between the address of the ROM 23 and the output is expressed as shown in the following table, for example (however, if the digital All codes are assumed to use two's complement representation).

[Table] Furthermore, the digital output of the ROM 23 is converted into an analog quantity by a digital-to-analog converter (hereinafter abbreviated as DA converter) 24, and the output terminal 2
5. At this time, there is a relationship between the phase amount θ and the DA output as shown in Figure 5, which is a tooth-tooth function, and the input/output characteristics are equivalent to that of a phase comparator using a normal set-reset flip-flop. It will be shown. In the above example of the ROM 23, it is assumed that the absolute value of the complex input γ _N is always 1, but if this absolute value is not kept constant due to fluctuations in line (transmission path) loss. so as to obtain a phase difference output according to the ratio of the real part and imaginary part of γ _N
All you have to do is set the contents of the ROM. Now, in one embodiment of the present invention shown in FIG. 3, from the real part and imaginary part of γ _N as described above,
I am getting the VCO control signal. This makes it possible to obtain an appropriate VCO control signal even if the absolute value of γ _N changes due to, for example, line fluctuations or line variations. Here, if the level of γ _N is kept at a constant value by an automatic gain control circuit (hereinafter abbreviated as AGC circuit), etc., then even simpler pilot phase control can be performed using only the imaginary part of γ _N. A circuit can be constructed. FIG. 6 is a block diagram showing a second embodiment of the present invention based on the above principle. In FIG. 6, the received signal input to the terminal 27 is compensated for loss fluctuations in the line by the AGC circuit 28, and then sent to the sampling circuit 29.
It is sampled by a sampling clock of frequency _s at .
The output of the sampling circuit 29 is further digitally encoded by the AD converter 30 and sent to the digital arithmetic processing section 3.
1, the signal is subjected to demodulation processing similar to that in the digital arithmetic processing section 13 of FIG. β ~ _N of equation (9) obtained as one output of the digital arithmetic processing unit 31
(z ^M/2 ), only its imaginary part is the low-pass wave circuit 3
5, and the imaginary part of γ _N (z ^M/2 ) expressed by equation (11) is obtained as its output. The phase difference detection circuit 36 detects a phase difference from the imaginary part of γ _N (z ^M/2 ) thus obtained, converts it into an analog quantity, and uses it as a control voltage for the voltage controlled oscillator 37 . Through this control, the sampling circuit 29 is supplied with a phase-controlled sampling clock from the voltage controlled oscillator 37.
Note that the circuit inside the broken line 34 is a combination of conventionally known techniques, and the circuit outside the broken line is the pilot phase control circuit of the present invention. Here, phase difference detection circuit 3
If 6 is configured, for example, only by a DA converter, it is possible to obtain a pilot phase control circuit whose characteristics are equivalent to a phase-locked loop using a conventional sine wave phase comparator. In addition, the phase difference detection circuit 36
However, if it is constructed by continuously connecting a ROM exhibiting inverse sine function characteristics and a DA converter, a pilot phase control circuit equivalent to a phase-locked loop having triangular wave phase comparison characteristics can be obtained. As described above, according to the present invention, a pilot phase control circuit in a digital processing receiver for orthogonal multiplexed signals can be obtained with a simple circuit configuration. Note that in the configuration shown in Figure 6, the AGC circuit is installed before the sampling circuit, but this
Even if it is replaced with a digital AGC circuit operating on the output side of the converter, the essence of the present invention does not change at all.
Furthermore, it is clear that the present invention can be applied even if the control signal for such an AGC circuit is generated from a demodulated pilot signal.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the spectral arrangement of transmission signals in the orthogonal multiplex transmission system targeted by the present invention, where 1 is the first QAM signal modulated by a complex carrier with a frequency of ₁ , and 2 is a complex carrier with a frequency of ₂ . 3 was modulated with a complex carrier of frequency _N-1 (N-1)
The th QAM signal, 4, is a pilot signal with frequency _N. FIG. 2 shows the demodulated signal spectrum of the Nth channel, where 5 represents a desired pilot component, 6 represents a phase noise spectrum, and 7 represents a spectrum of interference from an adjacent channel. FIG. 3 is a block diagram showing an embodiment of the present invention, and inside the 16 broken lines are 11 sampling circuits,
This is a conventionally known demodulation processing unit consisting of 12 AD converters, 13 digital arithmetic processing units, etc.
7 and 18 are low-pass wave generators, 19 is a phase difference detection circuit, and 20 is a voltage controlled oscillation circuit. FIG. 4 is a circuit diagram showing a specific embodiment of the phase difference detection circuit indicated by 19 in FIG. 3, and 23 is a ROM for associating the phase amount with the input complex amount. FIG. 5 is a diagram showing an example of phase comparison characteristics equivalently obtained by the phase difference detection circuit 19 of FIG. FIG. 6 is a block diagram showing a second embodiment of the present invention, in which 35 is a low-pass wave generator, 36 is a phase difference detection circuit, and 37 is a voltage controlled oscillator.

Claims (1)

[Claims] 1. A plurality of orthogonally multiplexed orthogonal amplitude modulated signals are received via a transmission line, and a plurality of source basebands are obtained by sampling, analog-to-digital conversion, wave manipulation, discrete Fourier transform operations, etc. In a pilot phase control circuit for a digital processing receiving device for an orthogonal multiplexed signal that demodulates a signal, a first low frequency component is used to remove unnecessary frequency components from the real part of the demodulated output corresponding to a channel in which a pilot is inserted in advance on the transmitting side. a pass pass wave generator, a second low pass wave generator that removes unnecessary frequency components from the imaginary part of the demodulated output, an output of the first low pass wave generator and the second low pass wave generator. a phase difference detection circuit that detects a phase error in the pilot frequency using the output of the phase difference detection circuit; and a voltage control circuit whose oscillation frequency is controlled by the output of the phase difference detection circuit and whose output is used as a sampling clock for the sampling. 1. A pilot phase control circuit in a digital processing type receiver for orthogonal multiplexed signals, characterized in that the pilot phase control circuit is comprised of an oscillation circuit. 2. Receive multiple orthogonally multiplexed orthogonal amplitude modulated signals via a transmission line, and demodulate multiple source baseband signals by automatic gain control, sampling analog-to-digital conversion, wave manipulation, discrete Fourier transform operations, etc. In a pilot phase control circuit for a digital processing receiver for orthogonal multiplexed signals, a low-pass waver removes unnecessary frequency components from the imaginary part of a demodulated output corresponding to a channel in which a pilot is inserted in advance on a transmitting side; A phase difference detection circuit detects a phase error in the pilot frequency from the output of the low-pass wave generator, and the oscillation frequency is controlled by the output of the phase difference detection circuit, and the output thereof is used as the sampling clock for the sampling. 1. A pilot phase control circuit in a digital processing receiver for orthogonal multiplexed signals, comprising a voltage controlled oscillation circuit.