JPS6338894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic circuit, and particularly to a frequency divider circuit configured with complementary MISFETs (insulated gate field effect transistors).

The frequency divider circuit has the function of reducing the frequency of the input clock pulse to a predetermined frequency division ratio.
The most basic circuit is constructed so that the inverted output of a D-type (delayed) flip-flop is fed back to the D input. Furthermore, even if the D type flip-flop is replaced with a 1-bit shift register, the operation is equivalent. Shift registers in integrated circuits are divided into two types: static type and dynamic type. Of these, the static type shift register uses a bistable circuit as a storage circuit, and can operate no matter how low the frequency of the clock pulse is. On the other hand, a dynamic shift register has a shift circuit configuration that uses the input capacitance of the next stage as a storage means. Therefore, clock pulses must be constantly applied (refreshed) at a frequency higher than a predetermined frequency, but because the number of components is small and there is no through current, power consumption is low, so it is used in relatively high-speed applications. There are many things.

FIG. 1 is an example of a 1/2 frequency divider circuit constructed using a conventional dynamic shift register. Second
Using the time chart shown in the figure, the operation during the temporal changes t ₁ and t ₂ of the clock pulse will be explained step by step.

MP1 to MP4 in Figure 1 are P channel type
MISFET, MN1 to MN4 are n-channel type
MISFET, MP2 and MN2 and MP4 and MN4
constitute a half-bit shift register, A ₁ ,
_A2 operates as a 1-bit shift register by cascading the output points as shown in the figure. Further, MN1, MP1, MN3, and MP3 are drive transistors whose opening and closing are controlled by a clock pulse CP and its inverted pulse. When clock pulse CP is “H” level, reverse phase clock pulse
CP becomes “L” level, MISFET MP1,
Both MN1 are conductive, and MISFET MP3,
Both MN3 become non-conductive (high impedance state), and the voltage value charged in the input capacitance of the next stage inverter _A3 is held at the output terminal _A2 .
The time when the "H" state is now held at the output terminal _A2 is defined as time _t1 . When the clock pulse CP falls at time t ₂ , the reverse phase clock pulse becomes "H" level, MISFETs MP1 and MN1 are both non-conductive, MP3 and MN3 are both conductive, and the output terminal _A1 is in the "H" state at time t ₁ . is held, so the outputs of output A ₂ and inverter I ₂ are each “L”
The level becomes "H" level. The state of each inverter when the clock pulse CP changes from the "H" level to the "L" level has been explained above, but in such a shift register, the clock input and signal input do not change at the same time, so the through current are very few. However, in the circuit shown in Figure 1, a through current flows through the inverter _I2 , and the rise and fall times of the reverse phase clock pulse are compared to the signal transmission time so that the inverter _I1 operates in an inverted manner to prevent malfunctions due to the pierce phenomenon. Since it is necessary to speed up the time, the channel width of the inverter _I1 is inevitably increased, and an even larger through current flows through the inverter _I1 .

In this way, conventional frequency divider circuits use a dynamic type shift register with low power consumption, but in addition to the dynamic type shift register, a static type inverter _I2 and a clock driver I to generate two clock pulses with opposite phases to each other are used. ₁ , and it was not possible to reduce power consumption sufficiently.

An object of the present invention is to provide an electronic circuit having a frequency dividing function with low power consumption and a small number of elements.

An electronic circuit according to the present invention includes first and second power supply voltage terminals different from each other, a first transistor of one conductivity type connected between the first power supply voltage terminal and a first node, and a second transistor connected between the first power supply voltage terminal and the first node. second and third transistors of opposite conductivity type connected in series between the power supply voltage terminal and the first node; and transistors of one conductivity type connected between the first power supply voltage terminal and the second node. a fourth transistor, and fifth and sixth transistors of opposite conductivity types connected between the second power supply voltage terminal and the second node;
seventh and eighth transistors of one conductivity type connected in series between the first power supply voltage terminal and the third node; a ninth transistor of conductivity type;
A clock pulse is applied to the gates of the first, third, sixth and eighth transistors, the gates of the second transistor are connected to the third node, the gates of the fourth and fifth transistors are connected to the first node, and the gates of the second transistor are connected to the first node, The gates of the transistors 9 are connected to the second node.

An embodiment of the present invention will be described in detail below using the drawings.

FIG. 3 is a circuit diagram of an embodiment in which the frequency dividing circuit of the present invention is configured as a 1/2 frequency dividing circuit, and FIG. 4 is a time chart for explaining its operation.

In the figure, MP11 to MP14 are P channel type.
MISFET, MN11 to MN15 are n-channel type
In the MISFET, the substrate potential (second gate) of the P-channel MISFET is connected to the _V1 power supply voltage terminal, while the n
Channel type MISFET substrate potential (second gate)
shall be connected to the _V2 power supply voltage terminals, respectively.
The explanation will be made using positive logic, with V ₁ being a positive power supply potential and V ₂ being a ground potential.

The circuit configuration of this embodiment has three terminals MP11, MN12, and MN11 between different power supply voltage terminals.
A first transistor circuit in which MISFETs are connected in series, a second transistor circuit in which MP12, MN14, and MN13 are connected in series;
A third transistor circuit has MP13 and MP15 connected in series, and the connection point between MP11 and MN12 of the first transistor circuit is _A11 , and the connection point between MP12 and MN14 of the second transistor circuit is A11. ₁₂ , MP13 of the third transistor circuit and
The connection point with MN15 is _A13 , and these three connection points are further connected as follows. That is, the connection point
A ₁₁ is MP12 and MN1 of the second transistor circuit
The connection point _A12 is connected to the gate of MP14 and MN15 of the third transistor circuit, and the connection point _A13 is fed back and connected to the gate of MN12 of the first transistor circuit. .
Further, a single-phase clock pulse CP is applied to the gates of MP11 and MN11 of the first transistor circuit, to the gate of MN13 of the second transistor circuit, and to the gate of MP13 of the third transistor circuit.
are configured to be commonly supplied to the respective gates. As is clear from the figure, the transistor circuits in each stage are of P-channel and N-channel type.
One inverter circuit composed of MISFET,
P channel or N channel type MISFET
It is equipped with one control transistor consisting of.

The operation of the 1/2 frequency divider circuit of this embodiment will be explained with reference to the time chart of FIG. As mentioned above, the _V1 power supply voltage level is set to H level, and the _V2 power supply voltage level is set to L level.

Now, if the clock pulse CP to be frequency-divided is at L level during a certain period _P1 , MP11 of the first transistor circuit is conductive and MN11 is cut off, so that the connection point _A11 is at H level. on the other hand,
During this period, the potential at the connection point _A11 is supplied to the gate of the inverter of the second transistor circuit.
Since the second transistor circuit MN13 is in a cut-off state, the connection point _A12 maintains the previous voltage level state.

Next, in period _P2 , when the clock pulse CP becomes H level, MN13 and MN of the second transistor circuit
14 are both conductive, and MP12 is cut off, so that the connection point _A12 becomes L level, making MP14 of the third transistor circuit conductive. Therefore, when the clock pulse CP becomes L level in the next period _P3 , the connection point _A13
becomes H level and makes the control transistor MN12 of the first transistor circuit conductive. After performing the above initialization operation, when the clock pulse CP changes to the H level (period _t1 ), the connection point _A11 goes to the L level.
level, and MP1 of the next stage transistor circuit
2 is forcibly made conductive, and the potential at the connection point _A12 is set to H level. As a result, MP14 and MN15 of the third transistor circuit are cut off and turned on, respectively, so that the connection point _A13 becomes L level, and MN12 of the first transistor circuit is forcibly cut off. Furthermore, in the next period _t2 , the clock pulse CP goes low.
When the level is reached, the connection point A ₁₁ of the first transistor circuit becomes H level, but since MN13 is cut off in the second transistor circuit, the connection point A ₁₂ as its output terminal remains in the previous state, that is, the H level. hold. Therefore, the output level of the connection point _A13 does not change, and the L level output remains during this period _t2 . Next, when the clock pulse CP rises to the H level in period _t3 , the connection point _A11 of the first transistor circuit, where MN12 is in the cutoff state, is set to a high impedance state, but the gate of the next stage transistor MN14 is set to the high impedance state. The H level is maintained until the accumulated charge is discharged. On the other hand, since the clock pulse CP is also at H level at this time, the second
MN13 of the transistor circuit is conductive and the connection point
_A12 changes to L level. Furthermore, when the clock pulse CP goes to the L level in period _t4 , the connection point _A13 of the third transistor circuit outputs the H level because both MP14 and MP13 are conductive and MN15 is in the cut-off state, and the first transistor circuit outputs the H level. The control transistor MN12 of is made conductive. Next, in period _t5 , when the clock pulse CP changes to the H level, the connection point _A11 goes to the L level, and the connection point _A12 is shifted to the H level.

That is, as is clear from this operation, the connection point _A12 of the second transistor circuit is connected to the clock pulse.
If one cycle of CP is taken out, a frequency divided output of 1/2 can be obtained for the clock pulse. Here, since the rising or falling change time of the clock pulse CP is sufficiently faster than the operating time of each transistor circuit, the circuit may malfunction or a through current path may be formed between the power supply terminals _V1 and _V2 . do not have.

As described above, according to this embodiment, the number of elements constituting the 1/2 frequency divider circuit is 4 fewer than the conventional one, which is 2/3 of the conventional number of elements (9 elements). Therefore, the circuit itself can be miniaturized and manufactured at extremely low cost. Further, the power consumption is significantly reduced compared to the conventional device due to the small number of elements, the extremely limited through current path, and the fact that only one phase clock pulse is required.

Furthermore, according to the novel circuit configuration of the frequency divider circuit of the present invention, it is also effective as a 1/3 frequency divider circuit as shown in FIG.

In FIG. 5, the same reference numerals are used for the same circuit components as those of the 1/2 frequency divider circuit in FIG. Therefore, 1/3
In the frequency dividing circuit, simply add a fourth MP15, MN17, MN16 and a fifth MP17, MP16, MN18 transistor circuits similar to the second and third transistor circuits to the stage after the third transistor circuit in FIG. good. In this case, the output fed back to the gate of the control transistor MN12 of the first transistor circuit may be the potential of the connection point _A15 of the fifth transistor circuit.

The operation of such a 1/3 frequency divider circuit will be explained below with reference to FIG.

Similar to the 1/2 frequency divider circuit in Figure 3, first the period P ₁ ~
After the initialization operation of _P5 is performed, the frequency division operation is performed after the period _t1 . When the clock pulse goes to H level in period _t1 , the connection point _A11 of the first transistor circuit goes to L level, and the connection points _A12 , _A13 , _A14 , _A15 of the subsequent transistor circuits are forced to go to H level,
It is shifted to L, H, and L levels. In the period _t2 , the connection point _A11 changes to H level, and in the next period _t3 , the connection point _A12 is shifted to L level. At this time, the connection point _A13 of the third transistor circuit becomes a high impedance state, but the previous output level is
The level is maintained, and during period _t4 when the clock pulse CP falls to the L level, it is shifted to the H level. As a result, the connection point _A14 goes to the L level during period _t5 , that is, when the clock pulse CP goes to the H level, and in the next period _t6 , the connection point _A15 at the last stage is shifted to the H level, and the control transistor MN12 of the first transistor circuit conduction. Therefore, during the period _t7 when the clock pulse CP changes to the H level, the connection point _A11 is at the L level, and the connection points _A12 and _A13 are at the H and L level, respectively.
By taking out the divided output from this connection point _A13 , a frequency division ratio of 1/3 of the clock pulse CP can be obtained.

As is clear from this reference example, only one phase of clock pulse is required and no through current flows, so power consumption can be reduced and the number of elements can be reduced.

It is clear that any frequency division ratio can be obtained by connecting the second and third transistor circuits in series in this manner.

Furthermore, for example, as shown in Figure 7, 1/2 of Figure 3
If the third transistor circuit constituting the frequency dividing circuit is provided in the first stage, and the first and second transistor circuits are sequentially shifted to the subsequent stages, the output of the last stage transistor circuit will be as shown in FIG. can also be extracted as a 1/2 frequency divided output.

In this case as well, as in the embodiments shown in FIGS. 3 and 4, after the initialization operation during periods P ₁ to P ₃ is performed as shown in FIG. 8, the frequency division operation begins after period t ₁ .

In addition to this embodiment, for example, the gate electrodes of channels of the same type connected in series may be interchanged. Although the reset (preset) circuit is omitted in this embodiment, for example, one n-channel type MISFET can be replaced with an n-channel type MISFET.
Connect it in parallel with MISFETMN13, or connect it between the output of connection point _A12 and power supply terminal _V2 to set its gate electrode to H level, and clock pulse
This is possible by setting CP to H level.

Furthermore, the reset (preset) function is 1.
N-channel type MISFET
This can also be done by placing it in parallel with MISFETMN15 or by placing it between the output of the connection point _A13 and the power supply terminal _V2 so that its gate electrode is at H level and the clock pulse CP is at L level.

In this embodiment, we have explained how to take out the output to obtain a frequency division ratio of 1/n of the clock pulse, but as is clear from each figure, by taking out the output from any connection point, it is possible to obtain a frequency division ratio of 3/2n. It is clear that we can obtain a division ratio of ~2n−1/2n,
The usage range of divided output is expanded.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional 1/2 frequency divider circuit, FIG. 2 is a time chart thereof, FIG. 3 is a circuit diagram showing an embodiment of a frequency divider circuit according to the present invention, and FIG. 4 is a circuit diagram of a conventional 1/2 frequency divider circuit. Time chart of the frequency divider circuit shown in Figure 5.
FIG. 7 is a circuit diagram showing a reference example of a frequency dividing circuit using the present invention, and FIGS. 6 and 8 are time charts thereof, respectively. MP1~MP4, MP11~MP17...P channel type MISFET, MN1~MN4, MN11~
MN18...n channel type MISFET, CP...
Clock pulse, A...Connection point, _I1 , _I2 ...Inverter.

Claims (1)

[Claims] 1 first and second power supply voltage terminals having different power supply voltages, a first transistor of one conductivity type connected between the first power supply voltage terminal and a first node, and the second power supply voltage terminal; second and third transistors of opposite conductivity types connected in series between the voltage terminal and the first node; and one conductivity type connected between the first power supply voltage terminal and the second node. a fifth and sixth transistor of opposite conductivity types connected in series between the second power supply voltage terminal and the second node; seventh and eighth transistors of one conductivity type connected in series between the third node; and a ninth transistor of the opposite conductivity type connected between the second power supply voltage terminal and the third node. a clock pulse is applied to the gates of the first, third, sixth and eighth transistors, and the gate of the second transistor is applied to the third node, and the gate of the second transistor An electronic circuit characterized in that the gates of the transistors are connected to the first node, and the gates of the seventh and ninth transistors are connected to the second node.