JPS6339143B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digitally constructed framing circuit for distinguishing between odd and even fields of a video signal.

Helical scan VTR using a rotating head
As is well known, four servo systems are provided, such as a drum phase servo, a drum speed servo, a capstan phase servo, and a capstan speed servo. Conventionally, these servo circuits have generally used an analog control method, which has made it difficult to integrate them into ICs, and has caused problems such as changes over time and temperature characteristics. Therefore, recently, servo circuits using digital control methods have been developed and are being put into practice in some areas.

In the drum phase servo and capstan phase servo, a vertical synchronization signal extracted from a video signal during recording is used as a reference signal. That is, in a drum phase servo, an error voltage is obtained by comparing the phase of a vertical synchronization signal and a pulse obtained from a pulse generator installed in the drum, and in a capstan phase servo, an error voltage is obtained by comparing the vertical synchronization signal with a pulse obtained from a pulse generator installed in the capstan. The phase of the obtained pulse is compared to obtain an error voltage. Further, the digital servo circuit described above is provided with a reference oscillator, and the reference oscillator generates various clock pulses and reference signals and supplies them to predetermined circuits constituting each servo system.
This reference oscillator is driven at a subcarrier frequency and is reset by a vertical synchronization signal during recording or externally synchronized reproduction.

Although the vertical synchronization signal is extracted from the video signal by a vertical synchronization separation circuit, it may be necessary to identify whether the extracted vertical synchronization signal is for an odd field or an even field. For example, during assemble editing, there are cases where it is determined whether two signal fields connected at an editing point on a tape are odd or even. In such a case, identification is performed by obtaining a framing signal whose level is inverted for each field. This framing signal is used in the digital servo circuit described above to reset the reference oscillator during assembling and editing.

A conventional framing circuit for obtaining a framing signal, for example, compares the phases of the framing pulse obtained for each frame and the pulse inverted by the vertical synchronization signal, and if the two do not match N times in a row, The phase of the above pulse is inverted. Such a framing circuit is CR
Because it uses a mono-multiple circuit containing multiple components, it is difficult to integrate it into an IC, and it takes time and effort to adjust CR variations, and furthermore, there are problems such as malfunctions due to noise. In addition, although the number of times N mentioned above is said to be approximately 3, this requires the use of 3 monomultis, which makes adjustment difficult, and it is difficult to actually set N to 3. Ta. Therefore, conventional framing circuits also have problems in terms of accuracy.

The present invention is intended to solve the above problems, but before explaining the present invention, an outline of an embodiment of a digital servo circuit to which the present invention can be applied will first be explained with reference to FIGS. 1 to 3. The type of helical scan VTR to which this servo circuit is applied is not particularly limited, but here we will discuss the case of a two-rotating, 180° omega-wound type VTR.

FIG. 1 shows a circuit for generating an error signal for controlling the circuit phase and rotational speed of a rotating drum and a capstan, and FIG. 2 shows a circuit for a motor drive section that is controlled in response to the error signal. In this servo circuit, in order to detect the phase and speed of the drum and capstan, a PG (pulse generator) is installed on the drum and the capstan is equipped with a PG (pulse generator), as in the past.
A FG (frequency generator) is provided.

As shown in FIGS. 2 and 3, six magnets 2 are arranged on the bottom of the drum 1 to which the A head and B head are attached, and one magnet 3 is placed inside the drum 1. They are arranged at predetermined angular intervals. Further, two heads 4 and 5 are arranged close to each other on the rotating circumference of the magnet 2 with an interval of 30° to 40°,
A head 6 is arranged close to the rotating circumference of the magnet 3. These magnets 2, 3 and heads 4, 5 constitute the above-mentioned PG. According to the above configuration,
When the drum 1 rotates, the interval between the approximately 180 Hz pulse SPG _A signal and the SPG _B signal obtained from the heads 4 and 5 represents the speed of the drum 1. Further, the period of the approximately 30 Hz pulse PPG signal obtained from the head 6 represents the phase of the drum 1.

On the shaft of the capstan 8 for running the tape 7, there is a disk 9 whose circumferential surface is magnetized with a predetermined circumference.
is provided. Heads 10 and 11 are arranged adjacent to this disc 9. These disks 9 and heads 10 and 11 constitute the above-mentioned FG.
According to this configuration, the interval between the 360 Hz or 450 Hz pulse FG _A signal and the FG _B signal obtained from the heads 10 and 11 represents the speed of the capstan 8. Further, the CTL signal recorded on the control track of the tape 7 is detected by the CTL head 12. This CTL signal is used for capstan phase servo during playback.

The circuit shown in FIG. 1 is divided into a digital part surrounded by a dotted line and an analog part, both of which are formed on the same LSI chip. This circuit is basically obtained from each head in Figure 2.
In response to pulses from SPG _A , SPG _B , FG _A , FG _B , CTL, etc., a counter counts the clocks added to these pulse intervals, and this count value determines the output duty ratio of the PWM circuit (pulse width modulation circuit). The configuration is such that this PWM output is output from the LSI as an error voltage. For this purpose, a reference oscillator 15 is provided, and the reference oscillator 15 generates the above-mentioned clocks of various frequencies and supplies them to each counter. This reference oscillator 15
In addition to the above clock, it also generates the necessary reference pulses, and during recording or externally synchronized playback, a subcarrier signal SC obtained from the burst of the video signal is generated.
is driven as a clock, and self-oscillates during playback in modes other than external synchronization mode.

In the drum speed servo system, the flip-flop 16 is set by the SPG _A signal through a variable delay circuit 17 and reset by the SPG _B signal. Therefore, the output pulse width of this flip-flop 16 corresponds to the speed of the drum, and the DS counter (drum speed counter)
18 to count the clocks. By controlling the output duty ratio of the PWM circuit 19 using this count value, an error voltage DSPWM signal for drum phase servo is obtained through the buffer amplifier 20. Note that the frequency adjustment voltage Ec ₁ is applied to the variable delay circuit 17 to adjust the frequency of the _SPGA signal.

In the drum phase servo system, the flip-flop 21 is set by the PPG signal through the variable delay circuit 22 and reset by the 30 Hz reference signal _SP1 obtained from the reference oscillator 15. Therefore, the output pulse width of this flip-flop 21 represents the phase of the drum, and with this pulse width,
A DP counter (drum phase counter) 23 is operated to count clocks. With this count value
By controlling the output duty ratio of the PWM circuit 24, the error voltage for drum phase control is
A DPPWM signal is obtained through contact a of the switch circuit 25 and the buffer amplifier 20. Note that the variable delay circuit 22 adjusts the phase of the PPG signal by applying the adjustment voltage _Ec2 . Further, the switch circuit 25 is switched to the contact b side in the special mode (slow motion, still, search mode, etc.). This switching is done by Schmitt circuit 26.
This is done by a switching signal SS applied through the switch. In this special mode, the H.AFCPWM circuit 27 outputs DPPWM so that the horizontal synchronizing signal PBH of the reproduced video signal is reproduced at regular time intervals.
I'm trying to get a signal. For this reason, this H.
A part of the output of the PWM circuit 24 is applied to the AFCPWM circuit 27, and a PBHD signal is also applied through the Schmitt circuit 26. In addition, 2 in Figure 1
All Schmitt circuits indicated by 6 are provided for noise countermeasures. The PPG signal is also used to create the switching signal SW for heads A and B. For this reason, the SPG _A signal and PPG signal
It is added to the PG extraction circuit 28. This circuit 2
8, the approximate center position of the PPG signal interval is detected,
This detection position is adjusted by the variable delay circuit 29 to adjust the voltage Ec ₃
After being adjusted by the oscillator, it is applied to the switching pulse oscillator 30. This oscillator 30 has a separate
A PPG signal is added, and a predetermined switching signal is generated based on this PPG signal and the above detection position.
SW is obtained. This signal SW is the vertical oscillator 49
This vertical oscillator 49 provides a vertical blanking pulse VBLK signal for controlling the signal system in the normal mode and a pseudo vertical synchronizing signal VD' in the special mode.

In the capstan speed servo system, the flip-flop 31 is set by the FG _A signal and reset by the FG _B signal. Therefore, this flip-flop 3
The output pulse width of 1 corresponds to the speed of the capstan, and the CS counter (capstan speed counter) 32 is operated with this pulse width to count the clocks. With this count value, PWM circuit 33
By controlling the output duty ratio of , an error signal CSPWM for capstan speed control is obtained. The clock frequency applied to the CS counter 32 can be switched in two ways by a switch circuit 34 depending on the set speed of the capstan. The speed of the capstan differs depending on, for example, one-hour recording/reproduction and two-hour recording/reproduction, that is, when the tape runs at 1x speed and when the tape runs at 1/2x speed. The clock frequency is switched by applying this speed setting signal SH to the switch circuit 34 via a speed setting circuit 35 consisting of a flip-flop or the like.

In the capstan phase servo system, during recording, the FC _B signal is divided into approximately 30
The signal frequency-divided to Hz is sent to the switch circuit 37's REC.
Reset flip-flop 38 via the ASS contact. Also, 30 obtained from the reference oscillator 15
The Hz signal SP ₂ sets the flip-flop 38 via the REC contact of the switch circuit 37.
In addition, the above signal SP ₂ is passed through the buffer amplifier 20.
It is recorded on the tape's control track as a REC/CTL signal. The above flip-flop 38
The output pulse width represents the phase of the capstan, and a CP counter (capstan phase counter) 39 is operated with this pulse width to count the clocks. By controlling the output duty ratio of the PWM circuit 40 using this count value, an error voltage CPPWM signal for capstan phase control is obtained. During playback, the SP ₂ signal sets the flip-flop 38 via the variable delay circuit 41 and the PB/ASS contact of the switch circuit 37, and the PB/CTL signal resets the flip-flop 38 via the PB contact. ,
A CPPWM signal is obtained. The variable delay circuit 41 receives the signal SP ₂ by applying the adjustment voltage Ec ₄
Adjust the servo reference position. The switch circuit 37 is connected to the gate 4 when the recording mode setting signal REC or the assemble editing mode setting signal ASS, which will be described later, is applied to the gate 4.
It is switched by adding it through 2.

The FG _A and FG _B signals are multiplied by a frequency four times by a multiplier circuit 43 and applied to a PWM circuit 44 and a capstan speed detection circuit 45, and a signal CSPWM (special) and a signal CS are obtained from these circuits. The signal CSPWM (special) is a capstan speed detection signal in the special mode, and the signal CS represents the magnification of the capstan speed.

During assemble editing, when the tape reaches the editing point, the lower contact of switch 37 moves from PB to
Switches to REC-ASS side. At this time, the frequency division counter 36 is reset by the PB/CTL signal, so that the transition between the CTL signal and the track joint is performed smoothly.

If the output of the reference oscillator 15 is required to be synchronized with the even and odd fields of the input video signal, the reference oscillator 15 is reset with a frame pulse from the frame detection circuit 47. This frame detection circuit 47 generates the above-mentioned frame pulse based on the vertical synchronization signal extracted by the vertical synchronization separation circuit 48 from the synchronization signal REC/SYNC signal of the input video signal, and operates when necessary according to the ON/OFF signal. be done.

Each error voltage obtained in the above manner is applied to each circuit shown in FIG. DSPWM signal and
The DPPWM signals are turned into DC voltages by integrating circuits 50 and 51, respectively, and are added by an adder 52. By applying this addition output to the servo motor 54 through the motor drive amplifier 53, the motor 5
4 phase and speed are controlled. CSPWM signal and
The CPPWM signal becomes a DC voltage in integrating circuits 55 and 56, respectively, and is added in an adder 57. This addition output is transmitted from contact a of the switch circuit 58 to the capstan motor 60 via the motor drive amplifier 59.
is added to control the phase and speed of this motor 60.

In the special mode, the switch circuit 58 is switched to the b contact side by the signal SS. Also
The CSPWN (special) signal is compared with the speed designation signal SCM in the control circuit 61, and the comparison output is applied to the motor 60 through the integration circuit 62, the switch circuit 58, and the amplifier 59, so that the motor 60 is controlled at the designated speed. Rotate.

Next, an embodiment of the framing circuit according to the present invention will be described with reference to FIG. Note that the circuit in Figure 4 is
This can be used as the frame detection circuit 47 shown in the figure.

The framing circuit shown in FIG. 4 is composed of a framing pulse generation circuit 63, a noise inhibition circuit 64, and a vertical synchronization separation circuit 65. The framing pulse generation circuit 63 includes an input terminal 66, a differential circuit 70 composed of an inverter 67, and an AND gate 69, a flip-flop 71, and an AND circuit 7.
2, counter 73, decoder 74, counter 7
5, an AND circuit 76, an inverter 77, and an AND circuit 79. Note that, for example, a 1 MHz clock pulse is applied to the counters 73 and 75 from the reference oscillator 15 shown in FIG. Noise inhibition circuit 6
4 is a flip-flop 81, an AND circuit 82,
83, counter 84, decoder 85, OR circuit 8
6 and an output terminal 87.

Next, the circuit operation of the framing pulse generating circuit 63 will be explained with reference to FIG.

Even field composite synchronization signal is input to input terminal 66.
Assume that SYNC is added. This SYNC
Signals include horizontal synchronization signals HD, EQ′, and vertical synchronization signals
VD ₀ and equalization pulse EQ, included. this
The SYNC signal is applied to a vertical synchronization separation circuit 65 and a vertical synchronization signal VD is extracted. This VD signal is taken out as representing a predetermined position during the VD ₀ signal period. The SYNC signal is also differentiated by a differentiating circuit 70 to obtain a differentiated pulse. . This differential pulse is applied to AND circuit 72 and resets flip-flop 71 at its falling edge. As a result, the _Q1 output of flip-flop 71 becomes "1".
(high level), the rising edge of the differential pulse resets the counter 73 through the AND circuit 72. After this, the _Q1 output becomes "0" (low level) at the falling edge of the differential pulse. When counter 73 is reset, it counts clock pulses, and this count value is decoded by decoder 74. The decoder 74 is about 3/4 of the time since the counter 73 was reset.
Set the flip-flop 71 with the output after H (H: horizontal scanning period) and set the _Q1 output to "1".
It is accomplished. As a result, the counter 73 is reset at every 1H rise of the signal SYNC, and this state is returned up to time _t1 . Decoder 74
Although the output at approximately 6/5H from reset is taken out from t1, the output at 6/5H cannot be obtained until time _t1 . SYNC signal
When _1H has elapsed since the counter 73 was reset at the rising edge at time t1, the period of the VD ₀ signal begins. Therefore, the approximate period from time t ₁ to the rise of the first EQ′ signal
The counter 73 is not reset for 1.5H. As a result, the decoder 74 obtains an output at a time point 6/5H after time _t1 . This output is not available for odd fields. That is, in the case of an odd field, the HD signal of the SYNC signal in _FIG . It will shift. As a result, the counter 73 is always reset every 1H, so the decoder 74 cannot obtain a 6/5H output. Note that a 6/5H output is obtained from the last equalization pulse EQ.

The 6/5H output obtained first in an even field resets the counter 75. This counter 75 is a frequency division counter for delay, and holds the output at "1" until a predetermined number of clocks are counted after the reset. This counter output and the VD signal are applied to an AND circuit 76, and this AND output is differentiated by a differentiation circuit 80, thereby obtaining a framing pulse FP.

This framing pulse is obtained in an even field for each frame, but if there is noise in the SYNC signal or the HD or EQ signal is missing, it may be output at the wrong position or in an odd field. or may not be output. In order to prevent such malfunctions, the framing pulse FP is applied to a noise prohibition circuit 64 to remove the influence of noise.

Next, the circuit operation of the noise inhibition circuit 64 will be explained with reference to FIG.

This noise inhibition circuit 64 obtains a framing signal as its _Q2 output by triggering the flip-flop 81 at the falling edge of the VD signal. This framing signal has a predetermined phase in a predetermined field at 1/2 period of the VD signal. In the framing pulse FP shown in Fig. 6, the pulse marked with ○ is the correct framing pulse obtained in an even field, and ×
The marked pulse is a pulse that appears in the wrong position. Further, the pulses marked with △ are framing pulses obtained because, for example, during the above-described assemble editing, even fields are input consecutively at the joint of the signals.

The flip-flop 81 is triggered by the fall of the VD signal, its Q ₂ output and pulse FP are applied to an AND circuit 82 , and its _{Q 2} output and the circle pulse FP are applied to an AND circuit 83 . As a result, the AND output of _{the two} outputs "1" and the pulse FP marked with a circle resets the flip-flop 81 and the counter 84 through the OR circuit 86, but the pulse marked with a circle resets the flip-flop 81 and the counter 84.
Flipflop 8 as long as FP is added
1 outputs a 1/2VD cycle framing signal to the output terminal 87 regardless of the reset. When the pulse FP marked with an × is added, this pulse FP and Q ₂
The AND output with the output "1" is counted as a count pulse by the counter 84, but the counter 84 is reset by the AND output with the next pulse FP marked with a circle and _two outputs. The _Q2 output also maintains the 1/2VD cycle. Even if there are two pulses FP marked with x in succession and there is no pulse FP marked with ○ between them, the counter 84 counts up to "2" and is reset, and the _Q2 output also does not change. When the pulses marked Δ are applied continuously, the counter 84 is reset when it counts "3", and at the same time, the flip-flop 81 is also reset, and the Q _2,2 output is inverted _. Therefore, in this case, the pulse FP marked with △ is not considered to be an incorrect pulse FP, but the phase of the frame is inverted, and the corresponding 1/2VD
A framing signal is obtained.

The present invention provides the composite synchronization signal in a period longer than approximately 1/2H period and shorter than approximately 1.5H period (for example, between 3/4H and 6/5H from signal HD) from the edge of the horizontal synchronization signal of the composite synchronization signal. edge detection circuits 70 to 74 that detect rising edges of signals; a gate signal generation circuit 75 that generates a gate signal for a predetermined period based on the output signal of the edge detection circuit; This relates to a framing circuit characterized in that it has a frame pulse forming circuit 76 that extracts a vertical synchronizing signal separated from the vertical synchronizing signal and outputs a frame pulse signal based on the extracted vertical synchronizing signal.

Further, the present invention compares the polarity of the flip-flop circuit output signal and the signal polarity of the frame pulse with the flip-flop circuit 81 which is triggered by the vertical synchronization signal separated from the composite synchronization signal, and the polarity of both is determined to be a predetermined value. A first reset signal forming circuit 83 outputs a first reset signal when there is a relationship, and a second reset signal outputs a second reset signal when the polarities of the two are not in a predetermined relationship a predetermined number of times in a row. Reset signal forming circuit 82, 8
4 and 85, and the flip-flop circuit and the second reset signal forming circuit are reset by the first or second reset signal, and the output signal of the flip-flop circuit is used as a framing signal. This relates to a framing circuit characterized by:

Therefore, according to the present invention, a circuit can be configured purely digitally without using CR. Furthermore, by using a counter, the number of times N described above can be reduced to three, so accuracy can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a digital servo circuit of a VTR to which the present invention can be applied, Fig. 2 is a circuit diagram of a motor drive section of a VTR, Fig. 3 is a bottom view of a rotating drum, and Fig. 4 is a diagram of the present invention. 5 and 6 are time charts of FIG. 4, respectively. In addition, in the code used in the drawing, 63
...Framing pulse generation circuit, 64...Noise inhibition circuit, 65...Vertical synchronization separation circuit, 71,
81...Flip-flop, 73, 84...Counter, 82, 83...AND circuit.

Claims (1)

[Scope of Claims] 1 Approximately 1/1 from the horizontal synchronization signal edge of the composite synchronization signal
an edge detection circuit that detects a rising edge of the composite synchronization signal in a period longer than a 2H period and shorter than approximately 1.5H period; and a gate signal that generates a gate signal for a predetermined period based on an output signal of the edge detection circuit. and a frame pulse forming circuit that extracts a vertical synchronization signal separated from the composite synchronization signal by the gate signal and outputs a frame pulse signal based on the extracted vertical synchronization signal. Framing circuit. 2 Approximately 1/ from the horizontal sync signal edge of the composite sync signal
an edge detection circuit that detects a rising edge of the composite synchronization signal in a period longer than a 2H period and shorter than approximately 1.5H period; and a gate signal that generates a gate signal for a predetermined period based on an output signal of the edge detection circuit. a generation circuit; a frame pulse forming circuit that extracts a vertical synchronization signal separated from the composite synchronization signal by the gate signal and outputs a frame pulse signal based on the extracted vertical synchronization signal; and the composite synchronization signal. A flip-flop circuit triggered by a vertical synchronization signal separated from a first reset signal forming circuit that outputs a second reset signal; and a second reset signal forming circuit that outputs a second reset signal when the polarities of the two do not have a predetermined relationship a predetermined number of times in a row; 1. A framing circuit characterized in that said flip-flop circuit and said second reset signal forming circuit are reset by said first or second reset signal, and said output signal of said flip-flop circuit is made into a framing signal.